sound/soc/stm/stm32_i2s.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  STM32 ALSA SoC Digital Audio Interface (I2S) driver.
   4  *
   5  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   6  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
   7  */
   8
   9 #include <linux/bitfield.h>
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/delay.h>
  13 #include <linux/module.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/regmap.h>
  17 #include <linux/reset.h>
  18 #include <linux/spinlock.h>
  19
  20 #include <sound/dmaengine_pcm.h>
  21 #include <sound/pcm_params.h>
  22
  23 #define STM32_I2S_CR1_REG       0x0
  24 #define STM32_I2S_CFG1_REG      0x08
  25 #define STM32_I2S_CFG2_REG      0x0C
  26 #define STM32_I2S_IER_REG       0x10
  27 #define STM32_I2S_SR_REG        0x14
  28 #define STM32_I2S_IFCR_REG      0x18
  29 #define STM32_I2S_TXDR_REG      0X20
  30 #define STM32_I2S_RXDR_REG      0x30
  31 #define STM32_I2S_CGFR_REG      0X50
  32 #define STM32_I2S_HWCFGR_REG    0x3F0
  33 #define STM32_I2S_VERR_REG      0x3F4
  34 #define STM32_I2S_IPIDR_REG     0x3F8
  35 #define STM32_I2S_SIDR_REG      0x3FC
  36
  37 /* Bit definition for SPI2S_CR1 register */
  38 #define I2S_CR1_SPE             BIT(0)
  39 #define I2S_CR1_CSTART          BIT(9)
  40 #define I2S_CR1_CSUSP           BIT(10)
  41 #define I2S_CR1_HDDIR           BIT(11)
  42 #define I2S_CR1_SSI             BIT(12)
  43 #define I2S_CR1_CRC33_17        BIT(13)
  44 #define I2S_CR1_RCRCI           BIT(14)
  45 #define I2S_CR1_TCRCI           BIT(15)
  46
  47 /* Bit definition for SPI_CFG2 register */
  48 #define I2S_CFG2_IOSWP_SHIFT    15
  49 #define I2S_CFG2_IOSWP          BIT(I2S_CFG2_IOSWP_SHIFT)
  50 #define I2S_CFG2_LSBFRST        BIT(23)
  51 #define I2S_CFG2_AFCNTR         BIT(31)
  52
  53 /* Bit definition for SPI_CFG1 register */
  54 #define I2S_CFG1_FTHVL_SHIFT    5
  55 #define I2S_CFG1_FTHVL_MASK     GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
  56 #define I2S_CFG1_FTHVL_SET(x)   ((x) << I2S_CFG1_FTHVL_SHIFT)
  57
  58 #define I2S_CFG1_TXDMAEN        BIT(15)
  59 #define I2S_CFG1_RXDMAEN        BIT(14)
  60
  61 /* Bit definition for SPI2S_IER register */
  62 #define I2S_IER_RXPIE           BIT(0)
  63 #define I2S_IER_TXPIE           BIT(1)
  64 #define I2S_IER_DPXPIE          BIT(2)
  65 #define I2S_IER_EOTIE           BIT(3)
  66 #define I2S_IER_TXTFIE          BIT(4)
  67 #define I2S_IER_UDRIE           BIT(5)
  68 #define I2S_IER_OVRIE           BIT(6)
  69 #define I2S_IER_CRCEIE          BIT(7)
  70 #define I2S_IER_TIFREIE         BIT(8)
  71 #define I2S_IER_MODFIE          BIT(9)
  72 #define I2S_IER_TSERFIE         BIT(10)
  73
  74 /* Bit definition for SPI2S_SR register */
  75 #define I2S_SR_RXP              BIT(0)
  76 #define I2S_SR_TXP              BIT(1)
  77 #define I2S_SR_DPXP             BIT(2)
  78 #define I2S_SR_EOT              BIT(3)
  79 #define I2S_SR_TXTF             BIT(4)
  80 #define I2S_SR_UDR              BIT(5)
  81 #define I2S_SR_OVR              BIT(6)
  82 #define I2S_SR_CRCERR           BIT(7)
  83 #define I2S_SR_TIFRE            BIT(8)
  84 #define I2S_SR_MODF             BIT(9)
  85 #define I2S_SR_TSERF            BIT(10)
  86 #define I2S_SR_SUSP             BIT(11)
  87 #define I2S_SR_TXC              BIT(12)
  88 #define I2S_SR_RXPLVL           GENMASK(14, 13)
  89 #define I2S_SR_RXWNE            BIT(15)
  90
  91 #define I2S_SR_MASK             GENMASK(15, 0)
  92
  93 /* Bit definition for SPI_IFCR register */
  94 #define I2S_IFCR_EOTC           BIT(3)
  95 #define I2S_IFCR_TXTFC          BIT(4)
  96 #define I2S_IFCR_UDRC           BIT(5)
  97 #define I2S_IFCR_OVRC           BIT(6)
  98 #define I2S_IFCR_CRCEC          BIT(7)
  99 #define I2S_IFCR_TIFREC         BIT(8)
 100 #define I2S_IFCR_MODFC          BIT(9)
 101 #define I2S_IFCR_TSERFC         BIT(10)
 102 #define I2S_IFCR_SUSPC          BIT(11)
 103
 104 #define I2S_IFCR_MASK           GENMASK(11, 3)
 105
 106 /* Bit definition for SPI_I2SCGFR register */
 107 #define I2S_CGFR_I2SMOD         BIT(0)
 108
 109 #define I2S_CGFR_I2SCFG_SHIFT   1
 110 #define I2S_CGFR_I2SCFG_MASK    GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
 111 #define I2S_CGFR_I2SCFG_SET(x)  ((x) << I2S_CGFR_I2SCFG_SHIFT)
 112
 113 #define I2S_CGFR_I2SSTD_SHIFT   4
 114 #define I2S_CGFR_I2SSTD_MASK    GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
 115 #define I2S_CGFR_I2SSTD_SET(x)  ((x) << I2S_CGFR_I2SSTD_SHIFT)
 116
 117 #define I2S_CGFR_PCMSYNC        BIT(7)
 118
 119 #define I2S_CGFR_DATLEN_SHIFT   8
 120 #define I2S_CGFR_DATLEN_MASK    GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
 121 #define I2S_CGFR_DATLEN_SET(x)  ((x) << I2S_CGFR_DATLEN_SHIFT)
 122
 123 #define I2S_CGFR_CHLEN_SHIFT    10
 124 #define I2S_CGFR_CHLEN          BIT(I2S_CGFR_CHLEN_SHIFT)
 125 #define I2S_CGFR_CKPOL          BIT(11)
 126 #define I2S_CGFR_FIXCH          BIT(12)
 127 #define I2S_CGFR_WSINV          BIT(13)
 128 #define I2S_CGFR_DATFMT         BIT(14)
 129
 130 #define I2S_CGFR_I2SDIV_SHIFT   16
 131 #define I2S_CGFR_I2SDIV_BIT_H   23
 132 #define I2S_CGFR_I2SDIV_MASK    GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
 133                                 I2S_CGFR_I2SDIV_SHIFT)
 134 #define I2S_CGFR_I2SDIV_SET(x)  ((x) << I2S_CGFR_I2SDIV_SHIFT)
 135 #define I2S_CGFR_I2SDIV_MAX     ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
 136                                 I2S_CGFR_I2SDIV_SHIFT)) - 1)
 137
 138 #define I2S_CGFR_ODD_SHIFT      24
 139 #define I2S_CGFR_ODD            BIT(I2S_CGFR_ODD_SHIFT)
 140 #define I2S_CGFR_MCKOE          BIT(25)
 141
 142 /* Registers below apply to I2S version 1.1 and more */
 143
 144 /* Bit definition for SPI_HWCFGR register */
 145 #define I2S_HWCFGR_I2S_SUPPORT_MASK     GENMASK(15, 12)
 146
 147 /* Bit definition for SPI_VERR register */
 148 #define I2S_VERR_MIN_MASK       GENMASK(3, 0)
 149 #define I2S_VERR_MAJ_MASK       GENMASK(7, 4)
 150
 151 /* Bit definition for SPI_IPIDR register */
 152 #define I2S_IPIDR_ID_MASK       GENMASK(31, 0)
 153
 154 /* Bit definition for SPI_SIDR register */
 155 #define I2S_SIDR_ID_MASK        GENMASK(31, 0)
 156
 157 #define I2S_IPIDR_NUMBER        0x00130022
 158
 159 enum i2s_master_mode {
 160         I2S_MS_NOT_SET,
 161         I2S_MS_MASTER,
 162         I2S_MS_SLAVE,
 163 };
 164
 165 enum i2s_mode {
 166         I2S_I2SMOD_TX_SLAVE,
 167         I2S_I2SMOD_RX_SLAVE,
 168         I2S_I2SMOD_TX_MASTER,
 169         I2S_I2SMOD_RX_MASTER,
 170         I2S_I2SMOD_FD_SLAVE,
 171         I2S_I2SMOD_FD_MASTER,
 172 };
 173
 174 enum i2s_fifo_th {
 175         I2S_FIFO_TH_NONE,
 176         I2S_FIFO_TH_ONE_QUARTER,
 177         I2S_FIFO_TH_HALF,
 178         I2S_FIFO_TH_THREE_QUARTER,
 179         I2S_FIFO_TH_FULL,
 180 };
 181
 182 enum i2s_std {
 183         I2S_STD_I2S,
 184         I2S_STD_LEFT_J,
 185         I2S_STD_RIGHT_J,
 186         I2S_STD_DSP,
 187 };
 188
 189 enum i2s_datlen {
 190         I2S_I2SMOD_DATLEN_16,
 191         I2S_I2SMOD_DATLEN_24,
 192         I2S_I2SMOD_DATLEN_32,
 193 };
 194
 195 #define STM32_I2S_FIFO_SIZE             16
 196
 197 #define STM32_I2S_IS_MASTER(x)          ((x)->ms_flg == I2S_MS_MASTER)
 198 #define STM32_I2S_IS_SLAVE(x)           ((x)->ms_flg == I2S_MS_SLAVE)
 199
 200 #define STM32_I2S_NAME_LEN              32
 201 #define STM32_I2S_RATE_11K              11025
 202
 203 /**
 204  * struct stm32_i2s_data - private data of I2S
 205  * @regmap_conf: I2S register map configuration pointer
 206  * @regmap: I2S register map pointer
 207  * @pdev: device data pointer
 208  * @dai_drv: DAI driver pointer
 209  * @dma_data_tx: dma configuration data for tx channel
 210  * @dma_data_rx: dma configuration data for tx channel
 211  * @substream: PCM substream data pointer
 212  * @i2sclk: kernel clock feeding the I2S clock generator
 213  * @i2smclk: master clock from I2S mclk provider
 214  * @pclk: peripheral clock driving bus interface
 215  * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
 216  * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
 217  * @base:  mmio register base virtual address
 218  * @phys_addr: I2S registers physical base address
 219  * @lock_fd: lock to manage race conditions in full duplex mode
 220  * @irq_lock: prevent race condition with IRQ
 221  * @mclk_rate: master clock frequency (Hz)
 222  * @fmt: DAI protocol
 223  * @divider: prescaler division ratio
 224  * @div: prescaler div field
 225  * @odd: prescaler odd field
 226  * @refcount: keep count of opened streams on I2S
 227  * @ms_flg: master mode flag.
 228  */
 229 struct stm32_i2s_data {
 230         const struct regmap_config *regmap_conf;
 231         struct regmap *regmap;
 232         struct platform_device *pdev;
 233         struct snd_soc_dai_driver *dai_drv;
 234         struct snd_dmaengine_dai_dma_data dma_data_tx;
 235         struct snd_dmaengine_dai_dma_data dma_data_rx;
 236         struct snd_pcm_substream *substream;
 237         struct clk *i2sclk;
 238         struct clk *i2smclk;
 239         struct clk *pclk;
 240         struct clk *x8kclk;
 241         struct clk *x11kclk;
 242         void __iomem *base;
 243         dma_addr_t phys_addr;
 244         spinlock_t lock_fd; /* Manage race conditions for full duplex */
 245         spinlock_t irq_lock; /* used to prevent race condition with IRQ */
 246         unsigned int mclk_rate;
 247         unsigned int fmt;
 248         unsigned int divider;
 249         unsigned int div;
 250         bool odd;
 251         int refcount;
 252         int ms_flg;
 253 };
 254
 255 struct stm32_i2smclk_data {
 256         struct clk_hw hw;
 257         unsigned long freq;
 258         struct stm32_i2s_data *i2s_data;
 259 };
 260
 261 #define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw)
 262
 263 static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
 264                                   unsigned long input_rate,
 265                                   unsigned long output_rate)
 266 {
 267         unsigned int ratio, div, divider = 1;
 268         bool odd;
 269
 270         ratio = DIV_ROUND_CLOSEST(input_rate, output_rate);
 271
 272         /* Check the parity of the divider */
 273         odd = ratio & 0x1;
 274
 275         /* Compute the div prescaler */
 276         div = ratio >> 1;
 277
 278         /* If div is 0 actual divider is 1 */
 279         if (div) {
 280                 divider = ((2 * div) + odd);
 281                 dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
 282                         div, odd, divider);
 283         }
 284
 285         /* Division by three is not allowed by I2S prescaler */
 286         if ((div == 1 && odd) || div > I2S_CGFR_I2SDIV_MAX) {
 287                 dev_err(&i2s->pdev->dev, "Wrong divider setting\n");
 288                 return -EINVAL;
 289         }
 290
 291         if (input_rate % divider)
 292                 dev_dbg(&i2s->pdev->dev,
 293                         "Rate not accurate. requested (%ld), actual (%ld)\n",
 294                         output_rate, input_rate / divider);
 295
 296         i2s->div = div;
 297         i2s->odd = odd;
 298         i2s->divider = divider;
 299
 300         return 0;
 301 }
 302
 303 static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
 304 {
 305         u32 cgfr, cgfr_mask;
 306
 307         cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);
 308         cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
 309
 310         return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 311                                   cgfr_mask, cgfr);
 312 }
 313
 314 static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
 315                                       unsigned int rate)
 316 {
 317         struct platform_device *pdev = i2s->pdev;
 318         struct clk *parent_clk;
 319         int ret;
 320
 321         if (!(rate % STM32_I2S_RATE_11K))
 322                 parent_clk = i2s->x11kclk;
 323         else
 324                 parent_clk = i2s->x8kclk;
 325
 326         ret = clk_set_parent(i2s->i2sclk, parent_clk);
 327         if (ret)
 328                 dev_err(&pdev->dev,
 329                         "Error %d setting i2sclk parent clock\n", ret);
 330
 331         return ret;
 332 }
 333
 334 static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate,
 335                                      unsigned long *prate)
 336 {
 337         struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
 338         struct stm32_i2s_data *i2s = mclk->i2s_data;
 339         int ret;
 340
 341         ret = stm32_i2s_calc_clk_div(i2s, *prate, rate);
 342         if (ret)
 343                 return ret;
 344
 345         mclk->freq = *prate / i2s->divider;
 346
 347         return mclk->freq;
 348 }
 349
 350 static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
 351                                                unsigned long parent_rate)
 352 {
 353         struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
 354
 355         return mclk->freq;
 356 }
 357
 358 static int stm32_i2smclk_set_rate(struct clk_hw *hw, unsigned long rate,
 359                                   unsigned long parent_rate)
 360 {
 361         struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
 362         struct stm32_i2s_data *i2s = mclk->i2s_data;
 363         int ret;
 364
 365         ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate);
 366         if (ret)
 367                 return ret;
 368
 369         ret = stm32_i2s_set_clk_div(i2s);
 370         if (ret)
 371                 return ret;
 372
 373         mclk->freq = rate;
 374
 375         return 0;
 376 }
 377
 378 static int stm32_i2smclk_enable(struct clk_hw *hw)
 379 {
 380         struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
 381         struct stm32_i2s_data *i2s = mclk->i2s_data;
 382
 383         dev_dbg(&i2s->pdev->dev, "Enable master clock\n");
 384
 385         return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 386                                     I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
 387 }
 388
 389 static void stm32_i2smclk_disable(struct clk_hw *hw)
 390 {
 391         struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
 392         struct stm32_i2s_data *i2s = mclk->i2s_data;
 393
 394         dev_dbg(&i2s->pdev->dev, "Disable master clock\n");
 395
 396         regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);
 397 }
 398
 399 static const struct clk_ops mclk_ops = {
 400         .enable = stm32_i2smclk_enable,
 401         .disable = stm32_i2smclk_disable,
 402         .recalc_rate = stm32_i2smclk_recalc_rate,
 403         .round_rate = stm32_i2smclk_round_rate,
 404         .set_rate = stm32_i2smclk_set_rate,
 405 };
 406
 407 static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s)
 408 {
 409         struct clk_hw *hw;
 410         struct stm32_i2smclk_data *mclk;
 411         struct device *dev = &i2s->pdev->dev;
 412         const char *pname = __clk_get_name(i2s->i2sclk);
 413         char *mclk_name, *p, *s = (char *)pname;
 414         int ret, i = 0;
 415
 416         mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
 417         if (!mclk)
 418                 return -ENOMEM;
 419
 420         mclk_name = devm_kcalloc(dev, sizeof(char),
 421                                  STM32_I2S_NAME_LEN, GFP_KERNEL);
 422         if (!mclk_name)
 423                 return -ENOMEM;
 424
 425         /*
 426          * Forge mclk clock name from parent clock name and suffix.
 427          * String after "_" char is stripped in parent name.
 428          */
 429         p = mclk_name;
 430         while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) {
 431                 *p++ = *s++;
 432                 i++;
 433         }
 434         strcat(p, "_mclk");
 435
 436         mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
 437         mclk->i2s_data = i2s;
 438         hw = &mclk->hw;
 439
 440         dev_dbg(dev, "Register master clock %s\n", mclk_name);
 441         ret = devm_clk_hw_register(&i2s->pdev->dev, hw);
 442         if (ret) {
 443                 dev_err(dev, "mclk register fails with error %d\n", ret);
 444                 return ret;
 445         }
 446         i2s->i2smclk = hw->clk;
 447
 448         /* register mclk provider */
 449         return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
 450 }
 451
 452 static irqreturn_t stm32_i2s_isr(int irq, void *devid)
 453 {
 454         struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
 455         struct platform_device *pdev = i2s->pdev;
 456         u32 sr, ier;
 457         unsigned long flags;
 458         int err = 0;
 459
 460         regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
 461         regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
 462
 463         flags = sr & ier;
 464         if (!flags) {
 465                 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
 466                         sr, ier);
 467                 return IRQ_NONE;
 468         }
 469
 470         regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 471                           I2S_IFCR_MASK, flags);
 472
 473         if (flags & I2S_SR_OVR) {
 474                 dev_dbg(&pdev->dev, "Overrun\n");
 475                 err = 1;
 476         }
 477
 478         if (flags & I2S_SR_UDR) {
 479                 dev_dbg(&pdev->dev, "Underrun\n");
 480                 err = 1;
 481         }
 482
 483         if (flags & I2S_SR_TIFRE)
 484                 dev_dbg(&pdev->dev, "Frame error\n");
 485
 486         spin_lock(&i2s->irq_lock);
 487         if (err && i2s->substream)
 488                 snd_pcm_stop_xrun(i2s->substream);
 489         spin_unlock(&i2s->irq_lock);
 490
 491         return IRQ_HANDLED;
 492 }
 493
 494 static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
 495 {
 496         switch (reg) {
 497         case STM32_I2S_CR1_REG:
 498         case STM32_I2S_CFG1_REG:
 499         case STM32_I2S_CFG2_REG:
 500         case STM32_I2S_IER_REG:
 501         case STM32_I2S_SR_REG:
 502         case STM32_I2S_RXDR_REG:
 503         case STM32_I2S_CGFR_REG:
 504         case STM32_I2S_HWCFGR_REG:
 505         case STM32_I2S_VERR_REG:
 506         case STM32_I2S_IPIDR_REG:
 507         case STM32_I2S_SIDR_REG:
 508                 return true;
 509         default:
 510                 return false;
 511         }
 512 }
 513
 514 static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
 515 {
 516         switch (reg) {
 517         case STM32_I2S_SR_REG:
 518         case STM32_I2S_RXDR_REG:
 519                 return true;
 520         default:
 521                 return false;
 522         }
 523 }
 524
 525 static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
 526 {
 527         switch (reg) {
 528         case STM32_I2S_CR1_REG:
 529         case STM32_I2S_CFG1_REG:
 530         case STM32_I2S_CFG2_REG:
 531         case STM32_I2S_IER_REG:
 532         case STM32_I2S_IFCR_REG:
 533         case STM32_I2S_TXDR_REG:
 534         case STM32_I2S_CGFR_REG:
 535                 return true;
 536         default:
 537                 return false;
 538         }
 539 }
 540
 541 static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 542 {
 543         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 544         u32 cgfr;
 545         u32 cgfr_mask =  I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
 546                          I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
 547
 548         dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
 549
 550         /*
 551          * winv = 0 : default behavior (high/low) for all standards
 552          * ckpol = 0 for all standards.
 553          */
 554         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 555         case SND_SOC_DAIFMT_I2S:
 556                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
 557                 break;
 558         case SND_SOC_DAIFMT_MSB:
 559                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
 560                 break;
 561         case SND_SOC_DAIFMT_LSB:
 562                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
 563                 break;
 564         case SND_SOC_DAIFMT_DSP_A:
 565                 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
 566                 break;
 567         /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
 568         default:
 569                 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
 570                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 571                 return -EINVAL;
 572         }
 573
 574         /* DAI clock strobing */
 575         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 576         case SND_SOC_DAIFMT_NB_NF:
 577                 break;
 578         case SND_SOC_DAIFMT_IB_NF:
 579                 cgfr |= I2S_CGFR_CKPOL;
 580                 break;
 581         case SND_SOC_DAIFMT_NB_IF:
 582                 cgfr |= I2S_CGFR_WSINV;
 583                 break;
 584         case SND_SOC_DAIFMT_IB_IF:
 585                 cgfr |= I2S_CGFR_CKPOL;
 586                 cgfr |= I2S_CGFR_WSINV;
 587                 break;
 588         default:
 589                 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
 590                         fmt & SND_SOC_DAIFMT_INV_MASK);
 591                 return -EINVAL;
 592         }
 593
 594         /* DAI clock master masks */
 595         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 596         case SND_SOC_DAIFMT_CBM_CFM:
 597                 i2s->ms_flg = I2S_MS_SLAVE;
 598                 break;
 599         case SND_SOC_DAIFMT_CBS_CFS:
 600                 i2s->ms_flg = I2S_MS_MASTER;
 601                 break;
 602         default:
 603                 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
 604                         fmt & SND_SOC_DAIFMT_MASTER_MASK);
 605                 return -EINVAL;
 606         }
 607
 608         i2s->fmt = fmt;
 609         return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 610                                   cgfr_mask, cgfr);
 611 }
 612
 613 static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
 614                                 int clk_id, unsigned int freq, int dir)
 615 {
 616         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 617         int ret = 0;
 618
 619         dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n",
 620                 freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave",
 621                 dir ? "output" : "input");
 622
 623         /* MCLK generation is available only in master mode */
 624         if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) {
 625                 if (!i2s->i2smclk) {
 626                         dev_dbg(cpu_dai->dev, "No MCLK registered\n");
 627                         return 0;
 628                 }
 629
 630                 /* Assume shutdown if requested frequency is 0Hz */
 631                 if (!freq) {
 632                         /* Release mclk rate only if rate was actually set */
 633                         if (i2s->mclk_rate) {
 634                                 clk_rate_exclusive_put(i2s->i2smclk);
 635                                 i2s->mclk_rate = 0;
 636                         }
 637                         return regmap_update_bits(i2s->regmap,
 638                                                   STM32_I2S_CGFR_REG,
 639                                                   I2S_CGFR_MCKOE, 0);
 640                 }
 641                 /* If master clock is used, set parent clock now */
 642                 ret = stm32_i2s_set_parent_clock(i2s, freq);
 643                 if (ret)
 644                         return ret;
 645                 ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
 646                 if (ret) {
 647                         dev_err(cpu_dai->dev, "Could not set mclk rate\n");
 648                         return ret;
 649                 }
 650                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 651                                          I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
 652                 if (!ret)
 653                         i2s->mclk_rate = freq;
 654         }
 655
 656         return ret;
 657 }
 658
 659 static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
 660                                      struct snd_pcm_hw_params *params)
 661 {
 662         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 663         unsigned long i2s_clock_rate;
 664         unsigned int nb_bits, frame_len;
 665         unsigned int rate = params_rate(params);
 666         u32 cgfr;
 667         int ret;
 668
 669         if (!(rate % 11025))
 670                 clk_set_parent(i2s->i2sclk, i2s->x11kclk);
 671         else
 672                 clk_set_parent(i2s->i2sclk, i2s->x8kclk);
 673         i2s_clock_rate = clk_get_rate(i2s->i2sclk);
 674
 675         /*
 676          * mckl = mclk_ratio x ws
 677          *   i2s mode : mclk_ratio = 256
 678          *   dsp mode : mclk_ratio = 128
 679          *
 680          * mclk on
 681          *   i2s mode : div = i2s_clk / (mclk_ratio * ws)
 682          *   dsp mode : div = i2s_clk / (mclk_ratio * ws)
 683          * mclk off
 684          *   i2s mode : div = i2s_clk / (nb_bits x ws)
 685          *   dsp mode : div = i2s_clk / (nb_bits x ws)
 686          */
 687         if (i2s->mclk_rate) {
 688                 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
 689                                              i2s->mclk_rate);
 690                 if (ret)
 691                         return ret;
 692         } else {
 693                 frame_len = 32;
 694                 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
 695                     SND_SOC_DAIFMT_DSP_A)
 696                         frame_len = 16;
 697
 698                 /* master clock not enabled */
 699                 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
 700                 if (ret < 0)
 701                         return ret;
 702
 703                 nb_bits = frame_len * (FIELD_GET(I2S_CGFR_CHLEN, cgfr) + 1);
 704                 ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
 705                                              (nb_bits * rate));
 706                 if (ret)
 707                         return ret;
 708         }
 709
 710         ret = stm32_i2s_set_clk_div(i2s);
 711         if (ret < 0)
 712                 return ret;
 713
 714         /* Set bitclock and frameclock to their inactive state */
 715         return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
 716                                   I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
 717 }
 718
 719 static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
 720                                struct snd_pcm_hw_params *params,
 721                                struct snd_pcm_substream *substream)
 722 {
 723         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 724         int format = params_width(params);
 725         u32 cfgr, cfgr_mask, cfg1;
 726         unsigned int fthlv;
 727         int ret;
 728
 729         switch (format) {
 730         case 16:
 731                 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
 732                 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
 733                 break;
 734         case 32:
 735                 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
 736                                            I2S_CGFR_CHLEN;
 737                 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
 738                 break;
 739         default:
 740                 dev_err(cpu_dai->dev, "Unexpected format %d", format);
 741                 return -EINVAL;
 742         }
 743
 744         if (STM32_I2S_IS_SLAVE(i2s)) {
 745                 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
 746
 747                 /* As data length is either 16 or 32 bits, fixch always set */
 748                 cfgr |= I2S_CGFR_FIXCH;
 749                 cfgr_mask |= I2S_CGFR_FIXCH;
 750         } else {
 751                 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
 752         }
 753         cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
 754
 755         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 756                                  cfgr_mask, cfgr);
 757         if (ret < 0)
 758                 return ret;
 759
 760         fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
 761         cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
 762
 763         return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 764                                   I2S_CFG1_FTHVL_MASK, cfg1);
 765 }
 766
 767 static int stm32_i2s_startup(struct snd_pcm_substream *substream,
 768                              struct snd_soc_dai *cpu_dai)
 769 {
 770         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 771         unsigned long flags;
 772         int ret;
 773
 774         spin_lock_irqsave(&i2s->irq_lock, flags);
 775         i2s->substream = substream;
 776         spin_unlock_irqrestore(&i2s->irq_lock, flags);
 777
 778         if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
 779                 snd_pcm_hw_constraint_single(substream->runtime,
 780                                              SNDRV_PCM_HW_PARAM_CHANNELS, 2);
 781
 782         ret = clk_prepare_enable(i2s->i2sclk);
 783         if (ret < 0) {
 784                 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
 785                 return ret;
 786         }
 787
 788         return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 789                                  I2S_IFCR_MASK, I2S_IFCR_MASK);
 790 }
 791
 792 static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
 793                                struct snd_pcm_hw_params *params,
 794                                struct snd_soc_dai *cpu_dai)
 795 {
 796         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 797         int ret;
 798
 799         ret = stm32_i2s_configure(cpu_dai, params, substream);
 800         if (ret < 0) {
 801                 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
 802                 return ret;
 803         }
 804
 805         if (STM32_I2S_IS_MASTER(i2s))
 806                 ret = stm32_i2s_configure_clock(cpu_dai, params);
 807
 808         return ret;
 809 }
 810
 811 static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 812                              struct snd_soc_dai *cpu_dai)
 813 {
 814         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 815         bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 816         u32 cfg1_mask, ier;
 817         int ret;
 818
 819         switch (cmd) {
 820         case SNDRV_PCM_TRIGGER_START:
 821         case SNDRV_PCM_TRIGGER_RESUME:
 822         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 823                 /* Enable i2s */
 824                 dev_dbg(cpu_dai->dev, "start I2S %s\n",
 825                         playback_flg ? "playback" : "capture");
 826
 827                 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
 828                 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 829                                    cfg1_mask, cfg1_mask);
 830
 831                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 832                                          I2S_CR1_SPE, I2S_CR1_SPE);
 833                 if (ret < 0) {
 834                         dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
 835                         return ret;
 836                 }
 837
 838                 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
 839                                         I2S_CR1_CSTART, I2S_CR1_CSTART);
 840                 if (ret < 0) {
 841                         dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
 842                         return ret;
 843                 }
 844
 845                 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 846                                   I2S_IFCR_MASK, I2S_IFCR_MASK);
 847
 848                 spin_lock(&i2s->lock_fd);
 849                 i2s->refcount++;
 850                 if (playback_flg) {
 851                         ier = I2S_IER_UDRIE;
 852                 } else {
 853                         ier = I2S_IER_OVRIE;
 854
 855                         if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
 856                                 /* dummy write to gate bus clocks */
 857                                 regmap_write(i2s->regmap,
 858                                              STM32_I2S_TXDR_REG, 0);
 859                 }
 860                 spin_unlock(&i2s->lock_fd);
 861
 862                 if (STM32_I2S_IS_SLAVE(i2s))
 863                         ier |= I2S_IER_TIFREIE;
 864
 865                 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
 866                 break;
 867         case SNDRV_PCM_TRIGGER_STOP:
 868         case SNDRV_PCM_TRIGGER_SUSPEND:
 869         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 870                 dev_dbg(cpu_dai->dev, "stop I2S %s\n",
 871                         playback_flg ? "playback" : "capture");
 872
 873                 if (playback_flg)
 874                         regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
 875                                            I2S_IER_UDRIE,
 876                                            (unsigned int)~I2S_IER_UDRIE);
 877                 else
 878                         regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
 879                                            I2S_IER_OVRIE,
 880                                            (unsigned int)~I2S_IER_OVRIE);
 881
 882                 spin_lock(&i2s->lock_fd);
 883                 i2s->refcount--;
 884                 if (i2s->refcount) {
 885                         spin_unlock(&i2s->lock_fd);
 886                         break;
 887                 }
 888
 889                 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 890                                          I2S_CR1_SPE, 0);
 891                 if (ret < 0) {
 892                         dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
 893                         spin_unlock(&i2s->lock_fd);
 894                         return ret;
 895                 }
 896                 spin_unlock(&i2s->lock_fd);
 897
 898                 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
 899                 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 900                                    cfg1_mask, 0);
 901                 break;
 902         default:
 903                 return -EINVAL;
 904         }
 905
 906         return 0;
 907 }
 908
 909 static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
 910                                struct snd_soc_dai *cpu_dai)
 911 {
 912         struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 913         unsigned long flags;
 914
 915         clk_disable_unprepare(i2s->i2sclk);
 916
 917         spin_lock_irqsave(&i2s->irq_lock, flags);
 918         i2s->substream = NULL;
 919         spin_unlock_irqrestore(&i2s->irq_lock, flags);
 920 }
 921
 922 static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
 923 {
 924         struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
 925         struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
 926         struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
 927
 928         /* Buswidth will be set by framework */
 929         dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 930         dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
 931         dma_data_tx->maxburst = 1;
 932         dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 933         dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
 934         dma_data_rx->maxburst = 1;
 935
 936         snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
 937
 938         return 0;
 939 }
 940
 941 static const struct regmap_config stm32_h7_i2s_regmap_conf = {
 942         .reg_bits = 32,
 943         .reg_stride = 4,
 944         .val_bits = 32,
 945         .max_register = STM32_I2S_SIDR_REG,
 946         .readable_reg = stm32_i2s_readable_reg,
 947         .volatile_reg = stm32_i2s_volatile_reg,
 948         .writeable_reg = stm32_i2s_writeable_reg,
 949         .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
 950         .fast_io = true,
 951         .cache_type = REGCACHE_FLAT,
 952 };
 953
 954 static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
 955         .set_sysclk     = stm32_i2s_set_sysclk,
 956         .set_fmt        = stm32_i2s_set_dai_fmt,
 957         .startup        = stm32_i2s_startup,
 958         .hw_params      = stm32_i2s_hw_params,
 959         .trigger        = stm32_i2s_trigger,
 960         .shutdown       = stm32_i2s_shutdown,
 961 };
 962
 963 static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
 964         .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
 965         .buffer_bytes_max = 8 * PAGE_SIZE,
 966         .period_bytes_min = 1024,
 967         .period_bytes_max = 4 * PAGE_SIZE,
 968         .periods_min = 2,
 969         .periods_max = 8,
 970 };
 971
 972 static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
 973         .pcm_hardware   = &stm32_i2s_pcm_hw,
 974         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
 975         .prealloc_buffer_size = PAGE_SIZE * 8,
 976 };
 977
 978 static const struct snd_soc_component_driver stm32_i2s_component = {
 979         .name = "stm32-i2s",
 980 };
 981
 982 static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
 983                                char *stream_name)
 984 {
 985         stream->stream_name = stream_name;
 986         stream->channels_min = 1;
 987         stream->channels_max = 2;
 988         stream->rates = SNDRV_PCM_RATE_8000_192000;
 989         stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
 990                                    SNDRV_PCM_FMTBIT_S32_LE;
 991 }
 992
 993 static int stm32_i2s_dais_init(struct platform_device *pdev,
 994                                struct stm32_i2s_data *i2s)
 995 {
 996         struct snd_soc_dai_driver *dai_ptr;
 997
 998         dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
 999                                GFP_KERNEL);
1000         if (!dai_ptr)
1001                 return -ENOMEM;
1002
1003         dai_ptr->probe = stm32_i2s_dai_probe;
1004         dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
1005         dai_ptr->id = 1;
1006         stm32_i2s_dai_init(&dai_ptr->playback, "playback");
1007         stm32_i2s_dai_init(&dai_ptr->capture, "capture");
1008         i2s->dai_drv = dai_ptr;
1009
1010         return 0;
1011 }
1012
1013 static const struct of_device_id stm32_i2s_ids[] = {
1014         {
1015                 .compatible = "st,stm32h7-i2s",
1016                 .data = &stm32_h7_i2s_regmap_conf
1017         },
1018         {},
1019 };
1020
1021 static int stm32_i2s_parse_dt(struct platform_device *pdev,
1022                               struct stm32_i2s_data *i2s)
1023 {
1024         struct device_node *np = pdev->dev.of_node;
1025         const struct of_device_id *of_id;
1026         struct reset_control *rst;
1027         struct resource *res;
1028         int irq, ret;
1029
1030         if (!np)
1031                 return -ENODEV;
1032
1033         of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
1034         if (of_id)
1035                 i2s->regmap_conf = (const struct regmap_config *)of_id->data;
1036         else
1037                 return -EINVAL;
1038
1039         i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1040         if (IS_ERR(i2s->base))
1041                 return PTR_ERR(i2s->base);
1042
1043         i2s->phys_addr = res->start;
1044
1045         /* Get clocks */
1046         i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
1047         if (IS_ERR(i2s->pclk)) {
1048                 if (PTR_ERR(i2s->pclk) != -EPROBE_DEFER)
1049                         dev_err(&pdev->dev, "Could not get pclk: %ld\n",
1050                                 PTR_ERR(i2s->pclk));
1051                 return PTR_ERR(i2s->pclk);
1052         }
1053
1054         i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
1055         if (IS_ERR(i2s->i2sclk)) {
1056                 if (PTR_ERR(i2s->i2sclk) != -EPROBE_DEFER)
1057                         dev_err(&pdev->dev, "Could not get i2sclk: %ld\n",
1058                                 PTR_ERR(i2s->i2sclk));
1059                 return PTR_ERR(i2s->i2sclk);
1060         }
1061
1062         i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
1063         if (IS_ERR(i2s->x8kclk)) {
1064                 if (PTR_ERR(i2s->x8kclk) != -EPROBE_DEFER)
1065                         dev_err(&pdev->dev, "Could not get x8k parent clock: %ld\n",
1066                                 PTR_ERR(i2s->x8kclk));
1067                 return PTR_ERR(i2s->x8kclk);
1068         }
1069
1070         i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
1071         if (IS_ERR(i2s->x11kclk)) {
1072                 if (PTR_ERR(i2s->x11kclk) != -EPROBE_DEFER)
1073                         dev_err(&pdev->dev, "Could not get x11k parent clock: %ld\n",
1074                                 PTR_ERR(i2s->x11kclk));
1075                 return PTR_ERR(i2s->x11kclk);
1076         }
1077
1078         /* Register mclk provider if requested */
1079         if (of_find_property(np, "#clock-cells", NULL)) {
1080                 ret = stm32_i2s_add_mclk_provider(i2s);
1081                 if (ret < 0)
1082                         return ret;
1083         }
1084
1085         /* Get irqs */
1086         irq = platform_get_irq(pdev, 0);
1087         if (irq < 0)
1088                 return irq;
1089
1090         ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,
1091                                dev_name(&pdev->dev), i2s);
1092         if (ret) {
1093                 dev_err(&pdev->dev, "irq request returned %d\n", ret);
1094                 return ret;
1095         }
1096
1097         /* Reset */
1098         rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1099         if (IS_ERR(rst)) {
1100                 if (PTR_ERR(rst) != -EPROBE_DEFER)
1101                         dev_err(&pdev->dev, "Reset controller error %ld\n",
1102                                 PTR_ERR(rst));
1103                 return PTR_ERR(rst);
1104         }
1105         reset_control_assert(rst);
1106         udelay(2);
1107         reset_control_deassert(rst);
1108
1109         return 0;
1110 }
1111
1112 static int stm32_i2s_remove(struct platform_device *pdev)
1113 {
1114         snd_dmaengine_pcm_unregister(&pdev->dev);
1115         snd_soc_unregister_component(&pdev->dev);
1116
1117         return 0;
1118 }
1119
1120 static int stm32_i2s_probe(struct platform_device *pdev)
1121 {
1122         struct stm32_i2s_data *i2s;
1123         u32 val;
1124         int ret;
1125
1126         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1127         if (!i2s)
1128                 return -ENOMEM;
1129
1130         i2s->pdev = pdev;
1131         i2s->ms_flg = I2S_MS_NOT_SET;
1132         spin_lock_init(&i2s->lock_fd);
1133         spin_lock_init(&i2s->irq_lock);
1134         platform_set_drvdata(pdev, i2s);
1135
1136         ret = stm32_i2s_parse_dt(pdev, i2s);
1137         if (ret)
1138                 return ret;
1139
1140         ret = stm32_i2s_dais_init(pdev, i2s);
1141         if (ret)
1142                 return ret;
1143
1144         i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
1145                                                 i2s->base, i2s->regmap_conf);
1146         if (IS_ERR(i2s->regmap)) {
1147                 if (PTR_ERR(i2s->regmap) != -EPROBE_DEFER)
1148                         dev_err(&pdev->dev, "Regmap init error %ld\n",
1149                                 PTR_ERR(i2s->regmap));
1150                 return PTR_ERR(i2s->regmap);
1151         }
1152
1153         ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);
1154         if (ret) {
1155                 if (ret != -EPROBE_DEFER)
1156                         dev_err(&pdev->dev, "PCM DMA register error %d\n", ret);
1157                 return ret;
1158         }
1159
1160         ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
1161                                          i2s->dai_drv, 1);
1162         if (ret) {
1163                 snd_dmaengine_pcm_unregister(&pdev->dev);
1164                 return ret;
1165         }
1166
1167         /* Set SPI/I2S in i2s mode */
1168         ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
1169                                  I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
1170         if (ret)
1171                 goto error;
1172
1173         ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
1174         if (ret)
1175                 goto error;
1176
1177         if (val == I2S_IPIDR_NUMBER) {
1178                 ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
1179                 if (ret)
1180                         goto error;
1181
1182                 if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
1183                         dev_err(&pdev->dev,
1184                                 "Device does not support i2s mode\n");
1185                         ret = -EPERM;
1186                         goto error;
1187                 }
1188
1189                 ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
1190                 if (ret)
1191                         goto error;
1192
1193                 dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
1194                         FIELD_GET(I2S_VERR_MAJ_MASK, val),
1195                         FIELD_GET(I2S_VERR_MIN_MASK, val));
1196         }
1197
1198         return ret;
1199
1200 error:
1201         stm32_i2s_remove(pdev);
1202
1203         return ret;
1204 }
1205
1206 MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
1207
1208 #ifdef CONFIG_PM_SLEEP
1209 static int stm32_i2s_suspend(struct device *dev)
1210 {
1211         struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1212
1213         regcache_cache_only(i2s->regmap, true);
1214         regcache_mark_dirty(i2s->regmap);
1215
1216         return 0;
1217 }
1218
1219 static int stm32_i2s_resume(struct device *dev)
1220 {
1221         struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1222
1223         regcache_cache_only(i2s->regmap, false);
1224         return regcache_sync(i2s->regmap);
1225 }
1226 #endif /* CONFIG_PM_SLEEP */
1227
1228 static const struct dev_pm_ops stm32_i2s_pm_ops = {
1229         SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
1230 };
1231
1232 static struct platform_driver stm32_i2s_driver = {
1233         .driver = {
1234                 .name = "st,stm32-i2s",
1235                 .of_match_table = stm32_i2s_ids,
1236                 .pm = &stm32_i2s_pm_ops,
1237         },
1238         .probe = stm32_i2s_probe,
1239         .remove = stm32_i2s_remove,
1240 };
1241
1242 module_platform_driver(stm32_i2s_driver);
1243
1244 MODULE_DESCRIPTION("STM32 Soc i2s Interface");
1245 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1246 MODULE_ALIAS("platform:stm32-i2s");
1247 MODULE_LICENSE("GPL v2");