1 // SPDX-License-Identifier: GPL-2.0-only
3 * STM32 ALSA SoC Digital Audio Interface (I2S) driver.
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/module.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_platform.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
17 #include <linux/spinlock.h>
19 #include <sound/dmaengine_pcm.h>
20 #include <sound/pcm_params.h>
22 #define STM32_I2S_CR1_REG 0x0
23 #define STM32_I2S_CFG1_REG 0x08
24 #define STM32_I2S_CFG2_REG 0x0C
25 #define STM32_I2S_IER_REG 0x10
26 #define STM32_I2S_SR_REG 0x14
27 #define STM32_I2S_IFCR_REG 0x18
28 #define STM32_I2S_TXDR_REG 0X20
29 #define STM32_I2S_RXDR_REG 0x30
30 #define STM32_I2S_CGFR_REG 0X50
31 #define STM32_I2S_HWCFGR_REG 0x3F0
32 #define STM32_I2S_VERR_REG 0x3F4
33 #define STM32_I2S_IPIDR_REG 0x3F8
34 #define STM32_I2S_SIDR_REG 0x3FC
36 /* Bit definition for SPI2S_CR1 register */
37 #define I2S_CR1_SPE BIT(0)
38 #define I2S_CR1_CSTART BIT(9)
39 #define I2S_CR1_CSUSP BIT(10)
40 #define I2S_CR1_HDDIR BIT(11)
41 #define I2S_CR1_SSI BIT(12)
42 #define I2S_CR1_CRC33_17 BIT(13)
43 #define I2S_CR1_RCRCI BIT(14)
44 #define I2S_CR1_TCRCI BIT(15)
46 /* Bit definition for SPI_CFG2 register */
47 #define I2S_CFG2_IOSWP_SHIFT 15
48 #define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
49 #define I2S_CFG2_LSBFRST BIT(23)
50 #define I2S_CFG2_AFCNTR BIT(31)
52 /* Bit definition for SPI_CFG1 register */
53 #define I2S_CFG1_FTHVL_SHIFT 5
54 #define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
55 #define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT)
57 #define I2S_CFG1_TXDMAEN BIT(15)
58 #define I2S_CFG1_RXDMAEN BIT(14)
60 /* Bit definition for SPI2S_IER register */
61 #define I2S_IER_RXPIE BIT(0)
62 #define I2S_IER_TXPIE BIT(1)
63 #define I2S_IER_DPXPIE BIT(2)
64 #define I2S_IER_EOTIE BIT(3)
65 #define I2S_IER_TXTFIE BIT(4)
66 #define I2S_IER_UDRIE BIT(5)
67 #define I2S_IER_OVRIE BIT(6)
68 #define I2S_IER_CRCEIE BIT(7)
69 #define I2S_IER_TIFREIE BIT(8)
70 #define I2S_IER_MODFIE BIT(9)
71 #define I2S_IER_TSERFIE BIT(10)
73 /* Bit definition for SPI2S_SR register */
74 #define I2S_SR_RXP BIT(0)
75 #define I2S_SR_TXP BIT(1)
76 #define I2S_SR_DPXP BIT(2)
77 #define I2S_SR_EOT BIT(3)
78 #define I2S_SR_TXTF BIT(4)
79 #define I2S_SR_UDR BIT(5)
80 #define I2S_SR_OVR BIT(6)
81 #define I2S_SR_CRCERR BIT(7)
82 #define I2S_SR_TIFRE BIT(8)
83 #define I2S_SR_MODF BIT(9)
84 #define I2S_SR_TSERF BIT(10)
85 #define I2S_SR_SUSP BIT(11)
86 #define I2S_SR_TXC BIT(12)
87 #define I2S_SR_RXPLVL GENMASK(14, 13)
88 #define I2S_SR_RXWNE BIT(15)
90 #define I2S_SR_MASK GENMASK(15, 0)
92 /* Bit definition for SPI_IFCR register */
93 #define I2S_IFCR_EOTC BIT(3)
94 #define I2S_IFCR_TXTFC BIT(4)
95 #define I2S_IFCR_UDRC BIT(5)
96 #define I2S_IFCR_OVRC BIT(6)
97 #define I2S_IFCR_CRCEC BIT(7)
98 #define I2S_IFCR_TIFREC BIT(8)
99 #define I2S_IFCR_MODFC BIT(9)
100 #define I2S_IFCR_TSERFC BIT(10)
101 #define I2S_IFCR_SUSPC BIT(11)
103 #define I2S_IFCR_MASK GENMASK(11, 3)
105 /* Bit definition for SPI_I2SCGFR register */
106 #define I2S_CGFR_I2SMOD BIT(0)
108 #define I2S_CGFR_I2SCFG_SHIFT 1
109 #define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
110 #define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT)
112 #define I2S_CGFR_I2SSTD_SHIFT 4
113 #define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
114 #define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT)
116 #define I2S_CGFR_PCMSYNC BIT(7)
118 #define I2S_CGFR_DATLEN_SHIFT 8
119 #define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
120 #define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT)
122 #define I2S_CGFR_CHLEN_SHIFT 10
123 #define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT)
124 #define I2S_CGFR_CKPOL BIT(11)
125 #define I2S_CGFR_FIXCH BIT(12)
126 #define I2S_CGFR_WSINV BIT(13)
127 #define I2S_CGFR_DATFMT BIT(14)
129 #define I2S_CGFR_I2SDIV_SHIFT 16
130 #define I2S_CGFR_I2SDIV_BIT_H 23
131 #define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
132 I2S_CGFR_I2SDIV_SHIFT)
133 #define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT)
134 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
135 I2S_CGFR_I2SDIV_SHIFT)) - 1)
137 #define I2S_CGFR_ODD_SHIFT 24
138 #define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT)
139 #define I2S_CGFR_MCKOE BIT(25)
141 /* Registers below apply to I2S version 1.1 and more */
143 /* Bit definition for SPI_HWCFGR register */
144 #define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
146 /* Bit definition for SPI_VERR register */
147 #define I2S_VERR_MIN_MASK GENMASK(3, 0)
148 #define I2S_VERR_MAJ_MASK GENMASK(7, 4)
150 /* Bit definition for SPI_IPIDR register */
151 #define I2S_IPIDR_ID_MASK GENMASK(31, 0)
153 /* Bit definition for SPI_SIDR register */
154 #define I2S_SIDR_ID_MASK GENMASK(31, 0)
156 #define I2S_IPIDR_NUMBER 0x00130022
158 enum i2s_master_mode {
167 I2S_I2SMOD_TX_MASTER,
168 I2S_I2SMOD_RX_MASTER,
170 I2S_I2SMOD_FD_MASTER,
175 I2S_FIFO_TH_ONE_QUARTER,
177 I2S_FIFO_TH_THREE_QUARTER,
189 I2S_I2SMOD_DATLEN_16,
190 I2S_I2SMOD_DATLEN_24,
191 I2S_I2SMOD_DATLEN_32,
194 #define STM32_I2S_FIFO_SIZE 16
196 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
197 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
200 * struct stm32_i2s_data - private data of I2S
201 * @regmap_conf: I2S register map configuration pointer
202 * @regmap: I2S register map pointer
203 * @pdev: device data pointer
204 * @dai_drv: DAI driver pointer
205 * @dma_data_tx: dma configuration data for tx channel
206 * @dma_data_rx: dma configuration data for tx channel
207 * @substream: PCM substream data pointer
208 * @i2sclk: kernel clock feeding the I2S clock generator
209 * @pclk: peripheral clock driving bus interface
210 * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
211 * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
212 * @base: mmio register base virtual address
213 * @phys_addr: I2S registers physical base address
214 * @lock_fd: lock to manage race conditions in full duplex mode
215 * @irq_lock: prevent race condition with IRQ
216 * @mclk_rate: master clock frequency (Hz)
218 * @refcount: keep count of opened streams on I2S
219 * @ms_flg: master mode flag.
221 struct stm32_i2s_data {
222 const struct regmap_config *regmap_conf;
223 struct regmap *regmap;
224 struct platform_device *pdev;
225 struct snd_soc_dai_driver *dai_drv;
226 struct snd_dmaengine_dai_dma_data dma_data_tx;
227 struct snd_dmaengine_dai_dma_data dma_data_rx;
228 struct snd_pcm_substream *substream;
234 dma_addr_t phys_addr;
235 spinlock_t lock_fd; /* Manage race conditions for full duplex */
236 spinlock_t irq_lock; /* used to prevent race condition with IRQ */
237 unsigned int mclk_rate;
243 static irqreturn_t stm32_i2s_isr(int irq, void *devid)
245 struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
246 struct platform_device *pdev = i2s->pdev;
251 regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
252 regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
256 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
261 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
262 I2S_IFCR_MASK, flags);
264 if (flags & I2S_SR_OVR) {
265 dev_dbg(&pdev->dev, "Overrun\n");
269 if (flags & I2S_SR_UDR) {
270 dev_dbg(&pdev->dev, "Underrun\n");
274 if (flags & I2S_SR_TIFRE)
275 dev_dbg(&pdev->dev, "Frame error\n");
277 spin_lock(&i2s->irq_lock);
278 if (err && i2s->substream)
279 snd_pcm_stop_xrun(i2s->substream);
280 spin_unlock(&i2s->irq_lock);
285 static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
288 case STM32_I2S_CR1_REG:
289 case STM32_I2S_CFG1_REG:
290 case STM32_I2S_CFG2_REG:
291 case STM32_I2S_IER_REG:
292 case STM32_I2S_SR_REG:
293 case STM32_I2S_RXDR_REG:
294 case STM32_I2S_CGFR_REG:
295 case STM32_I2S_HWCFGR_REG:
296 case STM32_I2S_VERR_REG:
297 case STM32_I2S_IPIDR_REG:
298 case STM32_I2S_SIDR_REG:
305 static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
308 case STM32_I2S_SR_REG:
309 case STM32_I2S_RXDR_REG:
316 static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
319 case STM32_I2S_CR1_REG:
320 case STM32_I2S_CFG1_REG:
321 case STM32_I2S_CFG2_REG:
322 case STM32_I2S_IER_REG:
323 case STM32_I2S_IFCR_REG:
324 case STM32_I2S_TXDR_REG:
325 case STM32_I2S_CGFR_REG:
332 static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
334 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
336 u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
337 I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
339 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
342 * winv = 0 : default behavior (high/low) for all standards
343 * ckpol = 0 for all standards.
345 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
346 case SND_SOC_DAIFMT_I2S:
347 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
349 case SND_SOC_DAIFMT_MSB:
350 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
352 case SND_SOC_DAIFMT_LSB:
353 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
355 case SND_SOC_DAIFMT_DSP_A:
356 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
358 /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
360 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
361 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
365 /* DAI clock strobing */
366 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
367 case SND_SOC_DAIFMT_NB_NF:
369 case SND_SOC_DAIFMT_IB_NF:
370 cgfr |= I2S_CGFR_CKPOL;
372 case SND_SOC_DAIFMT_NB_IF:
373 cgfr |= I2S_CGFR_WSINV;
375 case SND_SOC_DAIFMT_IB_IF:
376 cgfr |= I2S_CGFR_CKPOL;
377 cgfr |= I2S_CGFR_WSINV;
380 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
381 fmt & SND_SOC_DAIFMT_INV_MASK);
385 /* DAI clock master masks */
386 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
387 case SND_SOC_DAIFMT_CBM_CFM:
388 i2s->ms_flg = I2S_MS_SLAVE;
390 case SND_SOC_DAIFMT_CBS_CFS:
391 i2s->ms_flg = I2S_MS_MASTER;
394 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
395 fmt & SND_SOC_DAIFMT_MASTER_MASK);
400 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
404 static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
405 int clk_id, unsigned int freq, int dir)
407 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
409 dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz\n", freq);
411 if ((dir == SND_SOC_CLOCK_OUT) && STM32_I2S_IS_MASTER(i2s)) {
412 i2s->mclk_rate = freq;
414 /* Enable master clock if master mode and mclk-fs are set */
415 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
416 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
422 static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
423 struct snd_pcm_hw_params *params)
425 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
426 unsigned long i2s_clock_rate;
427 unsigned int tmp, div, real_div, nb_bits, frame_len;
428 unsigned int rate = params_rate(params);
434 clk_set_parent(i2s->i2sclk, i2s->x11kclk);
436 clk_set_parent(i2s->i2sclk, i2s->x8kclk);
437 i2s_clock_rate = clk_get_rate(i2s->i2sclk);
440 * mckl = mclk_ratio x ws
441 * i2s mode : mclk_ratio = 256
442 * dsp mode : mclk_ratio = 128
445 * i2s mode : div = i2s_clk / (mclk_ratio * ws)
446 * dsp mode : div = i2s_clk / (mclk_ratio * ws)
448 * i2s mode : div = i2s_clk / (nb_bits x ws)
449 * dsp mode : div = i2s_clk / (nb_bits x ws)
451 if (i2s->mclk_rate) {
452 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, i2s->mclk_rate);
455 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
456 SND_SOC_DAIFMT_DSP_A)
459 /* master clock not enabled */
460 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
464 nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1);
465 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, (nb_bits * rate));
468 /* Check the parity of the divider */
471 /* Compute the div prescaler */
474 cgfr = I2S_CGFR_I2SDIV_SET(div) | (odd << I2S_CGFR_ODD_SHIFT);
475 cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
477 real_div = ((2 * div) + odd);
478 dev_dbg(cpu_dai->dev, "I2S clk: %ld, SCLK: %d\n",
479 i2s_clock_rate, rate);
480 dev_dbg(cpu_dai->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
483 if (((div == 1) && odd) || (div > I2S_CGFR_I2SDIV_MAX)) {
484 dev_err(cpu_dai->dev, "Wrong divider setting\n");
489 dev_warn(cpu_dai->dev, "real divider forced to 1\n");
491 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
496 /* Set bitclock and frameclock to their inactive state */
497 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
498 I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
501 static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
502 struct snd_pcm_hw_params *params,
503 struct snd_pcm_substream *substream)
505 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
506 int format = params_width(params);
507 u32 cfgr, cfgr_mask, cfg1;
513 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
514 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
517 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
519 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
522 dev_err(cpu_dai->dev, "Unexpected format %d", format);
526 if (STM32_I2S_IS_SLAVE(i2s)) {
527 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
529 /* As data length is either 16 or 32 bits, fixch always set */
530 cfgr |= I2S_CGFR_FIXCH;
531 cfgr_mask |= I2S_CGFR_FIXCH;
533 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
535 cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
537 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
542 fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
543 cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
545 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
546 I2S_CFG1_FTHVL_MASK, cfg1);
549 static int stm32_i2s_startup(struct snd_pcm_substream *substream,
550 struct snd_soc_dai *cpu_dai)
552 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
556 spin_lock_irqsave(&i2s->irq_lock, flags);
557 i2s->substream = substream;
558 spin_unlock_irqrestore(&i2s->irq_lock, flags);
560 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
561 snd_pcm_hw_constraint_single(substream->runtime,
562 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
564 ret = clk_prepare_enable(i2s->i2sclk);
566 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
570 return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
571 I2S_IFCR_MASK, I2S_IFCR_MASK);
574 static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
575 struct snd_pcm_hw_params *params,
576 struct snd_soc_dai *cpu_dai)
578 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
581 ret = stm32_i2s_configure(cpu_dai, params, substream);
583 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
587 if (STM32_I2S_IS_MASTER(i2s))
588 ret = stm32_i2s_configure_clock(cpu_dai, params);
593 static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
594 struct snd_soc_dai *cpu_dai)
596 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
597 bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
602 case SNDRV_PCM_TRIGGER_START:
603 case SNDRV_PCM_TRIGGER_RESUME:
604 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
606 dev_dbg(cpu_dai->dev, "start I2S %s\n",
607 playback_flg ? "playback" : "capture");
609 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
610 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
611 cfg1_mask, cfg1_mask);
613 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
614 I2S_CR1_SPE, I2S_CR1_SPE);
616 dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
620 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
621 I2S_CR1_CSTART, I2S_CR1_CSTART);
623 dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
627 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
628 I2S_IFCR_MASK, I2S_IFCR_MASK);
630 spin_lock(&i2s->lock_fd);
637 if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
638 /* dummy write to gate bus clocks */
639 regmap_write(i2s->regmap,
640 STM32_I2S_TXDR_REG, 0);
642 spin_unlock(&i2s->lock_fd);
644 if (STM32_I2S_IS_SLAVE(i2s))
645 ier |= I2S_IER_TIFREIE;
647 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
649 case SNDRV_PCM_TRIGGER_STOP:
650 case SNDRV_PCM_TRIGGER_SUSPEND:
651 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
652 dev_dbg(cpu_dai->dev, "stop I2S %s\n",
653 playback_flg ? "playback" : "capture");
656 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
658 (unsigned int)~I2S_IER_UDRIE);
660 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
662 (unsigned int)~I2S_IER_OVRIE);
664 spin_lock(&i2s->lock_fd);
667 spin_unlock(&i2s->lock_fd);
671 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
674 dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
675 spin_unlock(&i2s->lock_fd);
678 spin_unlock(&i2s->lock_fd);
680 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
681 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
691 static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
692 struct snd_soc_dai *cpu_dai)
694 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
697 regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
698 I2S_CGFR_MCKOE, (unsigned int)~I2S_CGFR_MCKOE);
700 clk_disable_unprepare(i2s->i2sclk);
702 spin_lock_irqsave(&i2s->irq_lock, flags);
703 i2s->substream = NULL;
704 spin_unlock_irqrestore(&i2s->irq_lock, flags);
707 static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
709 struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
710 struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
711 struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
713 /* Buswidth will be set by framework */
714 dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
715 dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
716 dma_data_tx->maxburst = 1;
717 dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
718 dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
719 dma_data_rx->maxburst = 1;
721 snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
726 static const struct regmap_config stm32_h7_i2s_regmap_conf = {
730 .max_register = STM32_I2S_SIDR_REG,
731 .readable_reg = stm32_i2s_readable_reg,
732 .volatile_reg = stm32_i2s_volatile_reg,
733 .writeable_reg = stm32_i2s_writeable_reg,
734 .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
736 .cache_type = REGCACHE_FLAT,
739 static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
740 .set_sysclk = stm32_i2s_set_sysclk,
741 .set_fmt = stm32_i2s_set_dai_fmt,
742 .startup = stm32_i2s_startup,
743 .hw_params = stm32_i2s_hw_params,
744 .trigger = stm32_i2s_trigger,
745 .shutdown = stm32_i2s_shutdown,
748 static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
749 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
750 .buffer_bytes_max = 8 * PAGE_SIZE,
751 .period_bytes_min = 1024,
752 .period_bytes_max = 4 * PAGE_SIZE,
757 static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
758 .pcm_hardware = &stm32_i2s_pcm_hw,
759 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
760 .prealloc_buffer_size = PAGE_SIZE * 8,
763 static const struct snd_soc_component_driver stm32_i2s_component = {
767 static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
770 stream->stream_name = stream_name;
771 stream->channels_min = 1;
772 stream->channels_max = 2;
773 stream->rates = SNDRV_PCM_RATE_8000_192000;
774 stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
775 SNDRV_PCM_FMTBIT_S32_LE;
778 static int stm32_i2s_dais_init(struct platform_device *pdev,
779 struct stm32_i2s_data *i2s)
781 struct snd_soc_dai_driver *dai_ptr;
783 dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
788 dai_ptr->probe = stm32_i2s_dai_probe;
789 dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
791 stm32_i2s_dai_init(&dai_ptr->playback, "playback");
792 stm32_i2s_dai_init(&dai_ptr->capture, "capture");
793 i2s->dai_drv = dai_ptr;
798 static const struct of_device_id stm32_i2s_ids[] = {
800 .compatible = "st,stm32h7-i2s",
801 .data = &stm32_h7_i2s_regmap_conf
806 static int stm32_i2s_parse_dt(struct platform_device *pdev,
807 struct stm32_i2s_data *i2s)
809 struct device_node *np = pdev->dev.of_node;
810 const struct of_device_id *of_id;
811 struct reset_control *rst;
812 struct resource *res;
818 of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
820 i2s->regmap_conf = (const struct regmap_config *)of_id->data;
824 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
825 i2s->base = devm_ioremap_resource(&pdev->dev, res);
826 if (IS_ERR(i2s->base))
827 return PTR_ERR(i2s->base);
829 i2s->phys_addr = res->start;
832 i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
833 if (IS_ERR(i2s->pclk)) {
834 dev_err(&pdev->dev, "Could not get pclk\n");
835 return PTR_ERR(i2s->pclk);
838 i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
839 if (IS_ERR(i2s->i2sclk)) {
840 dev_err(&pdev->dev, "Could not get i2sclk\n");
841 return PTR_ERR(i2s->i2sclk);
844 i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
845 if (IS_ERR(i2s->x8kclk)) {
846 dev_err(&pdev->dev, "missing x8k parent clock\n");
847 return PTR_ERR(i2s->x8kclk);
850 i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
851 if (IS_ERR(i2s->x11kclk)) {
852 dev_err(&pdev->dev, "missing x11k parent clock\n");
853 return PTR_ERR(i2s->x11kclk);
857 irq = platform_get_irq(pdev, 0);
861 ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,
862 dev_name(&pdev->dev), i2s);
864 dev_err(&pdev->dev, "irq request returned %d\n", ret);
869 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
871 reset_control_assert(rst);
873 reset_control_deassert(rst);
879 static int stm32_i2s_probe(struct platform_device *pdev)
881 struct stm32_i2s_data *i2s;
885 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
889 ret = stm32_i2s_parse_dt(pdev, i2s);
894 i2s->ms_flg = I2S_MS_NOT_SET;
895 spin_lock_init(&i2s->lock_fd);
896 spin_lock_init(&i2s->irq_lock);
897 platform_set_drvdata(pdev, i2s);
899 ret = stm32_i2s_dais_init(pdev, i2s);
903 i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
904 i2s->base, i2s->regmap_conf);
905 if (IS_ERR(i2s->regmap)) {
906 dev_err(&pdev->dev, "regmap init failed\n");
907 return PTR_ERR(i2s->regmap);
910 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
915 ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
916 &stm32_i2s_pcm_config, 0);
920 /* Set SPI/I2S in i2s mode */
921 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
922 I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
926 ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
930 if (val == I2S_IPIDR_NUMBER) {
931 ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
935 if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
937 "Device does not support i2s mode\n");
941 ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
943 dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
944 FIELD_GET(I2S_VERR_MAJ_MASK, val),
945 FIELD_GET(I2S_VERR_MIN_MASK, val));
951 MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
953 #ifdef CONFIG_PM_SLEEP
954 static int stm32_i2s_suspend(struct device *dev)
956 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
958 regcache_cache_only(i2s->regmap, true);
959 regcache_mark_dirty(i2s->regmap);
964 static int stm32_i2s_resume(struct device *dev)
966 struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
968 regcache_cache_only(i2s->regmap, false);
969 return regcache_sync(i2s->regmap);
971 #endif /* CONFIG_PM_SLEEP */
973 static const struct dev_pm_ops stm32_i2s_pm_ops = {
974 SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
977 static struct platform_driver stm32_i2s_driver = {
979 .name = "st,stm32-i2s",
980 .of_match_table = stm32_i2s_ids,
981 .pm = &stm32_i2s_pm_ops,
983 .probe = stm32_i2s_probe,
986 module_platform_driver(stm32_i2s_driver);
988 MODULE_DESCRIPTION("STM32 Soc i2s Interface");
989 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
990 MODULE_ALIAS("platform:stm32-i2s");
991 MODULE_LICENSE("GPL v2");