1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2022 Intel Corporation. All rights reserved.
9 #include <sound/pcm_params.h>
10 #include <sound/sof/ipc4/header.h>
11 #include "sof-audio.h"
14 #include "ipc4-priv.h"
15 #include "ipc4-topology.h"
16 #include "ipc4-fw-reg.h"
18 static int sof_ipc4_set_multi_pipeline_state(struct snd_sof_dev *sdev, u32 state,
19 struct ipc4_pipeline_set_state_data *trigger_list)
21 struct sof_ipc4_msg msg = {{ 0 }};
22 u32 primary, ipc_size;
24 /* trigger a single pipeline */
25 if (trigger_list->count == 1)
26 return sof_ipc4_set_pipeline_state(sdev, trigger_list->pipeline_instance_ids[0],
30 primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
31 primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
32 primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
33 msg.primary = primary;
35 /* trigger multiple pipelines with a single IPC */
36 msg.extension = SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI;
38 /* ipc_size includes the count and the pipeline IDs for the number of pipelines */
39 ipc_size = sizeof(u32) * (trigger_list->count + 1);
40 msg.data_size = ipc_size;
41 msg.data_ptr = trigger_list;
43 return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, ipc_size);
46 int sof_ipc4_set_pipeline_state(struct snd_sof_dev *sdev, u32 instance_id, u32 state)
48 struct sof_ipc4_msg msg = {{ 0 }};
51 dev_dbg(sdev->dev, "ipc4 set pipeline instance %d state %d", instance_id, state);
54 primary |= SOF_IPC4_GLB_PIPE_STATE_ID(instance_id);
55 primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
56 primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
57 primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
59 msg.primary = primary;
61 return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
63 EXPORT_SYMBOL(sof_ipc4_set_pipeline_state);
65 static void sof_ipc4_add_pipeline_by_priority(struct ipc4_pipeline_set_state_data *trigger_list,
66 struct snd_sof_widget *pipe_widget,
67 s8 *pipe_priority, bool ascend)
69 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
72 for (i = 0; i < trigger_list->count; i++) {
73 /* add pipeline from low priority to high */
74 if (ascend && pipeline->priority < pipe_priority[i])
76 /* add pipeline from high priority to low */
77 else if (!ascend && pipeline->priority > pipe_priority[i])
81 for (j = trigger_list->count - 1; j >= i; j--) {
82 trigger_list->pipeline_instance_ids[j + 1] = trigger_list->pipeline_instance_ids[j];
83 pipe_priority[j + 1] = pipe_priority[j];
86 trigger_list->pipeline_instance_ids[i] = pipe_widget->instance_id;
87 trigger_list->count++;
88 pipe_priority[i] = pipeline->priority;
92 sof_ipc4_add_pipeline_to_trigger_list(struct snd_sof_dev *sdev, int state,
93 struct snd_sof_pipeline *spipe,
94 struct ipc4_pipeline_set_state_data *trigger_list,
97 struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
98 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
100 if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
104 case SOF_IPC4_PIPE_RUNNING:
106 * Trigger pipeline if all PCMs containing it are paused or if it is RUNNING
109 if (spipe->started_count == spipe->paused_count)
110 sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
113 case SOF_IPC4_PIPE_RESET:
114 /* RESET if the pipeline is neither running nor paused */
115 if (!spipe->started_count && !spipe->paused_count)
116 sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
119 case SOF_IPC4_PIPE_PAUSED:
120 /* Pause the pipeline only when its started_count is 1 more than paused_count */
121 if (spipe->paused_count == (spipe->started_count - 1))
122 sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
131 sof_ipc4_update_pipeline_state(struct snd_sof_dev *sdev, int state, int cmd,
132 struct snd_sof_pipeline *spipe,
133 struct ipc4_pipeline_set_state_data *trigger_list)
135 struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
136 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
139 if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
142 /* set state for pipeline if it was just triggered */
143 for (i = 0; i < trigger_list->count; i++) {
144 if (trigger_list->pipeline_instance_ids[i] == pipe_widget->instance_id) {
145 pipeline->state = state;
151 case SOF_IPC4_PIPE_PAUSED:
153 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
155 * increment paused_count if the PAUSED is the final state during
158 spipe->paused_count++;
160 case SNDRV_PCM_TRIGGER_STOP:
161 case SNDRV_PCM_TRIGGER_SUSPEND:
163 * decrement started_count if PAUSED is the final state during the
166 spipe->started_count--;
172 case SOF_IPC4_PIPE_RUNNING:
174 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
175 /* decrement paused_count for RELEASE */
176 spipe->paused_count--;
178 case SNDRV_PCM_TRIGGER_START:
179 case SNDRV_PCM_TRIGGER_RESUME:
180 /* increment started_count for START/RESUME */
181 spipe->started_count++;
193 * The picture below represents the pipeline state machine wrt PCM actions corresponding to the
194 * triggers and ioctls
205 * +----------------+ +------v-------+ +-------------+
206 * | | START | | HW_FREE | |
207 * | RUNNING <-------------+ PAUSED +--------------> + RESET |
209 * +------+---------+ RELEASE +---------+----+ +-------------+
215 * +---------------------------------+
218 * Note that during system suspend, the suspend trigger is followed by a hw_free in
219 * sof_pcm_trigger(). So, the final state during suspend would be RESET.
220 * Also, since the SOF driver doesn't support full resume, streams would be restarted with the
221 * prepare ioctl before the START trigger.
225 * Chained DMA is a special case where there is no processing on
226 * DSP. The samples are just moved over by host side DMA to a single
227 * buffer on DSP and directly from there to link DMA. However, the
228 * model on SOF driver has two notional pipelines, one at host DAI,
229 * and another at link DAI. They both shall have the use_chain_dma
233 static int sof_ipc4_chain_dma_trigger(struct snd_sof_dev *sdev,
234 struct snd_sof_pcm_stream_pipeline_list *pipeline_list,
237 bool allocate, enable, set_fifo_size;
238 struct sof_ipc4_msg msg = {{ 0 }};
242 case SOF_IPC4_PIPE_RUNNING: /* Allocate and start chained dma */
246 * SOF assumes creation of a new stream from the presence of fifo_size
247 * in the message, so we must leave it out in pause release case.
249 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
250 set_fifo_size = false;
252 set_fifo_size = true;
254 case SOF_IPC4_PIPE_PAUSED: /* Disable chained DMA. */
257 set_fifo_size = false;
259 case SOF_IPC4_PIPE_RESET: /* Disable and free chained DMA. */
262 set_fifo_size = false;
265 dev_err(sdev->dev, "Unexpected state %d", state);
269 msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_CHAIN_DMA);
270 msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
271 msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
274 * To set-up the DMA chain, the host DMA ID and SCS setting
275 * are retrieved from the host pipeline configuration. Likewise
276 * the link DMA ID and fifo_size are retrieved from the link
277 * pipeline configuration.
279 for (i = 0; i < pipeline_list->count; i++) {
280 struct snd_sof_pipeline *spipe = pipeline_list->pipelines[i];
281 struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
282 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
284 if (!pipeline->use_chain_dma) {
286 "All pipelines in chained DMA stream should have use_chain_dma attribute set.");
290 msg.primary |= pipeline->msg.primary;
292 /* Add fifo_size (actually DMA buffer size) field to the message */
294 msg.extension |= pipeline->msg.extension;
298 msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK;
301 msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK;
303 return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
306 static int sof_ipc4_trigger_pipelines(struct snd_soc_component *component,
307 struct snd_pcm_substream *substream, int state, int cmd)
309 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
310 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
311 struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
312 struct sof_ipc4_fw_data *ipc4_data = sdev->private;
313 struct ipc4_pipeline_set_state_data *trigger_list;
314 struct snd_sof_widget *pipe_widget;
315 struct sof_ipc4_pipeline *pipeline;
316 struct snd_sof_pipeline *spipe;
317 struct snd_sof_pcm *spcm;
322 dev_dbg(sdev->dev, "trigger cmd: %d state: %d\n", cmd, state);
324 spcm = snd_sof_find_spcm_dai(component, rtd);
328 pipeline_list = &spcm->stream[substream->stream].pipeline_list;
330 /* nothing to trigger if the list is empty */
331 if (!pipeline_list->pipelines || !pipeline_list->count)
334 spipe = pipeline_list->pipelines[0];
335 pipe_widget = spipe->pipe_widget;
336 pipeline = pipe_widget->private;
339 * If use_chain_dma attribute is set we proceed to chained DMA
340 * trigger function that handles the rest for the substream.
342 if (pipeline->use_chain_dma)
343 return sof_ipc4_chain_dma_trigger(sdev, pipeline_list, state, cmd);
345 /* allocate memory for the pipeline data */
346 trigger_list = kzalloc(struct_size(trigger_list, pipeline_instance_ids,
347 pipeline_list->count), GFP_KERNEL);
351 pipe_priority = kzalloc(pipeline_list->count, GFP_KERNEL);
352 if (!pipe_priority) {
357 mutex_lock(&ipc4_data->pipeline_state_mutex);
360 * IPC4 requires pipelines to be triggered in order starting at the sink and
361 * walking all the way to the source. So traverse the pipeline_list in the order
362 * sink->source when starting PCM's and in the reverse order to pause/stop PCM's.
363 * Skip the pipelines that have their skip_during_fe_trigger flag set. If there is a fork
364 * in the pipeline, the order of triggering between the left/right paths will be
365 * indeterministic. But the sink->source trigger order sink->source would still be
366 * guaranteed for each fork independently.
368 if (state == SOF_IPC4_PIPE_RUNNING || state == SOF_IPC4_PIPE_RESET)
369 for (i = pipeline_list->count - 1; i >= 0; i--) {
370 spipe = pipeline_list->pipelines[i];
371 sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list,
375 for (i = 0; i < pipeline_list->count; i++) {
376 spipe = pipeline_list->pipelines[i];
377 sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list,
381 /* return if all pipelines are in the requested state already */
382 if (!trigger_list->count) {
387 /* no need to pause before reset or before pause release */
388 if (state == SOF_IPC4_PIPE_RESET || cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
389 goto skip_pause_transition;
392 * set paused state for pipelines if the final state is PAUSED or when the pipeline
393 * is set to RUNNING for the first time after the PCM is started.
395 ret = sof_ipc4_set_multi_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, trigger_list);
397 dev_err(sdev->dev, "failed to pause all pipelines\n");
401 /* update PAUSED state for all pipelines just triggered */
402 for (i = 0; i < pipeline_list->count ; i++) {
403 spipe = pipeline_list->pipelines[i];
404 sof_ipc4_update_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, cmd, spipe,
408 /* return if this is the final state */
409 if (state == SOF_IPC4_PIPE_PAUSED)
411 skip_pause_transition:
412 /* else set the RUNNING/RESET state in the DSP */
413 ret = sof_ipc4_set_multi_pipeline_state(sdev, state, trigger_list);
415 dev_err(sdev->dev, "failed to set final state %d for all pipelines\n", state);
419 /* update RUNNING/RESET state for all pipelines that were just triggered */
420 for (i = 0; i < pipeline_list->count; i++) {
421 spipe = pipeline_list->pipelines[i];
422 sof_ipc4_update_pipeline_state(sdev, state, cmd, spipe, trigger_list);
426 mutex_unlock(&ipc4_data->pipeline_state_mutex);
428 kfree(pipe_priority);
432 static int sof_ipc4_pcm_trigger(struct snd_soc_component *component,
433 struct snd_pcm_substream *substream, int cmd)
437 /* determine the pipeline state */
439 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
440 state = SOF_IPC4_PIPE_PAUSED;
442 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
443 case SNDRV_PCM_TRIGGER_RESUME:
444 case SNDRV_PCM_TRIGGER_START:
445 state = SOF_IPC4_PIPE_RUNNING;
447 case SNDRV_PCM_TRIGGER_SUSPEND:
448 case SNDRV_PCM_TRIGGER_STOP:
449 state = SOF_IPC4_PIPE_PAUSED;
452 dev_err(component->dev, "%s: unhandled trigger cmd %d\n", __func__, cmd);
456 /* set the pipeline state */
457 return sof_ipc4_trigger_pipelines(component, substream, state, cmd);
460 static int sof_ipc4_pcm_hw_free(struct snd_soc_component *component,
461 struct snd_pcm_substream *substream)
463 /* command is not relevant with RESET, so just pass 0 */
464 return sof_ipc4_trigger_pipelines(component, substream, SOF_IPC4_PIPE_RESET, 0);
467 static void ipc4_ssp_dai_config_pcm_params_match(struct snd_sof_dev *sdev, const char *link_name,
468 struct snd_pcm_hw_params *params)
470 struct snd_sof_dai_link *slink;
471 struct snd_sof_dai *dai;
472 bool dai_link_found = false;
475 list_for_each_entry(slink, &sdev->dai_link_list, list) {
476 if (!strcmp(slink->link->name, link_name)) {
477 dai_link_found = true;
485 for (i = 0; i < slink->num_hw_configs; i++) {
486 struct snd_soc_tplg_hw_config *hw_config = &slink->hw_configs[i];
488 if (params_rate(params) == le32_to_cpu(hw_config->fsync_rate)) {
489 /* set current config for all DAI's with matching name */
490 list_for_each_entry(dai, &sdev->dai_list, list)
491 if (!strcmp(slink->link->name, dai->name))
492 dai->current_config = le32_to_cpu(hw_config->id);
499 * Fixup DAI link parameters for sampling rate based on
500 * DAI copier configuration.
502 static int sof_ipc4_pcm_dai_link_fixup_rate(struct snd_sof_dev *sdev,
503 struct snd_pcm_hw_params *params,
504 struct sof_ipc4_copier *ipc4_copier)
506 struct sof_ipc4_pin_format *pin_fmts = ipc4_copier->available_fmt.input_pin_fmts;
507 struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
508 int num_input_formats = ipc4_copier->available_fmt.num_input_formats;
509 unsigned int fe_rate = params_rate(params);
510 bool fe_be_rate_match = false;
511 bool single_be_rate = true;
512 unsigned int be_rate;
516 * Copier does not change sampling rate, so we
517 * need to only consider the input pin information.
519 for (i = 0; i < num_input_formats; i++) {
520 unsigned int val = pin_fmts[i].audio_fmt.sampling_frequency;
524 else if (val != be_rate)
525 single_be_rate = false;
527 if (val == fe_rate) {
528 fe_be_rate_match = true;
534 * If rate is different than FE rate, topology must
535 * contain an SRC. But we do require topology to
536 * define a single rate in the DAI copier config in
537 * this case (FE rate may be variable).
539 if (!fe_be_rate_match) {
540 if (!single_be_rate) {
541 dev_err(sdev->dev, "Unable to select sampling rate for DAI link\n");
546 rate->max = rate->min;
552 static int sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
553 struct snd_pcm_hw_params *params)
555 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
556 struct snd_sof_dai *dai = snd_sof_find_dai(component, rtd->dai_link->name);
557 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
558 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
559 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
560 struct sof_ipc4_audio_format *ipc4_fmt;
561 struct sof_ipc4_copier *ipc4_copier;
562 bool single_fmt = false;
567 dev_err(component->dev, "%s: No DAI found with name %s\n", __func__,
568 rtd->dai_link->name);
572 ipc4_copier = dai->private;
574 dev_err(component->dev, "%s: No private data found for DAI %s\n",
575 __func__, rtd->dai_link->name);
579 for_each_pcm_streams(dir) {
580 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(cpu_dai, dir);
583 struct sof_ipc4_available_audio_format *available_fmt =
584 &ipc4_copier->available_fmt;
585 struct snd_sof_widget *swidget = w->dobj.private;
586 struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget;
587 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
589 /* Chain DMA does not use copiers, so no fixup needed */
590 if (pipeline->use_chain_dma)
593 if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
594 if (sof_ipc4_copier_is_single_format(sdev,
595 available_fmt->output_pin_fmts,
596 available_fmt->num_output_formats)) {
597 ipc4_fmt = &available_fmt->output_pin_fmts->audio_fmt;
601 if (sof_ipc4_copier_is_single_format(sdev,
602 available_fmt->input_pin_fmts,
603 available_fmt->num_input_formats)) {
604 ipc4_fmt = &available_fmt->input_pin_fmts->audio_fmt;
611 ret = sof_ipc4_pcm_dai_link_fixup_rate(sdev, params, ipc4_copier);
617 valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(ipc4_fmt->fmt_cfg);
618 dev_dbg(component->dev, "Set %s to %d bit format\n", dai->name, valid_bits);
621 /* Set format if it is specified */
622 switch (valid_bits) {
624 snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
627 snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S24_LE);
630 snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S32_LE);
636 switch (ipc4_copier->dai_type) {
637 case SOF_DAI_INTEL_SSP:
638 ipc4_ssp_dai_config_pcm_params_match(sdev, (char *)rtd->dai_link->name, params);
647 static void sof_ipc4_pcm_free(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
649 struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
652 for_each_pcm_streams(stream) {
653 pipeline_list = &spcm->stream[stream].pipeline_list;
654 kfree(pipeline_list->pipelines);
655 pipeline_list->pipelines = NULL;
656 kfree(spcm->stream[stream].private);
657 spcm->stream[stream].private = NULL;
661 static int sof_ipc4_pcm_setup(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
663 struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
664 struct sof_ipc4_fw_data *ipc4_data = sdev->private;
665 struct sof_ipc4_timestamp_info *stream_info;
666 bool support_info = true;
671 abi_offset = offsetof(struct sof_ipc4_fw_registers, abi_ver);
672 sof_mailbox_read(sdev, sdev->fw_info_box.offset + abi_offset, &abi_version,
673 sizeof(abi_version));
675 if (abi_version < SOF_IPC4_FW_REGS_ABI_VER)
676 support_info = false;
678 for_each_pcm_streams(stream) {
679 pipeline_list = &spcm->stream[stream].pipeline_list;
681 /* allocate memory for max number of pipeline IDs */
682 pipeline_list->pipelines = kcalloc(ipc4_data->max_num_pipelines,
683 sizeof(struct snd_sof_widget *), GFP_KERNEL);
684 if (!pipeline_list->pipelines) {
685 sof_ipc4_pcm_free(sdev, spcm);
692 stream_info = kzalloc(sizeof(*stream_info), GFP_KERNEL);
694 sof_ipc4_pcm_free(sdev, spcm);
698 spcm->stream[stream].private = stream_info;
704 static void sof_ipc4_build_time_info(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *spcm)
706 struct sof_ipc4_copier *host_copier = NULL;
707 struct sof_ipc4_copier *dai_copier = NULL;
708 struct sof_ipc4_llp_reading_slot llp_slot;
709 struct sof_ipc4_timestamp_info *info;
710 struct snd_soc_dapm_widget *widget;
711 struct snd_sof_dai *dai;
714 /* find host & dai to locate info in memory window */
715 for_each_dapm_widgets(spcm->list, i, widget) {
716 struct snd_sof_widget *swidget = widget->dobj.private;
721 if (WIDGET_IS_AIF(swidget->widget->id)) {
722 host_copier = swidget->private;
723 } else if (WIDGET_IS_DAI(swidget->widget->id)) {
724 dai = swidget->private;
725 dai_copier = dai->private;
729 /* both host and dai copier must be valid for time_info */
730 if (!host_copier || !dai_copier) {
731 dev_err(sdev->dev, "host or dai copier are not found\n");
735 info = spcm->private;
736 info->host_copier = host_copier;
737 info->dai_copier = dai_copier;
738 info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_gpdma_reading_slots) +
739 sdev->fw_info_box.offset;
741 /* find llp slot used by current dai */
742 for (i = 0; i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS; i++) {
743 sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
744 if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
747 info->llp_offset += sizeof(llp_slot);
750 if (i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS)
753 /* if no llp gpdma slot is used, check aggregated sdw slot */
754 info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_sndw_reading_slots) +
755 sdev->fw_info_box.offset;
756 for (i = 0; i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS; i++) {
757 sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
758 if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
761 info->llp_offset += sizeof(llp_slot);
764 if (i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS)
767 /* check EVAD slot */
768 info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_evad_reading_slot) +
769 sdev->fw_info_box.offset;
770 sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
771 if (llp_slot.node_id != dai_copier->data.gtw_cfg.node_id) {
772 dev_info(sdev->dev, "no llp found, fall back to default HDA path");
773 info->llp_offset = 0;
777 static int sof_ipc4_pcm_hw_params(struct snd_soc_component *component,
778 struct snd_pcm_substream *substream,
779 struct snd_pcm_hw_params *params,
780 struct snd_sof_platform_stream_params *platform_params)
782 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
783 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
784 struct sof_ipc4_timestamp_info *time_info;
785 struct snd_sof_pcm *spcm;
787 spcm = snd_sof_find_spcm_dai(component, rtd);
791 time_info = spcm->stream[substream->stream].private;
792 /* delay calculation is not supported by current fw_reg ABI */
796 time_info->stream_start_offset = SOF_IPC4_INVALID_STREAM_POSITION;
797 time_info->llp_offset = 0;
799 sof_ipc4_build_time_info(sdev, &spcm->stream[substream->stream]);
804 static int sof_ipc4_get_stream_start_offset(struct snd_sof_dev *sdev,
805 struct snd_pcm_substream *substream,
806 struct snd_sof_pcm_stream *stream,
807 struct sof_ipc4_timestamp_info *time_info)
809 struct sof_ipc4_copier *host_copier = time_info->host_copier;
810 struct sof_ipc4_copier *dai_copier = time_info->dai_copier;
811 struct sof_ipc4_pipeline_registers ppl_reg;
812 u64 stream_start_position;
817 if (!host_copier || !dai_copier)
820 if (host_copier->data.gtw_cfg.node_id == SOF_IPC4_INVALID_NODE_ID)
823 node_index = SOF_IPC4_NODE_INDEX(host_copier->data.gtw_cfg.node_id);
824 offset = offsetof(struct sof_ipc4_fw_registers, pipeline_regs) + node_index * sizeof(ppl_reg);
825 sof_mailbox_read(sdev, sdev->fw_info_box.offset + offset, &ppl_reg, sizeof(ppl_reg));
826 if (ppl_reg.stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION)
829 stream_start_position = ppl_reg.stream_start_offset;
830 ch = dai_copier->data.out_format.fmt_cfg;
831 ch = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(ch);
832 dai_sample_size = (dai_copier->data.out_format.bit_depth >> 3) * ch;
833 /* convert offset to sample count */
834 do_div(stream_start_position, dai_sample_size);
835 time_info->stream_start_offset = stream_start_position;
840 static snd_pcm_sframes_t sof_ipc4_pcm_delay(struct snd_soc_component *component,
841 struct snd_pcm_substream *substream)
843 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
844 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
845 struct sof_ipc4_timestamp_info *time_info;
846 struct sof_ipc4_llp_reading_slot llp;
847 snd_pcm_uframes_t head_ptr, tail_ptr;
848 struct snd_sof_pcm_stream *stream;
849 struct snd_sof_pcm *spcm;
853 spcm = snd_sof_find_spcm_dai(component, rtd);
857 stream = &spcm->stream[substream->stream];
858 time_info = stream->private;
863 * stream_start_offset is updated to memory window by FW based on
864 * pipeline statistics and it may be invalid if host query happens before
865 * the statistics is complete. And it will not change after the first initiailization.
867 if (time_info->stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION) {
868 ret = sof_ipc4_get_stream_start_offset(sdev, substream, stream, time_info);
874 * HDaudio links don't support the LLP counter reported by firmware
875 * the link position is read directly from hardware registers.
877 if (!time_info->llp_offset) {
878 tmp_ptr = snd_sof_pcm_get_stream_position(sdev, component, substream);
882 sof_mailbox_read(sdev, time_info->llp_offset, &llp, sizeof(llp));
883 tmp_ptr = ((u64)llp.reading.llp_u << 32) | llp.reading.llp_l;
886 /* In two cases dai dma position is not accurate
887 * (1) dai pipeline is started before host pipeline
888 * (2) multiple streams mixed into one. Each stream has the same dai dma position
890 * Firmware calculates correct stream_start_offset for all cases including above two.
891 * Driver subtracts stream_start_offset from dai dma position to get accurate one
893 tmp_ptr -= time_info->stream_start_offset;
895 /* Calculate the delay taking into account that both pointer can wrap */
896 div64_u64_rem(tmp_ptr, substream->runtime->boundary, &tmp_ptr);
897 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
898 head_ptr = substream->runtime->status->hw_ptr;
902 tail_ptr = substream->runtime->status->hw_ptr;
905 if (head_ptr < tail_ptr)
906 return substream->runtime->boundary - tail_ptr + head_ptr;
908 return head_ptr - tail_ptr;
911 const struct sof_ipc_pcm_ops ipc4_pcm_ops = {
912 .hw_params = sof_ipc4_pcm_hw_params,
913 .trigger = sof_ipc4_pcm_trigger,
914 .hw_free = sof_ipc4_pcm_hw_free,
915 .dai_link_fixup = sof_ipc4_pcm_dai_link_fixup,
916 .pcm_setup = sof_ipc4_pcm_setup,
917 .pcm_free = sof_ipc4_pcm_free,
918 .delay = sof_ipc4_pcm_delay,
919 .ipc_first_on_start = true,
920 .platform_stop_during_hw_free = true,