1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
5 // Author: Daniel Baluta <daniel.baluta@nxp.com>
7 // Hardware interface for audio DSP on i.MX8
9 #include <linux/firmware.h>
10 #include <linux/of_platform.h>
11 #include <linux/of_address.h>
12 #include <linux/of_irq.h>
13 #include <linux/pm_domain.h>
15 #include <linux/module.h>
16 #include <sound/sof.h>
17 #include <sound/sof/xtensa.h>
18 #include <linux/firmware/imx/ipc.h>
19 #include <linux/firmware/imx/dsp.h>
21 #include <linux/firmware/imx/svc/misc.h>
22 #include <dt-bindings/firmware/imx/rsrc.h>
24 #include "../sof-of-dev.h"
25 #include "imx-common.h"
28 #define IRAM_OFFSET 0x10000
29 #define IRAM_SIZE (2 * 1024)
30 #define DRAM0_OFFSET 0x0
31 #define DRAM0_SIZE (32 * 1024)
32 #define DRAM1_OFFSET 0x8000
33 #define DRAM1_SIZE (32 * 1024)
34 #define SYSRAM_OFFSET 0x18000
35 #define SYSRAM_SIZE (256 * 1024)
36 #define SYSROM_OFFSET 0x58000
37 #define SYSROM_SIZE (192 * 1024)
39 #define RESET_VECTOR_VADDR 0x596f8000
41 #define MBOX_OFFSET 0x800000
42 #define MBOX_SIZE 0x1000
45 static struct clk_bulk_data imx8_dsp_clks[] = {
53 struct snd_sof_dev *sdev;
56 struct imx_dsp_ipc *dsp_ipc;
57 struct platform_device *ipc_dev;
59 /* System Controller IPC handler */
60 struct imx_sc_ipc *sc_ipc;
62 /* Power domain handling */
64 struct device **pd_dev;
65 struct device_link **link;
67 struct imx_clocks *clks;
70 static int imx8_get_mailbox_offset(struct snd_sof_dev *sdev)
75 static int imx8_get_window_offset(struct snd_sof_dev *sdev, u32 id)
80 static void imx8_dsp_handle_reply(struct imx_dsp_ipc *ipc)
82 struct imx8_priv *priv = imx_dsp_get_data(ipc);
85 spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
86 snd_sof_ipc_process_reply(priv->sdev, 0);
87 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
90 static void imx8_dsp_handle_request(struct imx_dsp_ipc *ipc)
92 struct imx8_priv *priv = imx_dsp_get_data(ipc);
93 u32 p; /* panic code */
95 /* Read the message from the debug box. */
96 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
98 /* Check to see if the message is a panic code (0x0dead***) */
99 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
100 snd_sof_dsp_panic(priv->sdev, p, true);
102 snd_sof_ipc_msgs_rx(priv->sdev);
105 static struct imx_dsp_ops dsp_ops = {
106 .handle_reply = imx8_dsp_handle_reply,
107 .handle_request = imx8_dsp_handle_request,
110 static int imx8_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
112 struct imx8_priv *priv = sdev->pdata->hw_pdata;
114 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
116 imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
124 static int imx8x_run(struct snd_sof_dev *sdev)
126 struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata;
129 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
130 IMX_SC_C_OFS_SEL, 1);
132 dev_err(sdev->dev, "Error system address offset source select\n");
136 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
137 IMX_SC_C_OFS_AUDIO, 0x80);
139 dev_err(sdev->dev, "Error system address offset of AUDIO\n");
143 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
144 IMX_SC_C_OFS_PERIPH, 0x5A);
146 dev_err(sdev->dev, "Error system address offset of PERIPH %d\n",
151 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
152 IMX_SC_C_OFS_IRQ, 0x51);
154 dev_err(sdev->dev, "Error system address offset of IRQ\n");
158 imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true,
164 static int imx8_run(struct snd_sof_dev *sdev)
166 struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata;
169 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
170 IMX_SC_C_OFS_SEL, 0);
172 dev_err(sdev->dev, "Error system address offset source select\n");
176 imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true,
182 static int imx8_probe(struct snd_sof_dev *sdev)
184 struct platform_device *pdev =
185 container_of(sdev->dev, struct platform_device, dev);
186 struct device_node *np = pdev->dev.of_node;
187 struct device_node *res_node;
188 struct resource *mmio;
189 struct imx8_priv *priv;
195 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
199 priv->clks = devm_kzalloc(&pdev->dev, sizeof(*priv->clks), GFP_KERNEL);
204 sdev->pdata->hw_pdata = priv;
205 priv->dev = sdev->dev;
208 /* power up device associated power domains */
209 priv->num_domains = of_count_phandle_with_args(np, "power-domains",
210 "#power-domain-cells");
211 if (priv->num_domains < 0) {
212 dev_err(sdev->dev, "no power-domains property in %pOF\n", np);
213 return priv->num_domains;
216 priv->pd_dev = devm_kmalloc_array(&pdev->dev, priv->num_domains,
217 sizeof(*priv->pd_dev), GFP_KERNEL);
221 priv->link = devm_kmalloc_array(&pdev->dev, priv->num_domains,
222 sizeof(*priv->link), GFP_KERNEL);
226 for (i = 0; i < priv->num_domains; i++) {
227 priv->pd_dev[i] = dev_pm_domain_attach_by_id(&pdev->dev, i);
228 if (IS_ERR(priv->pd_dev[i])) {
229 ret = PTR_ERR(priv->pd_dev[i]);
232 priv->link[i] = device_link_add(&pdev->dev, priv->pd_dev[i],
236 if (!priv->link[i]) {
238 dev_pm_domain_detach(priv->pd_dev[i], false);
243 ret = imx_scu_get_handle(&priv->sc_ipc);
245 dev_err(sdev->dev, "Cannot obtain SCU handle (err = %d)\n",
250 priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
252 pdev, sizeof(*pdev));
253 if (IS_ERR(priv->ipc_dev)) {
254 ret = PTR_ERR(priv->ipc_dev);
258 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
259 if (!priv->dsp_ipc) {
260 /* DSP IPC driver not probed yet, try later */
262 dev_err(sdev->dev, "Failed to get drvdata\n");
263 goto exit_pdev_unregister;
266 imx_dsp_set_data(priv->dsp_ipc, priv);
267 priv->dsp_ipc->ops = &dsp_ops;
270 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
273 size = resource_size(mmio);
275 dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
277 goto exit_pdev_unregister;
280 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
281 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
282 dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
285 goto exit_pdev_unregister;
287 sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
289 res_node = of_parse_phandle(np, "memory-region", 0);
291 dev_err(&pdev->dev, "failed to get memory region node\n");
293 goto exit_pdev_unregister;
296 ret = of_address_to_resource(res_node, 0, &res);
297 of_node_put(res_node);
299 dev_err(&pdev->dev, "failed to get reserved region address\n");
300 goto exit_pdev_unregister;
303 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
304 resource_size(&res));
305 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
306 dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
309 goto exit_pdev_unregister;
311 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
313 /* set default mailbox offset for FW ready message */
314 sdev->dsp_box.offset = MBOX_OFFSET;
316 /* init clocks info */
317 priv->clks->dsp_clks = imx8_dsp_clks;
318 priv->clks->num_dsp_clks = ARRAY_SIZE(imx8_dsp_clks);
320 ret = imx8_parse_clocks(sdev, priv->clks);
322 goto exit_pdev_unregister;
324 ret = imx8_enable_clocks(sdev, priv->clks);
326 goto exit_pdev_unregister;
330 exit_pdev_unregister:
331 platform_device_unregister(priv->ipc_dev);
334 device_link_del(priv->link[i]);
335 dev_pm_domain_detach(priv->pd_dev[i], false);
341 static void imx8_remove(struct snd_sof_dev *sdev)
343 struct imx8_priv *priv = sdev->pdata->hw_pdata;
346 imx8_disable_clocks(sdev, priv->clks);
347 platform_device_unregister(priv->ipc_dev);
349 for (i = 0; i < priv->num_domains; i++) {
350 device_link_del(priv->link[i]);
351 dev_pm_domain_detach(priv->pd_dev[i], false);
355 /* on i.MX8 there is 1 to 1 match between type and BAR idx */
356 static int imx8_get_bar_index(struct snd_sof_dev *sdev, u32 type)
358 /* Only IRAM and SRAM bars are valid */
360 case SOF_FW_BLK_TYPE_IRAM:
361 case SOF_FW_BLK_TYPE_SRAM:
368 static void imx8_suspend(struct snd_sof_dev *sdev)
371 struct imx8_priv *priv = (struct imx8_priv *)sdev->pdata->hw_pdata;
373 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
374 imx_dsp_free_channel(priv->dsp_ipc, i);
376 imx8_disable_clocks(sdev, priv->clks);
379 static int imx8_resume(struct snd_sof_dev *sdev)
381 struct imx8_priv *priv = (struct imx8_priv *)sdev->pdata->hw_pdata;
385 ret = imx8_enable_clocks(sdev, priv->clks);
389 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
390 imx_dsp_request_channel(priv->dsp_ipc, i);
395 static int imx8_dsp_runtime_resume(struct snd_sof_dev *sdev)
398 const struct sof_dsp_power_state target_dsp_state = {
399 .state = SOF_DSP_PM_D0,
402 ret = imx8_resume(sdev);
406 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
409 static int imx8_dsp_runtime_suspend(struct snd_sof_dev *sdev)
411 const struct sof_dsp_power_state target_dsp_state = {
412 .state = SOF_DSP_PM_D3,
417 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
420 static int imx8_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state)
422 const struct sof_dsp_power_state target_dsp_state = {
423 .state = target_state,
426 if (!pm_runtime_suspended(sdev->dev))
429 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
432 static int imx8_dsp_resume(struct snd_sof_dev *sdev)
435 const struct sof_dsp_power_state target_dsp_state = {
436 .state = SOF_DSP_PM_D0,
439 ret = imx8_resume(sdev);
443 if (pm_runtime_suspended(sdev->dev)) {
444 pm_runtime_disable(sdev->dev);
445 pm_runtime_set_active(sdev->dev);
446 pm_runtime_mark_last_busy(sdev->dev);
447 pm_runtime_enable(sdev->dev);
448 pm_runtime_idle(sdev->dev);
451 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
454 static struct snd_soc_dai_driver imx8_dai[] = {
479 static int imx8_dsp_set_power_state(struct snd_sof_dev *sdev,
480 const struct sof_dsp_power_state *target_state)
482 sdev->dsp_power_state = *target_state;
488 static struct snd_sof_dsp_ops sof_imx8_ops = {
489 /* probe and remove */
491 .remove = imx8_remove,
496 .block_read = sof_block_read,
497 .block_write = sof_block_write,
500 .mailbox_read = sof_mailbox_read,
501 .mailbox_write = sof_mailbox_write,
504 .send_msg = imx8_send_msg,
505 .get_mailbox_offset = imx8_get_mailbox_offset,
506 .get_window_offset = imx8_get_window_offset,
508 .ipc_msg_data = sof_ipc_msg_data,
509 .set_stream_data_offset = sof_set_stream_data_offset,
511 .get_bar_index = imx8_get_bar_index,
513 /* firmware loading */
514 .load_firmware = snd_sof_load_firmware_memcpy,
516 /* Debug information */
517 .dbg_dump = imx8_dump,
518 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
520 /* stream callbacks */
521 .pcm_open = sof_stream_pcm_open,
522 .pcm_close = sof_stream_pcm_close,
525 .dsp_arch_ops = &sof_xtensa_arch_ops,
529 .num_drv = ARRAY_SIZE(imx8_dai),
531 /* ALSA HW info flags */
532 .hw_info = SNDRV_PCM_INFO_MMAP |
533 SNDRV_PCM_INFO_MMAP_VALID |
534 SNDRV_PCM_INFO_INTERLEAVED |
535 SNDRV_PCM_INFO_PAUSE |
536 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
539 .runtime_suspend = imx8_dsp_runtime_suspend,
540 .runtime_resume = imx8_dsp_runtime_resume,
542 .suspend = imx8_dsp_suspend,
543 .resume = imx8_dsp_resume,
545 .set_power_state = imx8_dsp_set_power_state,
549 static struct snd_sof_dsp_ops sof_imx8x_ops = {
550 /* probe and remove */
552 .remove = imx8_remove,
557 .block_read = sof_block_read,
558 .block_write = sof_block_write,
561 .mailbox_read = sof_mailbox_read,
562 .mailbox_write = sof_mailbox_write,
565 .send_msg = imx8_send_msg,
566 .get_mailbox_offset = imx8_get_mailbox_offset,
567 .get_window_offset = imx8_get_window_offset,
569 .ipc_msg_data = sof_ipc_msg_data,
570 .set_stream_data_offset = sof_set_stream_data_offset,
572 .get_bar_index = imx8_get_bar_index,
574 /* firmware loading */
575 .load_firmware = snd_sof_load_firmware_memcpy,
577 /* Debug information */
578 .dbg_dump = imx8_dump,
579 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
581 /* stream callbacks */
582 .pcm_open = sof_stream_pcm_open,
583 .pcm_close = sof_stream_pcm_close,
586 .dsp_arch_ops = &sof_xtensa_arch_ops,
590 .num_drv = ARRAY_SIZE(imx8_dai),
593 .runtime_suspend = imx8_dsp_runtime_suspend,
594 .runtime_resume = imx8_dsp_runtime_resume,
596 .suspend = imx8_dsp_suspend,
597 .resume = imx8_dsp_resume,
599 .set_power_state = imx8_dsp_set_power_state,
601 /* ALSA HW info flags */
602 .hw_info = SNDRV_PCM_INFO_MMAP |
603 SNDRV_PCM_INFO_MMAP_VALID |
604 SNDRV_PCM_INFO_INTERLEAVED |
605 SNDRV_PCM_INFO_PAUSE |
606 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP
609 static struct sof_dev_desc sof_of_imx8qxp_desc = {
610 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
611 .ipc_default = SOF_IPC_TYPE_3,
613 [SOF_IPC_TYPE_3] = "imx/sof",
615 .default_tplg_path = {
616 [SOF_IPC_TYPE_3] = "imx/sof-tplg",
618 .default_fw_filename = {
619 [SOF_IPC_TYPE_3] = "sof-imx8x.ri",
621 .nocodec_tplg_filename = "sof-imx8-nocodec.tplg",
622 .ops = &sof_imx8x_ops,
625 static struct sof_dev_desc sof_of_imx8qm_desc = {
626 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
627 .ipc_default = SOF_IPC_TYPE_3,
629 [SOF_IPC_TYPE_3] = "imx/sof",
631 .default_tplg_path = {
632 [SOF_IPC_TYPE_3] = "imx/sof-tplg",
634 .default_fw_filename = {
635 [SOF_IPC_TYPE_3] = "sof-imx8.ri",
637 .nocodec_tplg_filename = "sof-imx8-nocodec.tplg",
638 .ops = &sof_imx8_ops,
641 static const struct of_device_id sof_of_imx8_ids[] = {
642 { .compatible = "fsl,imx8qxp-dsp", .data = &sof_of_imx8qxp_desc},
643 { .compatible = "fsl,imx8qm-dsp", .data = &sof_of_imx8qm_desc},
646 MODULE_DEVICE_TABLE(of, sof_of_imx8_ids);
648 /* DT driver definition */
649 static struct platform_driver snd_sof_of_imx8_driver = {
650 .probe = sof_of_probe,
651 .remove_new = sof_of_remove,
653 .name = "sof-audio-of-imx8",
655 .of_match_table = sof_of_imx8_ids,
658 module_platform_driver(snd_sof_of_imx8_driver);
660 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
661 MODULE_LICENSE("Dual BSD/GPL");