1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
12 * Hardware interface for generic AMD ACP processor
16 #include <linux/module.h>
17 #include <linux/pci.h>
21 #include "acp-dsp-offset.h"
23 #define SECURED_FIRMWARE 1
25 static bool enable_fw_debug;
26 module_param(enable_fw_debug, bool, 0444);
27 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug");
29 const struct dmi_system_id acp_sof_quirk_table[] = {
31 /* Valve Jupiter device */
33 DMI_MATCH(DMI_SYS_VENDOR, "Valve"),
34 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"),
35 DMI_MATCH(DMI_PRODUCT_FAMILY, "Sephiroth"),
37 .driver_data = (void *)SECURED_FIRMWARE,
41 EXPORT_SYMBOL_GPL(acp_sof_quirk_table);
43 static int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data)
45 pci_write_config_dword(dev, 0x60, smn_addr);
46 pci_write_config_dword(dev, 0x64, data);
51 static int smn_read(struct pci_dev *dev, u32 smn_addr)
55 pci_write_config_dword(dev, 0x60, smn_addr);
56 pci_read_config_dword(dev, 0x64, &data);
61 static void init_dma_descriptor(struct acp_dev_data *adata)
63 struct snd_sof_dev *sdev = adata->dev;
64 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
67 addr = desc->sram_pte_offset + sdev->debug_box.offset +
68 offsetof(struct scratch_reg_conf, dma_desc);
70 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr);
71 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT);
74 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx,
75 struct dma_descriptor *dscr_info)
77 struct snd_sof_dev *sdev = adata->dev;
80 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset +
81 offsetof(struct scratch_reg_conf, dma_desc) +
82 idx * sizeof(struct dma_descriptor);
84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr);
85 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr);
86 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all);
89 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
90 unsigned int idx, unsigned int dscr_count)
92 struct snd_sof_dev *sdev = adata->dev;
93 unsigned int val, status;
96 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32),
97 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN);
99 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val,
100 val & (1 << ch), ACP_REG_POLL_INTERVAL,
101 ACP_REG_POLL_TIMEOUT_US);
103 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS);
104 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));
106 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
110 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0);
111 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count);
112 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx);
113 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0);
114 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);
119 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch,
120 unsigned int dscr_count, struct dma_descriptor *dscr_info)
122 struct snd_sof_dev *sdev = adata->dev;
126 if (!dscr_info || !dscr_count)
129 for (dscr = 0; dscr < dscr_count; dscr++)
130 configure_dma_descriptor(adata, dscr, dscr_info++);
132 ret = config_dma_channel(adata, ch, 0, dscr_count);
134 dev_err(sdev->dev, "config dma ch failed:%d\n", ret);
139 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
140 unsigned int dest_addr, int dsp_data_size)
142 struct snd_sof_dev *sdev = adata->dev;
143 unsigned int desc_count, index;
146 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0;
147 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) {
148 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE;
149 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE;
150 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE;
151 if (dsp_data_size < ACP_PAGE_SIZE)
152 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size;
155 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info);
157 dev_err(sdev->dev, "acpbus_dma_start failed\n");
159 /* Clear descriptor array */
160 for (index = 0; index < desc_count; index++)
161 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor));
167 * psp_mbox_ready- function to poll ready bit of psp mbox
168 * @adata: acp device data
169 * @ack: bool variable to check ready bit status or psp ack
172 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack)
174 struct snd_sof_dev *sdev = adata->dev;
178 ret = read_poll_timeout(smn_read, data, data & MBOX_READY_MASK, MBOX_DELAY_US,
179 ACP_PSP_TIMEOUT_US, false, adata->smn_dev, MP0_C2PMSG_114_REG);
183 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK);
192 * psp_send_cmd - function to send psp command over mbox
193 * @adata: acp device data
194 * @cmd: non zero integer value for command type
197 static int psp_send_cmd(struct acp_dev_data *adata, int cmd)
199 struct snd_sof_dev *sdev = adata->dev;
206 /* Get a non-zero Doorbell value from PSP */
207 ret = read_poll_timeout(smn_read, data, data, MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false,
208 adata->smn_dev, MP0_C2PMSG_73_REG);
211 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG);
215 /* Check if PSP is ready for new command */
216 ret = psp_mbox_ready(adata, 0);
220 smn_write(adata->smn_dev, MP0_C2PMSG_114_REG, cmd);
222 /* Ring the Doorbell for PSP */
223 smn_write(adata->smn_dev, MP0_C2PMSG_73_REG, data);
225 /* Check MBOX ready as PSP ack */
226 ret = psp_mbox_ready(adata, 1);
231 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
232 unsigned int start_addr, unsigned int dest_addr,
233 unsigned int image_length)
235 struct snd_sof_dev *sdev = adata->dev;
236 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
237 unsigned int tx_count, fw_qualifier, val;
241 dev_err(sdev->dev, "SHA DMA image address is NULL\n");
245 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD);
246 if (val & ACP_SHA_RUN) {
247 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET);
248 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS,
249 val, val & ACP_SHA_RESET,
250 ACP_REG_POLL_INTERVAL,
251 ACP_REG_POLL_TIMEOUT_US);
253 dev_err(sdev->dev, "SHA DMA Failed to Reset\n");
258 if (adata->signed_fw_image)
259 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER);
261 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr);
262 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr);
263 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length);
264 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN);
266 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT,
267 tx_count, tx_count == image_length,
268 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
270 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count);
274 /* psp_send_cmd only required for renoir platform (rev - 3) */
275 if (desc->rev == 3) {
276 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND);
281 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER,
282 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE,
283 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
285 dev_err(sdev->dev, "PSP validation failed\n");
292 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch)
294 struct snd_sof_dev *sdev = adata->dev;
298 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32));
299 if (val & ACP_DMA_CH_RUN) {
300 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val,
301 ACP_REG_POLL_INTERVAL,
302 ACP_DMA_COMPLETE_TIMEOUT_US);
304 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch);
310 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes)
312 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
315 for (i = 0, j = 0; i < bytes; i = i + 4, j++)
316 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i);
319 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes)
321 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
324 for (i = 0, j = 0; i < bytes; i = i + 4, j++)
325 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);
328 static int acp_memory_init(struct snd_sof_dev *sdev)
330 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
331 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
333 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET,
334 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK);
335 init_dma_descriptor(adata);
340 static irqreturn_t acp_irq_thread(int irq, void *context)
342 struct snd_sof_dev *sdev = context;
343 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
344 unsigned int count = ACP_HW_SEM_RETRY_COUNT;
346 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) {
347 /* Wait until acquired HW Semaphore lock or timeout */
350 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
355 sof_ops(sdev)->irq_thread(irq, sdev);
356 /* Unlock or Release HW Semaphore */
357 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);
362 static irqreturn_t acp_irq_handler(int irq, void *dev_id)
364 struct snd_sof_dev *sdev = dev_id;
365 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
366 unsigned int base = desc->dsp_intr_base;
369 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
370 if (val & ACP_DSP_TO_HOST_IRQ) {
371 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET,
372 ACP_DSP_TO_HOST_IRQ);
373 return IRQ_WAKE_THREAD;
379 static int acp_power_on(struct snd_sof_dev *sdev)
381 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
382 unsigned int base = desc->pgfsm_base;
386 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET);
388 if (val == ACP_POWERED_ON)
391 if (val & ACP_PGFSM_STATUS_MASK)
392 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,
393 ACP_PGFSM_CNTL_POWER_ON_MASK);
395 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,
396 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
398 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n");
403 static int acp_reset(struct snd_sof_dev *sdev)
405 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
409 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET);
411 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,
412 val & ACP_SOFT_RESET_DONE_MASK,
413 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
415 dev_err(sdev->dev, "timeout asserting reset\n");
419 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET);
421 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,
422 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
424 dev_err(sdev->dev, "timeout in releasing reset\n");
426 if (desc->acp_clkmux_sel)
427 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK);
429 if (desc->ext_intr_enb)
430 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);
435 static int acp_init(struct snd_sof_dev *sdev)
440 ret = acp_power_on(sdev);
442 dev_err(sdev->dev, "ACP power on failed\n");
446 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01);
448 return acp_reset(sdev);
451 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
455 ret = acp_reset(sdev);
457 dev_err(sdev->dev, "ACP Reset failed\n");
461 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00);
465 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, SND_SOC_SOF_AMD_COMMON);
467 int amd_sof_acp_resume(struct snd_sof_dev *sdev)
471 ret = acp_init(sdev);
473 dev_err(sdev->dev, "ACP Init failed\n");
476 return acp_memory_init(sdev);
478 EXPORT_SYMBOL_NS(amd_sof_acp_resume, SND_SOC_SOF_AMD_COMMON);
480 int amd_sof_acp_probe(struct snd_sof_dev *sdev)
482 struct pci_dev *pci = to_pci_dev(sdev->dev);
483 struct snd_sof_pdata *plat_data = sdev->pdata;
484 struct acp_dev_data *adata;
485 const struct sof_amd_acp_desc *chip;
486 const struct dmi_system_id *dmi_id;
490 chip = get_chip_info(sdev->pdata);
492 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device);
495 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data),
501 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
502 PLATFORM_DEVID_NONE, NULL, 0);
503 if (IS_ERR(adata->dmic_dev)) {
504 dev_err(sdev->dev, "failed to register platform for dmic codec\n");
505 return PTR_ERR(adata->dmic_dev);
507 addr = pci_resource_start(pci, ACP_DSP_BAR);
508 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR));
509 if (!sdev->bar[ACP_DSP_BAR]) {
510 dev_err(sdev->dev, "ioremap error\n");
517 sdev->pdata->hw_pdata = adata;
518 adata->smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, chip->host_bridge_id, NULL);
519 if (!adata->smn_dev) {
520 dev_err(sdev->dev, "Failed to get host bridge device\n");
525 sdev->ipc_irq = pci->irq;
526 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread,
527 IRQF_SHARED, "AudioDSP", sdev);
529 dev_err(sdev->dev, "failed to register IRQ %d\n",
534 ret = acp_init(sdev);
538 sdev->dsp_box.offset = 0;
539 sdev->dsp_box.size = BOX_SIZE_512;
541 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size;
542 sdev->host_box.size = BOX_SIZE_512;
544 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size;
545 sdev->debug_box.size = BOX_SIZE_1024;
547 adata->signed_fw_image = false;
548 dmi_id = dmi_first_match(acp_sof_quirk_table);
549 if (dmi_id && dmi_id->driver_data) {
550 adata->fw_code_bin = kasprintf(GFP_KERNEL, "%s/sof-%s-code.bin",
551 plat_data->fw_filename_prefix,
553 adata->fw_data_bin = kasprintf(GFP_KERNEL, "%s/sof-%s-data.bin",
554 plat_data->fw_filename_prefix,
556 adata->signed_fw_image = dmi_id->driver_data;
558 dev_dbg(sdev->dev, "fw_code_bin:%s, fw_data_bin:%s\n", adata->fw_code_bin,
561 adata->enable_fw_debug = enable_fw_debug;
562 acp_memory_init(sdev);
564 acp_dsp_stream_init(sdev);
569 free_irq(sdev->ipc_irq, sdev);
571 pci_dev_put(adata->smn_dev);
573 platform_device_unregister(adata->dmic_dev);
576 EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COMMON);
578 void amd_sof_acp_remove(struct snd_sof_dev *sdev)
580 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
583 pci_dev_put(adata->smn_dev);
586 free_irq(sdev->ipc_irq, sdev);
589 platform_device_unregister(adata->dmic_dev);
593 EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON);
595 MODULE_DESCRIPTION("AMD ACP sof driver");
596 MODULE_LICENSE("Dual BSD/GPL");