1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
5 // Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 #include <linux/clk-provider.h>
7 #include <linux/clkdev.h>
22 #define BRRx_MASK(x) (0x3FF & x)
24 static struct rsnd_mod_ops adg_ops = {
33 struct clk *clkin[CLKINMAX];
34 struct clk *clkout[CLKOUTMAX];
36 struct clk_onecell_data onecell;
38 int clkin_rate[CLKINMAX];
45 int brg_rate[ADG_HZ_SIZE]; /* BRGA / BRGB */
48 #define for_each_rsnd_clkin(pos, adg, i) \
50 (i < adg->clkin_size) && \
51 ((pos) = adg->clkin[i]); \
53 #define for_each_rsnd_clkout(pos, adg, i) \
55 (i < adg->clkout_size) && \
56 ((pos) = adg->clkout[i]); \
58 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
60 static const char * const clkin_name_gen4[] = {
64 static const char * const clkin_name_gen2[] = {
71 static const char * const clkout_name_gen2[] = {
72 [CLKOUT] = "audio_clkout",
73 [CLKOUT1] = "audio_clkout1",
74 [CLKOUT2] = "audio_clkout2",
75 [CLKOUT3] = "audio_clkout3",
78 static u32 rsnd_adg_calculate_brgx(unsigned long div)
85 for (i = 3; i >= 0; i--) {
86 int ratio = 2 << (i * 2);
87 if (0 == (div % ratio))
88 return (u32)((i << 8) | ((div / ratio) - 1));
94 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
96 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
97 int id = rsnd_mod_id(ssi_mod);
100 if (rsnd_ssi_is_pin_sharing(io)) {
116 return (0x6 + ws) << 8;
119 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
120 struct rsnd_dai_stream *io,
121 unsigned int target_rate,
122 unsigned int *target_val,
123 unsigned int *target_en)
125 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
126 struct device *dev = rsnd_priv_to_dev(priv);
128 unsigned int val, en;
129 unsigned int min, diff;
130 unsigned int sel_rate[] = {
131 adg->clkin_rate[CLKA], /* 0000: CLKA */
132 adg->clkin_rate[CLKB], /* 0001: CLKB */
133 adg->clkin_rate[CLKC], /* 0010: CLKC */
134 adg->brg_rate[ADG_HZ_441], /* 0011: BRGA */
135 adg->brg_rate[ADG_HZ_48], /* 0100: BRGB */
141 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
149 for (div = 2; div <= 98304; div += step) {
150 diff = abs(target_rate - sel_rate[sel] / div);
152 val = (sel << 8) | idx;
154 en = 1 << (sel + 1); /* fixme */
158 * step of 0_0000 / 0_0001 / 0_1101
161 if ((idx > 2) && (idx % 2))
172 dev_err(dev, "no Input clock\n");
181 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
182 struct rsnd_dai_stream *io,
183 unsigned int in_rate,
184 unsigned int out_rate,
185 u32 *in, u32 *out, u32 *en)
187 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
188 unsigned int target_rate;
194 /* default = SSI WS */
196 _out = rsnd_adg_ssi_ws_timing_gen2(io);
201 if (runtime->rate != in_rate) {
202 target_rate = out_rate;
204 } else if (runtime->rate != out_rate) {
205 target_rate = in_rate;
210 __rsnd_adg_get_timesel_ratio(priv, io,
222 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
223 struct rsnd_dai_stream *io)
225 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
226 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
227 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
228 int id = rsnd_mod_id(cmd_mod);
229 int shift = (id % 2) ? 16 : 0;
232 rsnd_adg_get_timesel_ratio(priv, io,
233 rsnd_src_get_in_rate(priv, io),
234 rsnd_src_get_out_rate(priv, io),
238 mask = 0x0f1f << shift;
240 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
245 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
246 struct rsnd_dai_stream *io,
247 unsigned int in_rate,
248 unsigned int out_rate)
250 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
251 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
252 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
255 int id = rsnd_mod_id(src_mod);
256 int shift = (id % 2) ? 16 : 0;
258 rsnd_mod_confirm_src(src_mod);
260 rsnd_adg_get_timesel_ratio(priv, io,
266 mask = 0x0f1f << shift;
268 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in);
269 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
272 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
277 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
279 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
280 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
281 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
282 struct device *dev = rsnd_priv_to_dev(priv);
283 int id = rsnd_mod_id(ssi_mod);
284 int shift = (id % 4) * 8;
285 u32 mask = 0xFF << shift;
287 rsnd_mod_confirm_ssi(ssi_mod);
292 * SSI 8 is not connected to ADG.
293 * it works with SSI 7
298 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
300 dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
303 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
305 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
316 * find suitable clock from
317 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
319 for_each_rsnd_clkin(clk, adg, i)
320 if (rate == adg->clkin_rate[i])
324 * find divided clock from BRGA/BRGB
326 if (rate == adg->brg_rate[ADG_HZ_441])
329 if (rate == adg->brg_rate[ADG_HZ_48])
335 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
337 rsnd_adg_set_ssi_clk(ssi_mod, 0);
342 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
344 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
345 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
346 struct device *dev = rsnd_priv_to_dev(priv);
347 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
351 data = rsnd_adg_clk_query(priv, rate);
355 rsnd_adg_set_ssi_clk(ssi_mod, data);
357 if (0 == (rate % 8000))
358 ckr = 0x80000000; /* BRGB output = 48kHz */
360 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
362 dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
364 (ckr) ? adg->brg_rate[ADG_HZ_48] :
365 adg->brg_rate[ADG_HZ_441]);
370 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
372 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
373 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
378 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr);
379 rsnd_mod_write(adg_mod, BRRA, adg->brga);
380 rsnd_mod_write(adg_mod, BRRB, adg->brgb);
383 for_each_rsnd_clkin(clk, adg, i) {
385 clk_prepare_enable(clk);
388 * We shouldn't use clk_get_rate() under
389 * atomic context. Let's keep it when
390 * rsnd_adg_clk_enable() was called
392 adg->clkin_rate[i] = clk_get_rate(clk);
394 clk_disable_unprepare(clk);
399 static struct clk *rsnd_adg_create_null_clk(struct rsnd_priv *priv,
400 const char * const name,
403 struct device *dev = rsnd_priv_to_dev(priv);
406 clk = clk_register_fixed_rate(dev, name, parent, 0, 0);
407 if (IS_ERR_OR_NULL(clk)) {
408 dev_err(dev, "create null clk error\n");
409 return ERR_CAST(clk);
415 static struct clk *rsnd_adg_null_clk_get(struct rsnd_priv *priv)
417 struct rsnd_adg *adg = priv->adg;
419 if (!adg->null_clk) {
420 static const char * const name = "rsnd_adg_null";
422 adg->null_clk = rsnd_adg_create_null_clk(priv, name, NULL);
425 return adg->null_clk;
428 static void rsnd_adg_null_clk_clean(struct rsnd_priv *priv)
430 struct rsnd_adg *adg = priv->adg;
433 clk_unregister_fixed_rate(adg->null_clk);
436 static int rsnd_adg_get_clkin(struct rsnd_priv *priv)
438 struct rsnd_adg *adg = priv->adg;
439 struct device *dev = rsnd_priv_to_dev(priv);
441 const char * const *clkin_name;
445 clkin_name = clkin_name_gen2;
446 clkin_size = ARRAY_SIZE(clkin_name_gen2);
447 if (rsnd_is_gen4(priv)) {
448 clkin_name = clkin_name_gen4;
449 clkin_size = ARRAY_SIZE(clkin_name_gen4);
452 for (i = 0; i < clkin_size; i++) {
453 clk = devm_clk_get(dev, clkin_name[i]);
455 if (IS_ERR_OR_NULL(clk))
456 clk = rsnd_adg_null_clk_get(priv);
457 if (IS_ERR_OR_NULL(clk))
463 adg->clkin_size = clkin_size;
468 dev_err(dev, "adg clock IN get failed\n");
470 rsnd_adg_null_clk_clean(priv);
475 static void rsnd_adg_unregister_clkout(struct rsnd_priv *priv)
477 struct rsnd_adg *adg = priv->adg;
481 for_each_rsnd_clkout(clk, adg, i)
482 clk_unregister_fixed_rate(clk);
485 static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
487 struct rsnd_adg *adg = priv->adg;
489 struct device *dev = rsnd_priv_to_dev(priv);
490 struct device_node *np = dev->of_node;
491 struct property *prop;
492 u32 ckr, brgx, brga, brgb;
493 u32 req_rate[ADG_HZ_SIZE] = {};
495 unsigned long req_Hz[ADG_HZ_SIZE];
499 const char *parent_clk_name = NULL;
500 const char * const *clkout_name;
509 brga = 0xff; /* default */
510 brgb = 0xff; /* default */
513 * ADG supports BRRA/BRRB output only
514 * this means all clkout0/1/2/3 will be same rate
516 prop = of_find_property(np, "clock-frequency", NULL);
518 goto rsnd_adg_get_clkout_end;
520 req_size = prop->length / sizeof(u32);
521 if (req_size > ADG_HZ_SIZE) {
522 dev_err(dev, "too many clock-frequency\n");
526 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
527 req_Hz[ADG_HZ_48] = 0;
528 req_Hz[ADG_HZ_441] = 0;
529 for (i = 0; i < req_size; i++) {
530 if (0 == (req_rate[i] % 44100))
531 req_Hz[ADG_HZ_441] = req_rate[i];
532 if (0 == (req_rate[i] % 48000))
533 req_Hz[ADG_HZ_48] = req_rate[i];
537 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
538 * have 44.1kHz or 48kHz base clocks for now.
540 * SSI itself can divide parent clock by 1/1 - 1/16
542 * rsnd_adg_ssi_clk_try_start()
543 * rsnd_ssi_master_clk_start()
549 * clk_i (internal clock) can't create accurate rate, it will be approximate rate.
553 * clk_i needs x2 of required maximum rate.
555 * - Minimum division of BRRA/BRRB
556 * - rsnd_ssi_clk_query()
558 * Sample Settings for TDM 8ch, 32bit width
560 * 8(ch) x 32(bit) x 44100(Hz) x 2<Note> = 22579200
561 * 8(ch) x 32(bit) x 48000(Hz) x 2<Note> = 24576000
563 * clock-frequency = <22579200 24576000>;
565 for_each_rsnd_clkin(clk, adg, i) {
568 rate = clk_get_rate(clk);
570 if (0 == rate) /* not used */
576 /* see [APPROXIMATE] */
577 rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_441]) * req_Hz[ADG_HZ_441];
578 if (!adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441] && (0 == rate % 44100)) {
579 div = rate / req_Hz[ADG_HZ_441];
580 brgx = rsnd_adg_calculate_brgx(div);
581 if (BRRx_MASK(brgx) == brgx) {
583 adg->brg_rate[ADG_HZ_441] = rate / div;
584 ckr |= brg_table[i] << 20;
585 if (req_Hz[ADG_HZ_441])
586 parent_clk_name = __clk_get_name(clk);
595 /* see [APPROXIMATE] */
596 rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_48]) * req_Hz[ADG_HZ_48];
597 if (!adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48] && (0 == rate % 48000)) {
598 div = rate / req_Hz[ADG_HZ_48];
599 brgx = rsnd_adg_calculate_brgx(div);
600 if (BRRx_MASK(brgx) == brgx) {
602 adg->brg_rate[ADG_HZ_48] = rate / div;
603 ckr |= brg_table[i] << 16;
604 if (req_Hz[ADG_HZ_48])
605 parent_clk_name = __clk_get_name(clk);
612 if (!(adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48]) &&
613 !(adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441]))
614 goto rsnd_adg_get_clkout_end;
617 dev_info(dev, "It uses CLK_I as approximate rate");
619 clkout_name = clkout_name_gen2;
620 clkout_size = ARRAY_SIZE(clkout_name_gen2);
621 if (rsnd_is_gen4(priv))
622 clkout_size = 1; /* reuse clkout_name_gen2[] */
625 * ADG supports BRRA/BRRB output only.
626 * this means all clkout0/1/2/3 will be * same rate
629 of_property_read_u32(np, "#clock-cells", &count);
634 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
635 parent_clk_name, 0, req_rate[0]);
636 if (IS_ERR_OR_NULL(clk))
639 adg->clkout[CLKOUT] = clk;
640 adg->clkout_size = 1;
641 of_clk_add_provider(np, of_clk_src_simple_get, clk);
647 for (i = 0; i < clkout_size; i++) {
648 clk = clk_register_fixed_rate(dev, clkout_name[i],
651 if (IS_ERR_OR_NULL(clk))
654 adg->clkout[i] = clk;
656 adg->onecell.clks = adg->clkout;
657 adg->onecell.clk_num = clkout_size;
658 adg->clkout_size = clkout_size;
659 of_clk_add_provider(np, of_clk_src_onecell_get,
663 rsnd_adg_get_clkout_end:
671 dev_err(dev, "adg clock OUT get failed\n");
673 rsnd_adg_unregister_clkout(priv);
678 #if defined(DEBUG) || defined(CONFIG_DEBUG_FS)
680 static void dbg_msg(struct device *dev, struct seq_file *m,
681 const char *fmt, ...)
687 vsnprintf(msg, sizeof(msg), fmt, args);
693 dev_dbg(dev, "%s", msg);
696 void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m)
698 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
699 struct device *dev = rsnd_priv_to_dev(priv);
703 for_each_rsnd_clkin(clk, adg, i)
704 dbg_msg(dev, m, "%-18s : %pa : %ld\n",
705 __clk_get_name(clk), clk, clk_get_rate(clk));
707 dbg_msg(dev, m, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
708 adg->ckr, adg->brga, adg->brgb);
709 dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->brg_rate[ADG_HZ_441]);
710 dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->brg_rate[ADG_HZ_48]);
713 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
714 * by BRGCKR::BRGCKR_31
716 for_each_rsnd_clkout(clk, adg, i)
717 dbg_msg(dev, m, "%-18s : %pa : %ld\n",
718 __clk_get_name(clk), clk, clk_get_rate(clk));
721 #define rsnd_adg_clk_dbg_info(priv, m)
724 int rsnd_adg_probe(struct rsnd_priv *priv)
726 struct rsnd_adg *adg;
727 struct device *dev = rsnd_priv_to_dev(priv);
730 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
734 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
741 ret = rsnd_adg_get_clkin(priv);
745 ret = rsnd_adg_get_clkout(priv);
749 rsnd_adg_clk_enable(priv);
750 rsnd_adg_clk_dbg_info(priv, NULL);
755 void rsnd_adg_remove(struct rsnd_priv *priv)
757 struct device *dev = rsnd_priv_to_dev(priv);
758 struct device_node *np = dev->of_node;
760 rsnd_adg_unregister_clkout(priv);
762 of_clk_del_provider(np);
764 rsnd_adg_clk_disable(priv);
766 /* It should be called after rsnd_adg_clk_disable() */
767 rsnd_adg_null_clk_clean(priv);