1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
5 // Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 #include <linux/clk-provider.h>
22 #define BRRx_MASK(x) (0x3FF & x)
24 static struct rsnd_mod_ops adg_ops = {
29 struct clk *clk[CLKMAX];
30 struct clk *clkout[CLKOUTMAX];
31 struct clk_onecell_data onecell;
39 int rbga_rate_for_441khz; /* RBGA */
40 int rbgb_rate_for_48khz; /* RBGB */
43 #define LRCLK_ASYNC (1 << 0)
44 #define AUDIO_OUT_48 (1 << 1)
46 #define for_each_rsnd_clk(pos, adg, i) \
49 ((pos) = adg->clk[i]); \
51 #define for_each_rsnd_clkout(pos, adg, i) \
54 ((pos) = adg->clkout[i]); \
56 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
58 static const char * const clk_name[] = {
65 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
72 for (i = 3; i >= 0; i--) {
74 if (0 == (div % ratio))
75 return (u32)((i << 8) | ((div / ratio) - 1));
81 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
83 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
84 int id = rsnd_mod_id(ssi_mod);
87 if (rsnd_ssi_is_pin_sharing(io)) {
102 return (0x6 + ws) << 8;
105 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
106 struct rsnd_dai_stream *io,
107 unsigned int target_rate,
108 unsigned int *target_val,
109 unsigned int *target_en)
111 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
112 struct device *dev = rsnd_priv_to_dev(priv);
113 int idx, sel, div, step;
114 unsigned int val, en;
115 unsigned int min, diff;
116 unsigned int sel_rate[] = {
117 adg->clk_rate[CLKA], /* 0000: CLKA */
118 adg->clk_rate[CLKB], /* 0001: CLKB */
119 adg->clk_rate[CLKC], /* 0010: CLKC */
120 adg->rbga_rate_for_441khz, /* 0011: RBGA */
121 adg->rbgb_rate_for_48khz, /* 0100: RBGB */
127 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
134 for (div = 2; div <= 98304; div += step) {
135 diff = abs(target_rate - sel_rate[sel] / div);
137 val = (sel << 8) | idx;
139 en = 1 << (sel + 1); /* fixme */
143 * step of 0_0000 / 0_0001 / 0_1101
146 if ((idx > 2) && (idx % 2))
157 dev_err(dev, "no Input clock\n");
166 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
167 struct rsnd_dai_stream *io,
168 unsigned int in_rate,
169 unsigned int out_rate,
170 u32 *in, u32 *out, u32 *en)
172 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
173 unsigned int target_rate;
179 /* default = SSI WS */
181 _out = rsnd_adg_ssi_ws_timing_gen2(io);
186 if (runtime->rate != in_rate) {
187 target_rate = out_rate;
189 } else if (runtime->rate != out_rate) {
190 target_rate = in_rate;
195 __rsnd_adg_get_timesel_ratio(priv, io,
207 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
208 struct rsnd_dai_stream *io)
210 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
211 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
212 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
213 int id = rsnd_mod_id(cmd_mod);
214 int shift = (id % 2) ? 16 : 0;
217 rsnd_adg_get_timesel_ratio(priv, io,
218 rsnd_src_get_in_rate(priv, io),
219 rsnd_src_get_out_rate(priv, io),
223 mask = 0x0f1f << shift;
225 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
230 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
231 struct rsnd_dai_stream *io,
232 unsigned int in_rate,
233 unsigned int out_rate)
235 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
236 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
237 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
240 int id = rsnd_mod_id(src_mod);
241 int shift = (id % 2) ? 16 : 0;
243 rsnd_mod_confirm_src(src_mod);
245 rsnd_adg_get_timesel_ratio(priv, io,
251 mask = 0x0f1f << shift;
255 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in);
256 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
259 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in);
260 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
263 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in);
264 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
267 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in);
268 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
271 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in);
272 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
277 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
282 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
284 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
285 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
286 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
287 struct device *dev = rsnd_priv_to_dev(priv);
288 int id = rsnd_mod_id(ssi_mod);
289 int shift = (id % 4) * 8;
290 u32 mask = 0xFF << shift;
292 rsnd_mod_confirm_ssi(ssi_mod);
297 * SSI 8 is not connected to ADG.
298 * it works with SSI 7
305 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
308 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
311 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
315 dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
318 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
320 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
330 * find suitable clock from
331 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
333 for (i = 0; i < CLKMAX; i++)
334 if (rate == adg->clk_rate[i])
338 * find divided clock from BRGA/BRGB
340 if (rate == adg->rbga_rate_for_441khz)
343 if (rate == adg->rbgb_rate_for_48khz)
349 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
351 rsnd_adg_set_ssi_clk(ssi_mod, 0);
356 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
358 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
359 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
360 struct device *dev = rsnd_priv_to_dev(priv);
361 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
365 data = rsnd_adg_clk_query(priv, rate);
369 rsnd_adg_set_ssi_clk(ssi_mod, data);
371 if (rsnd_flags_has(adg, LRCLK_ASYNC)) {
372 if (rsnd_flags_has(adg, AUDIO_OUT_48))
375 if (0 == (rate % 8000))
379 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
380 rsnd_mod_write(adg_mod, BRRA, adg->rbga);
381 rsnd_mod_write(adg_mod, BRRB, adg->rbgb);
383 dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
385 (ckr) ? adg->rbgb_rate_for_48khz :
386 adg->rbga_rate_for_441khz);
391 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
393 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
394 struct device *dev = rsnd_priv_to_dev(priv);
398 for_each_rsnd_clk(clk, adg, i) {
401 ret = clk_prepare_enable(clk);
404 * We shouldn't use clk_get_rate() under
405 * atomic context. Let's keep it when
406 * rsnd_adg_clk_enable() was called
408 adg->clk_rate[i] = clk_get_rate(adg->clk[i]);
410 clk_disable_unprepare(clk);
414 dev_warn(dev, "can't use clk %d\n", i);
418 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
419 struct rsnd_adg *adg)
421 struct device *dev = rsnd_priv_to_dev(priv);
425 for (i = 0; i < CLKMAX; i++) {
426 clk = devm_clk_get(dev, clk_name[i]);
427 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
431 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
432 struct rsnd_adg *adg)
435 struct device *dev = rsnd_priv_to_dev(priv);
436 struct device_node *np = dev->of_node;
437 struct property *prop;
438 u32 ckr, rbgx, rbga, rbgb;
441 u32 req_rate[REQ_SIZE] = {};
443 unsigned long req_48kHz_rate, req_441kHz_rate;
445 const char *parent_clk_name = NULL;
446 static const char * const clkout_name[] = {
447 [CLKOUT] = "audio_clkout",
448 [CLKOUT1] = "audio_clkout1",
449 [CLKOUT2] = "audio_clkout2",
450 [CLKOUT3] = "audio_clkout3",
460 rbga = 2; /* default 1/6 */
461 rbgb = 2; /* default 1/6 */
464 * ADG supports BRRA/BRRB output only
465 * this means all clkout0/1/2/3 will be same rate
467 prop = of_find_property(np, "clock-frequency", NULL);
469 goto rsnd_adg_get_clkout_end;
471 req_size = prop->length / sizeof(u32);
472 if (req_size > REQ_SIZE) {
474 "too many clock-frequency, use top %d\n", REQ_SIZE);
478 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
481 for (i = 0; i < req_size; i++) {
482 if (0 == (req_rate[i] % 44100))
483 req_441kHz_rate = req_rate[i];
484 if (0 == (req_rate[i] % 48000))
485 req_48kHz_rate = req_rate[i];
488 if (req_rate[0] % 48000 == 0)
489 rsnd_flags_set(adg, AUDIO_OUT_48);
491 if (of_get_property(np, "clkout-lr-asynchronous", NULL))
492 rsnd_flags_set(adg, LRCLK_ASYNC);
495 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
496 * have 44.1kHz or 48kHz base clocks for now.
498 * SSI itself can divide parent clock by 1/1 - 1/16
500 * rsnd_adg_ssi_clk_try_start()
501 * rsnd_ssi_master_clk_start()
503 adg->rbga_rate_for_441khz = 0;
504 adg->rbgb_rate_for_48khz = 0;
505 for_each_rsnd_clk(clk, adg, i) {
506 rate = clk_get_rate(clk);
508 if (0 == rate) /* not used */
512 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
515 div = rate / req_441kHz_rate;
516 rbgx = rsnd_adg_calculate_rbgx(div);
517 if (BRRx_MASK(rbgx) == rbgx) {
519 adg->rbga_rate_for_441khz = rate / div;
520 ckr |= brg_table[i] << 20;
521 if (req_441kHz_rate &&
522 !rsnd_flags_has(adg, AUDIO_OUT_48))
523 parent_clk_name = __clk_get_name(clk);
528 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
531 div = rate / req_48kHz_rate;
532 rbgx = rsnd_adg_calculate_rbgx(div);
533 if (BRRx_MASK(rbgx) == rbgx) {
535 adg->rbgb_rate_for_48khz = rate / div;
536 ckr |= brg_table[i] << 16;
537 if (req_48kHz_rate &&
538 rsnd_flags_has(adg, AUDIO_OUT_48))
539 parent_clk_name = __clk_get_name(clk);
545 * ADG supports BRRA/BRRB output only.
546 * this means all clkout0/1/2/3 will be * same rate
549 of_property_read_u32(np, "#clock-cells", &count);
554 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
555 parent_clk_name, 0, req_rate[0]);
557 adg->clkout[CLKOUT] = clk;
558 of_clk_add_provider(np, of_clk_src_simple_get, clk);
565 for (i = 0; i < CLKOUTMAX; i++) {
566 clk = clk_register_fixed_rate(dev, clkout_name[i],
570 adg->clkout[i] = clk;
572 adg->onecell.clks = adg->clkout;
573 adg->onecell.clk_num = CLKOUTMAX;
574 of_clk_add_provider(np, of_clk_src_onecell_get,
578 rsnd_adg_get_clkout_end:
585 static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg)
587 struct device *dev = rsnd_priv_to_dev(priv);
591 for_each_rsnd_clk(clk, adg, i)
592 dev_dbg(dev, "%s : %p : %ld\n",
593 clk_name[i], clk, clk_get_rate(clk));
595 dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
596 adg->ckr, adg->rbga, adg->rbgb);
597 dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz);
598 dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz);
601 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
602 * by BRGCKR::BRGCKR_31
604 for_each_rsnd_clkout(clk, adg, i)
605 dev_dbg(dev, "clkout %d : %p : %ld\n", i,
606 clk, clk_get_rate(clk));
609 #define rsnd_adg_clk_dbg_info(priv, adg)
612 int rsnd_adg_probe(struct rsnd_priv *priv)
614 struct rsnd_adg *adg;
615 struct device *dev = rsnd_priv_to_dev(priv);
618 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
622 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
627 rsnd_adg_get_clkin(priv, adg);
628 rsnd_adg_get_clkout(priv, adg);
629 rsnd_adg_clk_dbg_info(priv, adg);
633 rsnd_adg_clk_enable(priv);
638 void rsnd_adg_remove(struct rsnd_priv *priv)
640 struct device *dev = rsnd_priv_to_dev(priv);
641 struct device_node *np = dev->of_node;
642 struct rsnd_adg *adg = priv->adg;
646 for_each_rsnd_clkout(clk, adg, i)
648 clk_unregister_fixed_rate(adg->clkout[i]);
650 of_clk_del_provider(np);
652 rsnd_adg_clk_disable(priv);