sound/soc/sh/rcar/adg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Helper routines for R-Car sound ADG.
   4 //
   5 //  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6
   7 #include <linux/clk-provider.h>
   8 #include "rsnd.h"
   9
  10 #define CLKA    0
  11 #define CLKB    1
  12 #define CLKC    2
  13 #define CLKI    3
  14 #define CLKMAX  4
  15
  16 #define CLKOUT  0
  17 #define CLKOUT1 1
  18 #define CLKOUT2 2
  19 #define CLKOUT3 3
  20 #define CLKOUTMAX 4
  21
  22 #define BRRx_MASK(x) (0x3FF & x)
  23
  24 static struct rsnd_mod_ops adg_ops = {
  25         .name = "adg",
  26 };
  27
  28 struct rsnd_adg {
  29         struct clk *clk[CLKMAX];
  30         struct clk *clkout[CLKOUTMAX];
  31         struct clk_onecell_data onecell;
  32         struct rsnd_mod mod;
  33         int clk_rate[CLKMAX];
  34         u32 flags;
  35         u32 ckr;
  36         u32 rbga;
  37         u32 rbgb;
  38
  39         int rbga_rate_for_441khz; /* RBGA */
  40         int rbgb_rate_for_48khz;  /* RBGB */
  41 };
  42
  43 #define LRCLK_ASYNC     (1 << 0)
  44 #define AUDIO_OUT_48    (1 << 1)
  45
  46 #define for_each_rsnd_clk(pos, adg, i)          \
  47         for (i = 0;                             \
  48              (i < CLKMAX) &&                    \
  49              ((pos) = adg->clk[i]);             \
  50              i++)
  51 #define for_each_rsnd_clkout(pos, adg, i)       \
  52         for (i = 0;                             \
  53              (i < CLKOUTMAX) &&                 \
  54              ((pos) = adg->clkout[i]);  \
  55              i++)
  56 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  57
  58 static const char * const clk_name[] = {
  59         [CLKA]  = "clk_a",
  60         [CLKB]  = "clk_b",
  61         [CLKC]  = "clk_c",
  62         [CLKI]  = "clk_i",
  63 };
  64
  65 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
  66 {
  67         int i, ratio;
  68
  69         if (!div)
  70                 return 0;
  71
  72         for (i = 3; i >= 0; i--) {
  73                 ratio = 2 << (i * 2);
  74                 if (0 == (div % ratio))
  75                         return (u32)((i << 8) | ((div / ratio) - 1));
  76         }
  77
  78         return ~0;
  79 }
  80
  81 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
  82 {
  83         struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
  84         int id = rsnd_mod_id(ssi_mod);
  85         int ws = id;
  86
  87         if (rsnd_ssi_is_pin_sharing(io)) {
  88                 switch (id) {
  89                 case 1:
  90                 case 2:
  91                         ws = 0;
  92                         break;
  93                 case 4:
  94                         ws = 3;
  95                         break;
  96                 case 8:
  97                         ws = 7;
  98                         break;
  99                 }
 100         }
 101
 102         return (0x6 + ws) << 8;
 103 }
 104
 105 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
 106                                        struct rsnd_dai_stream *io,
 107                                        unsigned int target_rate,
 108                                        unsigned int *target_val,
 109                                        unsigned int *target_en)
 110 {
 111         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 112         struct device *dev = rsnd_priv_to_dev(priv);
 113         int idx, sel, div, step;
 114         unsigned int val, en;
 115         unsigned int min, diff;
 116         unsigned int sel_rate[] = {
 117                 adg->clk_rate[CLKA],    /* 0000: CLKA */
 118                 adg->clk_rate[CLKB],    /* 0001: CLKB */
 119                 adg->clk_rate[CLKC],    /* 0010: CLKC */
 120                 adg->rbga_rate_for_441khz,      /* 0011: RBGA */
 121                 adg->rbgb_rate_for_48khz,       /* 0100: RBGB */
 122         };
 123
 124         min = ~0;
 125         val = 0;
 126         en = 0;
 127         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 128                 idx = 0;
 129                 step = 2;
 130
 131                 if (!sel_rate[sel])
 132                         continue;
 133
 134                 for (div = 2; div <= 98304; div += step) {
 135                         diff = abs(target_rate - sel_rate[sel] / div);
 136                         if (min > diff) {
 137                                 val = (sel << 8) | idx;
 138                                 min = diff;
 139                                 en = 1 << (sel + 1); /* fixme */
 140                         }
 141
 142                         /*
 143                          * step of 0_0000 / 0_0001 / 0_1101
 144                          * are out of order
 145                          */
 146                         if ((idx > 2) && (idx % 2))
 147                                 step *= 2;
 148                         if (idx == 0x1c) {
 149                                 div += step;
 150                                 step *= 2;
 151                         }
 152                         idx++;
 153                 }
 154         }
 155
 156         if (min == ~0) {
 157                 dev_err(dev, "no Input clock\n");
 158                 return;
 159         }
 160
 161         *target_val = val;
 162         if (target_en)
 163                 *target_en = en;
 164 }
 165
 166 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
 167                                        struct rsnd_dai_stream *io,
 168                                        unsigned int in_rate,
 169                                        unsigned int out_rate,
 170                                        u32 *in, u32 *out, u32 *en)
 171 {
 172         struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
 173         unsigned int target_rate;
 174         u32 *target_val;
 175         u32 _in;
 176         u32 _out;
 177         u32 _en;
 178
 179         /* default = SSI WS */
 180         _in =
 181         _out = rsnd_adg_ssi_ws_timing_gen2(io);
 182
 183         target_rate = 0;
 184         target_val = NULL;
 185         _en = 0;
 186         if (runtime->rate != in_rate) {
 187                 target_rate = out_rate;
 188                 target_val  = &_out;
 189         } else if (runtime->rate != out_rate) {
 190                 target_rate = in_rate;
 191                 target_val  = &_in;
 192         }
 193
 194         if (target_rate)
 195                 __rsnd_adg_get_timesel_ratio(priv, io,
 196                                              target_rate,
 197                                              target_val, &_en);
 198
 199         if (in)
 200                 *in = _in;
 201         if (out)
 202                 *out = _out;
 203         if (en)
 204                 *en = _en;
 205 }
 206
 207 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
 208                                  struct rsnd_dai_stream *io)
 209 {
 210         struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
 211         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 212         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 213         int id = rsnd_mod_id(cmd_mod);
 214         int shift = (id % 2) ? 16 : 0;
 215         u32 mask, val;
 216
 217         rsnd_adg_get_timesel_ratio(priv, io,
 218                                    rsnd_src_get_in_rate(priv, io),
 219                                    rsnd_src_get_out_rate(priv, io),
 220                                    NULL, &val, NULL);
 221
 222         val  = val      << shift;
 223         mask = 0x0f1f   << shift;
 224
 225         rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
 226
 227         return 0;
 228 }
 229
 230 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
 231                                   struct rsnd_dai_stream *io,
 232                                   unsigned int in_rate,
 233                                   unsigned int out_rate)
 234 {
 235         struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 236         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 237         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 238         u32 in, out;
 239         u32 mask, en;
 240         int id = rsnd_mod_id(src_mod);
 241         int shift = (id % 2) ? 16 : 0;
 242
 243         rsnd_mod_confirm_src(src_mod);
 244
 245         rsnd_adg_get_timesel_ratio(priv, io,
 246                                    in_rate, out_rate,
 247                                    &in, &out, &en);
 248
 249         in   = in       << shift;
 250         out  = out      << shift;
 251         mask = 0x0f1f   << shift;
 252
 253         switch (id / 2) {
 254         case 0:
 255                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0,  mask, in);
 256                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
 257                 break;
 258         case 1:
 259                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1,  mask, in);
 260                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
 261                 break;
 262         case 2:
 263                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2,  mask, in);
 264                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
 265                 break;
 266         case 3:
 267                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3,  mask, in);
 268                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
 269                 break;
 270         case 4:
 271                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4,  mask, in);
 272                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
 273                 break;
 274         }
 275
 276         if (en)
 277                 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
 278
 279         return 0;
 280 }
 281
 282 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
 283 {
 284         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 285         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 286         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 287         struct device *dev = rsnd_priv_to_dev(priv);
 288         int id = rsnd_mod_id(ssi_mod);
 289         int shift = (id % 4) * 8;
 290         u32 mask = 0xFF << shift;
 291
 292         rsnd_mod_confirm_ssi(ssi_mod);
 293
 294         val = val << shift;
 295
 296         /*
 297          * SSI 8 is not connected to ADG.
 298          * it works with SSI 7
 299          */
 300         if (id == 8)
 301                 return;
 302
 303         switch (id / 4) {
 304         case 0:
 305                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
 306                 break;
 307         case 1:
 308                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
 309                 break;
 310         case 2:
 311                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
 312                 break;
 313         }
 314
 315         dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
 316 }
 317
 318 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
 319 {
 320         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 321         int i;
 322         int sel_table[] = {
 323                 [CLKA] = 0x1,
 324                 [CLKB] = 0x2,
 325                 [CLKC] = 0x3,
 326                 [CLKI] = 0x0,
 327         };
 328
 329         /*
 330          * find suitable clock from
 331          * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
 332          */
 333         for (i = 0; i < CLKMAX; i++)
 334                 if (rate == adg->clk_rate[i])
 335                         return sel_table[i];
 336
 337         /*
 338          * find divided clock from BRGA/BRGB
 339          */
 340         if (rate == adg->rbga_rate_for_441khz)
 341                 return 0x10;
 342
 343         if (rate == adg->rbgb_rate_for_48khz)
 344                 return 0x20;
 345
 346         return -EIO;
 347 }
 348
 349 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
 350 {
 351         rsnd_adg_set_ssi_clk(ssi_mod, 0);
 352
 353         return 0;
 354 }
 355
 356 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
 357 {
 358         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 359         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 360         struct device *dev = rsnd_priv_to_dev(priv);
 361         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 362         int data;
 363         u32 ckr = 0;
 364
 365         data = rsnd_adg_clk_query(priv, rate);
 366         if (data < 0)
 367                 return data;
 368
 369         rsnd_adg_set_ssi_clk(ssi_mod, data);
 370
 371         if (rsnd_flags_has(adg, LRCLK_ASYNC)) {
 372                 if (rsnd_flags_has(adg, AUDIO_OUT_48))
 373                         ckr = 0x80000000;
 374         } else {
 375                 if (0 == (rate % 8000))
 376                         ckr = 0x80000000;
 377         }
 378
 379         rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
 380         rsnd_mod_write(adg_mod, BRRA,  adg->rbga);
 381         rsnd_mod_write(adg_mod, BRRB,  adg->rbgb);
 382
 383         dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
 384                 (ckr) ? 'B' : 'A',
 385                 (ckr) ? adg->rbgb_rate_for_48khz :
 386                         adg->rbga_rate_for_441khz);
 387
 388         return 0;
 389 }
 390
 391 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
 392 {
 393         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 394         struct device *dev = rsnd_priv_to_dev(priv);
 395         struct clk *clk;
 396         int i, ret;
 397
 398         for_each_rsnd_clk(clk, adg, i) {
 399                 ret = 0;
 400                 if (enable) {
 401                         ret = clk_prepare_enable(clk);
 402
 403                         /*
 404                          * We shouldn't use clk_get_rate() under
 405                          * atomic context. Let's keep it when
 406                          * rsnd_adg_clk_enable() was called
 407                          */
 408                         adg->clk_rate[i] = clk_get_rate(adg->clk[i]);
 409                 } else {
 410                         clk_disable_unprepare(clk);
 411                 }
 412
 413                 if (ret < 0)
 414                         dev_warn(dev, "can't use clk %d\n", i);
 415         }
 416 }
 417
 418 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
 419                                struct rsnd_adg *adg)
 420 {
 421         struct device *dev = rsnd_priv_to_dev(priv);
 422         struct clk *clk;
 423         int i;
 424
 425         for (i = 0; i < CLKMAX; i++) {
 426                 clk = devm_clk_get(dev, clk_name[i]);
 427                 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
 428         }
 429 }
 430
 431 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
 432                                 struct rsnd_adg *adg)
 433 {
 434         struct clk *clk;
 435         struct device *dev = rsnd_priv_to_dev(priv);
 436         struct device_node *np = dev->of_node;
 437         struct property *prop;
 438         u32 ckr, rbgx, rbga, rbgb;
 439         u32 rate, div;
 440 #define REQ_SIZE 2
 441         u32 req_rate[REQ_SIZE] = {};
 442         uint32_t count = 0;
 443         unsigned long req_48kHz_rate, req_441kHz_rate;
 444         int i, req_size;
 445         const char *parent_clk_name = NULL;
 446         static const char * const clkout_name[] = {
 447                 [CLKOUT]  = "audio_clkout",
 448                 [CLKOUT1] = "audio_clkout1",
 449                 [CLKOUT2] = "audio_clkout2",
 450                 [CLKOUT3] = "audio_clkout3",
 451         };
 452         int brg_table[] = {
 453                 [CLKA] = 0x0,
 454                 [CLKB] = 0x1,
 455                 [CLKC] = 0x4,
 456                 [CLKI] = 0x2,
 457         };
 458
 459         ckr = 0;
 460         rbga = 2; /* default 1/6 */
 461         rbgb = 2; /* default 1/6 */
 462
 463         /*
 464          * ADG supports BRRA/BRRB output only
 465          * this means all clkout0/1/2/3 will be same rate
 466          */
 467         prop = of_find_property(np, "clock-frequency", NULL);
 468         if (!prop)
 469                 goto rsnd_adg_get_clkout_end;
 470
 471         req_size = prop->length / sizeof(u32);
 472         if (req_size > REQ_SIZE) {
 473                 dev_err(dev,
 474                         "too many clock-frequency, use top %d\n", REQ_SIZE);
 475                 req_size = REQ_SIZE;
 476         }
 477
 478         of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
 479         req_48kHz_rate = 0;
 480         req_441kHz_rate = 0;
 481         for (i = 0; i < req_size; i++) {
 482                 if (0 == (req_rate[i] % 44100))
 483                         req_441kHz_rate = req_rate[i];
 484                 if (0 == (req_rate[i] % 48000))
 485                         req_48kHz_rate = req_rate[i];
 486         }
 487
 488         if (req_rate[0] % 48000 == 0)
 489                 rsnd_flags_set(adg, AUDIO_OUT_48);
 490
 491         if (of_get_property(np, "clkout-lr-asynchronous", NULL))
 492                 rsnd_flags_set(adg, LRCLK_ASYNC);
 493
 494         /*
 495          * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
 496          * have 44.1kHz or 48kHz base clocks for now.
 497          *
 498          * SSI itself can divide parent clock by 1/1 - 1/16
 499          * see
 500          *      rsnd_adg_ssi_clk_try_start()
 501          *      rsnd_ssi_master_clk_start()
 502          */
 503         adg->rbga_rate_for_441khz       = 0;
 504         adg->rbgb_rate_for_48khz        = 0;
 505         for_each_rsnd_clk(clk, adg, i) {
 506                 rate = clk_get_rate(clk);
 507
 508                 if (0 == rate) /* not used */
 509                         continue;
 510
 511                 /* RBGA */
 512                 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
 513                         div = 6;
 514                         if (req_441kHz_rate)
 515                                 div = rate / req_441kHz_rate;
 516                         rbgx = rsnd_adg_calculate_rbgx(div);
 517                         if (BRRx_MASK(rbgx) == rbgx) {
 518                                 rbga = rbgx;
 519                                 adg->rbga_rate_for_441khz = rate / div;
 520                                 ckr |= brg_table[i] << 20;
 521                                 if (req_441kHz_rate &&
 522                                     !rsnd_flags_has(adg, AUDIO_OUT_48))
 523                                         parent_clk_name = __clk_get_name(clk);
 524                         }
 525                 }
 526
 527                 /* RBGB */
 528                 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
 529                         div = 6;
 530                         if (req_48kHz_rate)
 531                                 div = rate / req_48kHz_rate;
 532                         rbgx = rsnd_adg_calculate_rbgx(div);
 533                         if (BRRx_MASK(rbgx) == rbgx) {
 534                                 rbgb = rbgx;
 535                                 adg->rbgb_rate_for_48khz = rate / div;
 536                                 ckr |= brg_table[i] << 16;
 537                                 if (req_48kHz_rate &&
 538                                     rsnd_flags_has(adg, AUDIO_OUT_48))
 539                                         parent_clk_name = __clk_get_name(clk);
 540                         }
 541                 }
 542         }
 543
 544         /*
 545          * ADG supports BRRA/BRRB output only.
 546          * this means all clkout0/1/2/3 will be * same rate
 547          */
 548
 549         of_property_read_u32(np, "#clock-cells", &count);
 550         /*
 551          * for clkout
 552          */
 553         if (!count) {
 554                 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
 555                                               parent_clk_name, 0, req_rate[0]);
 556                 if (!IS_ERR(clk)) {
 557                         adg->clkout[CLKOUT] = clk;
 558                         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 559                 }
 560         }
 561         /*
 562          * for clkout0/1/2/3
 563          */
 564         else {
 565                 for (i = 0; i < CLKOUTMAX; i++) {
 566                         clk = clk_register_fixed_rate(dev, clkout_name[i],
 567                                                       parent_clk_name, 0,
 568                                                       req_rate[0]);
 569                         if (!IS_ERR(clk))
 570                                 adg->clkout[i] = clk;
 571                 }
 572                 adg->onecell.clks       = adg->clkout;
 573                 adg->onecell.clk_num    = CLKOUTMAX;
 574                 of_clk_add_provider(np, of_clk_src_onecell_get,
 575                                     &adg->onecell);
 576         }
 577
 578 rsnd_adg_get_clkout_end:
 579         adg->ckr = ckr;
 580         adg->rbga = rbga;
 581         adg->rbgb = rbgb;
 582 }
 583
 584 #ifdef DEBUG
 585 static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg)
 586 {
 587         struct device *dev = rsnd_priv_to_dev(priv);
 588         struct clk *clk;
 589         int i;
 590
 591         for_each_rsnd_clk(clk, adg, i)
 592                 dev_dbg(dev, "%s    : %p : %ld\n",
 593                         clk_name[i], clk, clk_get_rate(clk));
 594
 595         dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
 596                 adg->ckr, adg->rbga, adg->rbgb);
 597         dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz);
 598         dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz);
 599
 600         /*
 601          * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
 602          * by BRGCKR::BRGCKR_31
 603          */
 604         for_each_rsnd_clkout(clk, adg, i)
 605                 dev_dbg(dev, "clkout %d : %p : %ld\n", i,
 606                         clk, clk_get_rate(clk));
 607 }
 608 #else
 609 #define rsnd_adg_clk_dbg_info(priv, adg)
 610 #endif
 611
 612 int rsnd_adg_probe(struct rsnd_priv *priv)
 613 {
 614         struct rsnd_adg *adg;
 615         struct device *dev = rsnd_priv_to_dev(priv);
 616         int ret;
 617
 618         adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
 619         if (!adg)
 620                 return -ENOMEM;
 621
 622         ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
 623                       NULL, NULL, 0, 0);
 624         if (ret)
 625                 return ret;
 626
 627         rsnd_adg_get_clkin(priv, adg);
 628         rsnd_adg_get_clkout(priv, adg);
 629         rsnd_adg_clk_dbg_info(priv, adg);
 630
 631         priv->adg = adg;
 632
 633         rsnd_adg_clk_enable(priv);
 634
 635         return 0;
 636 }
 637
 638 void rsnd_adg_remove(struct rsnd_priv *priv)
 639 {
 640         struct device *dev = rsnd_priv_to_dev(priv);
 641         struct device_node *np = dev->of_node;
 642         struct rsnd_adg *adg = priv->adg;
 643         struct clk *clk;
 644         int i;
 645
 646         for_each_rsnd_clkout(clk, adg, i)
 647                 if (adg->clkout[i])
 648                         clk_unregister_fixed_rate(adg->clkout[i]);
 649
 650         of_clk_del_provider(np);
 651
 652         rsnd_adg_clk_disable(priv);
 653 }