sound/soc/sh/rcar/adg.c

   1 /*
   2  * Helper routines for R-Car sound ADG.
   3  *
   4  *  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/clk-provider.h>
  11 #include "rsnd.h"
  12
  13 #define CLKA    0
  14 #define CLKB    1
  15 #define CLKC    2
  16 #define CLKI    3
  17 #define CLKMAX  4
  18
  19 #define CLKOUT  0
  20 #define CLKOUT1 1
  21 #define CLKOUT2 2
  22 #define CLKOUT3 3
  23 #define CLKOUTMAX 4
  24
  25 #define BRRx_MASK(x) (0x3FF & x)
  26
  27 static struct rsnd_mod_ops adg_ops = {
  28         .name = "adg",
  29 };
  30
  31 struct rsnd_adg {
  32         struct clk *clk[CLKMAX];
  33         struct clk *clkout[CLKOUTMAX];
  34         struct clk_onecell_data onecell;
  35         struct rsnd_mod mod;
  36         u32 flags;
  37
  38         int rbga_rate_for_441khz; /* RBGA */
  39         int rbgb_rate_for_48khz;  /* RBGB */
  40 };
  41
  42 #define LRCLK_ASYNC     (1 << 0)
  43 #define adg_mode_flags(adg)     (adg->flags)
  44
  45 #define for_each_rsnd_clk(pos, adg, i)          \
  46         for (i = 0;                             \
  47              (i < CLKMAX) &&                    \
  48              ((pos) = adg->clk[i]);             \
  49              i++)
  50 #define for_each_rsnd_clkout(pos, adg, i)       \
  51         for (i = 0;                             \
  52              (i < CLKOUTMAX) &&                 \
  53              ((pos) = adg->clkout[i]);  \
  54              i++)
  55 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  56
  57 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
  58 {
  59         int i, ratio;
  60
  61         if (!div)
  62                 return 0;
  63
  64         for (i = 3; i >= 0; i--) {
  65                 ratio = 2 << (i * 2);
  66                 if (0 == (div % ratio))
  67                         return (u32)((i << 8) | ((div / ratio) - 1));
  68         }
  69
  70         return ~0;
  71 }
  72
  73 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
  74 {
  75         struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
  76         int id = rsnd_mod_id(ssi_mod);
  77         int ws = id;
  78
  79         if (rsnd_ssi_is_pin_sharing(io)) {
  80                 switch (id) {
  81                 case 1:
  82                 case 2:
  83                         ws = 0;
  84                         break;
  85                 case 4:
  86                         ws = 3;
  87                         break;
  88                 case 8:
  89                         ws = 7;
  90                         break;
  91                 }
  92         }
  93
  94         return (0x6 + ws) << 8;
  95 }
  96
  97 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
  98                                        struct rsnd_dai_stream *io,
  99                                        unsigned int target_rate,
 100                                        unsigned int *target_val,
 101                                        unsigned int *target_en)
 102 {
 103         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 104         struct device *dev = rsnd_priv_to_dev(priv);
 105         int idx, sel, div, step;
 106         unsigned int val, en;
 107         unsigned int min, diff;
 108         unsigned int sel_rate[] = {
 109                 clk_get_rate(adg->clk[CLKA]),   /* 0000: CLKA */
 110                 clk_get_rate(adg->clk[CLKB]),   /* 0001: CLKB */
 111                 clk_get_rate(adg->clk[CLKC]),   /* 0010: CLKC */
 112                 adg->rbga_rate_for_441khz,      /* 0011: RBGA */
 113                 adg->rbgb_rate_for_48khz,       /* 0100: RBGB */
 114         };
 115
 116         min = ~0;
 117         val = 0;
 118         en = 0;
 119         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 120                 idx = 0;
 121                 step = 2;
 122
 123                 if (!sel_rate[sel])
 124                         continue;
 125
 126                 for (div = 2; div <= 98304; div += step) {
 127                         diff = abs(target_rate - sel_rate[sel] / div);
 128                         if (min > diff) {
 129                                 val = (sel << 8) | idx;
 130                                 min = diff;
 131                                 en = 1 << (sel + 1); /* fixme */
 132                         }
 133
 134                         /*
 135                          * step of 0_0000 / 0_0001 / 0_1101
 136                          * are out of order
 137                          */
 138                         if ((idx > 2) && (idx % 2))
 139                                 step *= 2;
 140                         if (idx == 0x1c) {
 141                                 div += step;
 142                                 step *= 2;
 143                         }
 144                         idx++;
 145                 }
 146         }
 147
 148         if (min == ~0) {
 149                 dev_err(dev, "no Input clock\n");
 150                 return;
 151         }
 152
 153         *target_val = val;
 154         if (target_en)
 155                 *target_en = en;
 156 }
 157
 158 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
 159                                        struct rsnd_dai_stream *io,
 160                                        unsigned int in_rate,
 161                                        unsigned int out_rate,
 162                                        u32 *in, u32 *out, u32 *en)
 163 {
 164         struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
 165         unsigned int target_rate;
 166         u32 *target_val;
 167         u32 _in;
 168         u32 _out;
 169         u32 _en;
 170
 171         /* default = SSI WS */
 172         _in =
 173         _out = rsnd_adg_ssi_ws_timing_gen2(io);
 174
 175         target_rate = 0;
 176         target_val = NULL;
 177         _en = 0;
 178         if (runtime->rate != in_rate) {
 179                 target_rate = out_rate;
 180                 target_val  = &_out;
 181         } else if (runtime->rate != out_rate) {
 182                 target_rate = in_rate;
 183                 target_val  = &_in;
 184         }
 185
 186         if (target_rate)
 187                 __rsnd_adg_get_timesel_ratio(priv, io,
 188                                              target_rate,
 189                                              target_val, &_en);
 190
 191         if (in)
 192                 *in = _in;
 193         if (out)
 194                 *out = _out;
 195         if (en)
 196                 *en = _en;
 197 }
 198
 199 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
 200                                  struct rsnd_dai_stream *io)
 201 {
 202         struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
 203         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 204         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 205         int id = rsnd_mod_id(cmd_mod);
 206         int shift = (id % 2) ? 16 : 0;
 207         u32 mask, val;
 208
 209         rsnd_adg_get_timesel_ratio(priv, io,
 210                                    rsnd_src_get_in_rate(priv, io),
 211                                    rsnd_src_get_out_rate(priv, io),
 212                                    NULL, &val, NULL);
 213
 214         val  = val      << shift;
 215         mask = 0xffff   << shift;
 216
 217         rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
 218
 219         return 0;
 220 }
 221
 222 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
 223                                   struct rsnd_dai_stream *io,
 224                                   unsigned int in_rate,
 225                                   unsigned int out_rate)
 226 {
 227         struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 228         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 229         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 230         u32 in, out;
 231         u32 mask, en;
 232         int id = rsnd_mod_id(src_mod);
 233         int shift = (id % 2) ? 16 : 0;
 234
 235         rsnd_mod_confirm_src(src_mod);
 236
 237         rsnd_adg_get_timesel_ratio(priv, io,
 238                                    in_rate, out_rate,
 239                                    &in, &out, &en);
 240
 241         in   = in       << shift;
 242         out  = out      << shift;
 243         mask = 0xffff   << shift;
 244
 245         switch (id / 2) {
 246         case 0:
 247                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0,  mask, in);
 248                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
 249                 break;
 250         case 1:
 251                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1,  mask, in);
 252                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
 253                 break;
 254         case 2:
 255                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2,  mask, in);
 256                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
 257                 break;
 258         case 3:
 259                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3,  mask, in);
 260                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
 261                 break;
 262         case 4:
 263                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4,  mask, in);
 264                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
 265                 break;
 266         }
 267
 268         if (en)
 269                 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
 270
 271         return 0;
 272 }
 273
 274 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
 275 {
 276         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 277         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 278         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 279         int id = rsnd_mod_id(ssi_mod);
 280         int shift = (id % 4) * 8;
 281         u32 mask = 0xFF << shift;
 282
 283         rsnd_mod_confirm_ssi(ssi_mod);
 284
 285         val = val << shift;
 286
 287         /*
 288          * SSI 8 is not connected to ADG.
 289          * it works with SSI 7
 290          */
 291         if (id == 8)
 292                 return;
 293
 294         switch (id / 4) {
 295         case 0:
 296                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
 297                 break;
 298         case 1:
 299                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
 300                 break;
 301         case 2:
 302                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
 303                 break;
 304         }
 305 }
 306
 307 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
 308 {
 309         rsnd_adg_set_ssi_clk(ssi_mod, 0);
 310
 311         return 0;
 312 }
 313
 314 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
 315 {
 316         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 317         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 318         struct device *dev = rsnd_priv_to_dev(priv);
 319         struct clk *clk;
 320         int i;
 321         u32 data;
 322         int sel_table[] = {
 323                 [CLKA] = 0x1,
 324                 [CLKB] = 0x2,
 325                 [CLKC] = 0x3,
 326                 [CLKI] = 0x0,
 327         };
 328
 329         dev_dbg(dev, "request clock = %d\n", rate);
 330
 331         /*
 332          * find suitable clock from
 333          * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
 334          */
 335         data = 0;
 336         for_each_rsnd_clk(clk, adg, i) {
 337                 if (rate == clk_get_rate(clk)) {
 338                         data = sel_table[i];
 339                         goto found_clock;
 340                 }
 341         }
 342
 343         /*
 344          * find divided clock from BRGA/BRGB
 345          */
 346         if (rate  == adg->rbga_rate_for_441khz) {
 347                 data = 0x10;
 348                 goto found_clock;
 349         }
 350
 351         if (rate == adg->rbgb_rate_for_48khz) {
 352                 data = 0x20;
 353                 goto found_clock;
 354         }
 355
 356         return -EIO;
 357
 358 found_clock:
 359
 360         rsnd_adg_set_ssi_clk(ssi_mod, data);
 361
 362         if (!(adg_mode_flags(adg) & LRCLK_ASYNC)) {
 363                 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 364                 u32 ckr = 0;
 365
 366                 if (0 == (rate % 8000))
 367                         ckr = 0x80000000;
 368
 369                 rsnd_mod_bset(adg_mod, SSICKR, 0x80000000, ckr);
 370         }
 371
 372         dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
 373                 rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
 374                 data, rate);
 375
 376         return 0;
 377 }
 378
 379 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
 380                                struct rsnd_adg *adg)
 381 {
 382         struct device *dev = rsnd_priv_to_dev(priv);
 383         struct clk *clk;
 384         static const char * const clk_name[] = {
 385                 [CLKA]  = "clk_a",
 386                 [CLKB]  = "clk_b",
 387                 [CLKC]  = "clk_c",
 388                 [CLKI]  = "clk_i",
 389         };
 390         int i, ret;
 391
 392         for (i = 0; i < CLKMAX; i++) {
 393                 clk = devm_clk_get(dev, clk_name[i]);
 394                 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
 395         }
 396
 397         for_each_rsnd_clk(clk, adg, i) {
 398                 ret = clk_prepare_enable(clk);
 399                 if (ret < 0)
 400                         dev_warn(dev, "can't use clk %d\n", i);
 401
 402                 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
 403         }
 404 }
 405
 406 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
 407                                 struct rsnd_adg *adg)
 408 {
 409         struct clk *clk;
 410         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 411         struct device *dev = rsnd_priv_to_dev(priv);
 412         struct device_node *np = dev->of_node;
 413         u32 ckr, rbgx, rbga, rbgb;
 414         u32 rate, req_rate = 0, div;
 415         uint32_t count = 0;
 416         unsigned long req_48kHz_rate, req_441kHz_rate;
 417         int i;
 418         const char *parent_clk_name = NULL;
 419         static const char * const clkout_name[] = {
 420                 [CLKOUT]  = "audio_clkout",
 421                 [CLKOUT1] = "audio_clkout1",
 422                 [CLKOUT2] = "audio_clkout2",
 423                 [CLKOUT3] = "audio_clkout3",
 424         };
 425         int brg_table[] = {
 426                 [CLKA] = 0x0,
 427                 [CLKB] = 0x1,
 428                 [CLKC] = 0x4,
 429                 [CLKI] = 0x2,
 430         };
 431
 432         of_property_read_u32(np, "#clock-cells", &count);
 433
 434         /*
 435          * ADG supports BRRA/BRRB output only
 436          * this means all clkout0/1/2/3 will be same rate
 437          */
 438         of_property_read_u32(np, "clock-frequency", &req_rate);
 439         req_48kHz_rate = 0;
 440         req_441kHz_rate = 0;
 441         if (0 == (req_rate % 44100))
 442                 req_441kHz_rate = req_rate;
 443         if (0 == (req_rate % 48000))
 444                 req_48kHz_rate = req_rate;
 445
 446         /*
 447          * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
 448          * have 44.1kHz or 48kHz base clocks for now.
 449          *
 450          * SSI itself can divide parent clock by 1/1 - 1/16
 451          * see
 452          *      rsnd_adg_ssi_clk_try_start()
 453          *      rsnd_ssi_master_clk_start()
 454          */
 455         ckr = 0;
 456         rbga = 2; /* default 1/6 */
 457         rbgb = 2; /* default 1/6 */
 458         adg->rbga_rate_for_441khz       = 0;
 459         adg->rbgb_rate_for_48khz        = 0;
 460         for_each_rsnd_clk(clk, adg, i) {
 461                 rate = clk_get_rate(clk);
 462
 463                 if (0 == rate) /* not used */
 464                         continue;
 465
 466                 /* RBGA */
 467                 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
 468                         div = 6;
 469                         if (req_441kHz_rate)
 470                                 div = rate / req_441kHz_rate;
 471                         rbgx = rsnd_adg_calculate_rbgx(div);
 472                         if (BRRx_MASK(rbgx) == rbgx) {
 473                                 rbga = rbgx;
 474                                 adg->rbga_rate_for_441khz = rate / div;
 475                                 ckr |= brg_table[i] << 20;
 476                                 if (req_441kHz_rate)
 477                                         parent_clk_name = __clk_get_name(clk);
 478                         }
 479                 }
 480
 481                 /* RBGB */
 482                 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
 483                         div = 6;
 484                         if (req_48kHz_rate)
 485                                 div = rate / req_48kHz_rate;
 486                         rbgx = rsnd_adg_calculate_rbgx(div);
 487                         if (BRRx_MASK(rbgx) == rbgx) {
 488                                 rbgb = rbgx;
 489                                 adg->rbgb_rate_for_48khz = rate / div;
 490                                 ckr |= brg_table[i] << 16;
 491                                 if (req_48kHz_rate) {
 492                                         parent_clk_name = __clk_get_name(clk);
 493                                         ckr |= 0x80000000;
 494                                 }
 495                         }
 496                 }
 497         }
 498
 499         /*
 500          * ADG supports BRRA/BRRB output only.
 501          * this means all clkout0/1/2/3 will be * same rate
 502          */
 503
 504         /*
 505          * for clkout
 506          */
 507         if (!count) {
 508                 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
 509                                               parent_clk_name, 0, req_rate);
 510                 if (!IS_ERR(clk)) {
 511                         adg->clkout[CLKOUT] = clk;
 512                         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 513                 }
 514         }
 515         /*
 516          * for clkout0/1/2/3
 517          */
 518         else {
 519                 for (i = 0; i < CLKOUTMAX; i++) {
 520                         clk = clk_register_fixed_rate(dev, clkout_name[i],
 521                                                       parent_clk_name, 0,
 522                                                       req_rate);
 523                         if (!IS_ERR(clk)) {
 524                                 adg->onecell.clks       = adg->clkout;
 525                                 adg->onecell.clk_num    = CLKOUTMAX;
 526
 527                                 adg->clkout[i] = clk;
 528
 529                                 of_clk_add_provider(np, of_clk_src_onecell_get,
 530                                                     &adg->onecell);
 531                         }
 532                 }
 533         }
 534
 535         rsnd_mod_bset(adg_mod, SSICKR, 0x80FF0000, ckr);
 536         rsnd_mod_write(adg_mod, BRRA,  rbga);
 537         rsnd_mod_write(adg_mod, BRRB,  rbgb);
 538
 539         for_each_rsnd_clkout(clk, adg, i)
 540                 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
 541         dev_dbg(dev, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
 542                 ckr, rbga, rbgb);
 543 }
 544
 545 int rsnd_adg_probe(struct rsnd_priv *priv)
 546 {
 547         struct rsnd_adg *adg;
 548         struct device *dev = rsnd_priv_to_dev(priv);
 549         struct device_node *np = dev->of_node;
 550
 551         adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
 552         if (!adg) {
 553                 dev_err(dev, "ADG allocate failed\n");
 554                 return -ENOMEM;
 555         }
 556
 557         rsnd_mod_init(priv, &adg->mod, &adg_ops,
 558                       NULL, NULL, 0, 0);
 559
 560         rsnd_adg_get_clkin(priv, adg);
 561         rsnd_adg_get_clkout(priv, adg);
 562
 563         if (of_get_property(np, "clkout-lr-asynchronous", NULL))
 564                 adg->flags = LRCLK_ASYNC;
 565
 566         priv->adg = adg;
 567
 568         return 0;
 569 }
 570
 571 void rsnd_adg_remove(struct rsnd_priv *priv)
 572 {
 573         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 574         struct clk *clk;
 575         int i;
 576
 577         for_each_rsnd_clk(clk, adg, i) {
 578                 clk_disable_unprepare(clk);
 579         }
 580 }