1 // SPDX-License-Identifier: GPL-2.0
3 // Fifo-attached Serial Interface (FSI) support for SH7724
5 // Copyright (C) 2009 Renesas Solutions Corp.
6 // Kuninori Morimoto <morimoto.kuninori@renesas.com>
9 // Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/pm_runtime.h>
16 #include <linux/of_device.h>
17 #include <linux/scatterlist.h>
18 #include <linux/sh_dma.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/workqueue.h>
22 #include <sound/soc.h>
23 #include <sound/pcm_params.h>
24 #include <sound/sh_fsi.h>
26 /* PortA/PortB register */
27 #define REG_DO_FMT 0x0000
28 #define REG_DOFF_CTL 0x0004
29 #define REG_DOFF_ST 0x0008
30 #define REG_DI_FMT 0x000C
31 #define REG_DIFF_CTL 0x0010
32 #define REG_DIFF_ST 0x0014
33 #define REG_CKG1 0x0018
34 #define REG_CKG2 0x001C
35 #define REG_DIDT 0x0020
36 #define REG_DODT 0x0024
37 #define REG_MUTE_ST 0x0028
38 #define REG_OUT_DMAC 0x002C
39 #define REG_OUT_SEL 0x0030
40 #define REG_IN_DMAC 0x0038
43 #define MST_CLK_RST 0x0210
44 #define MST_SOFT_RST 0x0214
45 #define MST_FIFO_SZ 0x0218
47 /* core register (depend on FSI version) */
48 #define A_MST_CTLR 0x0180
49 #define B_MST_CTLR 0x01A0
50 #define CPU_INT_ST 0x01F4
51 #define CPU_IEMSK 0x01F8
52 #define CPU_IMSK 0x01FC
59 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */
60 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
61 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
62 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
64 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
65 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
66 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
68 #define CR_MONO (0x0 << 4)
69 #define CR_MONO_D (0x1 << 4)
70 #define CR_PCM (0x2 << 4)
71 #define CR_I2S (0x3 << 4)
72 #define CR_TDM (0x4 << 4)
73 #define CR_TDM_D (0x5 << 4)
77 #define VDMD_MASK (0x3 << 4)
78 #define VDMD_FRONT (0x0 << 4) /* Package in front */
79 #define VDMD_BACK (0x1 << 4) /* Package in back */
80 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
82 #define DMA_ON (0x1 << 0)
86 #define IRQ_HALF 0x00100000
87 #define FIFO_CLR 0x00000001
90 #define ERR_OVER 0x00000010
91 #define ERR_UNDER 0x00000001
92 #define ST_ERR (ERR_OVER | ERR_UNDER)
95 #define ACKMD_MASK 0x00007000
96 #define BPFMD_MASK 0x00000700
101 #define BP (1 << 4) /* Fix the signal of Biphase output */
102 #define SE (1 << 0) /* Fix the master clock */
108 /* IO SHIFT / MACRO */
113 #define AB_IO(param, shift) (param << shift)
116 #define PBSR (1 << 12) /* Port B Software Reset */
117 #define PASR (1 << 8) /* Port A Software Reset */
118 #define IR (1 << 4) /* Interrupt Reset */
119 #define FSISR (1 << 0) /* Software Reset */
122 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
123 /* 1: Biphase and serial */
126 #define FIFO_SZ_MASK 0x7
128 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
130 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
137 * A : sample widtht 16bit setting
138 * B : sample widtht 24bit setting
141 #define SHIFT_16DATA 0
142 #define SHIFT_24DATA 4
144 #define PACKAGE_24BITBUS_BACK 0
145 #define PACKAGE_24BITBUS_FRONT 1
146 #define PACKAGE_16BITBUS_STREAM 2
148 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
149 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
152 * FSI driver use below type name for variable
154 * xxx_num : number of data
155 * xxx_pos : position of data
156 * xxx_capa : capacity of data
160 * period/frame/sample image
164 * period pos period pos
166 * |<-------------------- period--------------------->|
167 * ==|============================================ ... =|==
169 * ||<----- frame ----->|<------ frame ----->| ... |
170 * |+--------------------+--------------------+- ... |
171 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
172 * |+--------------------+--------------------+- ... |
173 * ==|============================================ ... =|==
191 * FSIxCLK [CPG] (ick) -------> |
192 * |-> FSI_DIV (div)-> FSI2
193 * FSIxCK [external] (xck) ---> |
200 struct fsi_stream_handler;
204 * these are initialized by fsi_stream_init()
206 struct snd_pcm_substream *substream;
207 int fifo_sample_capa; /* sample capacity of FSI FIFO */
208 int buff_sample_capa; /* sample capacity of ALSA buffer */
209 int buff_sample_pos; /* sample position of ALSA buffer */
210 int period_samples; /* sample number / 1 period */
211 int period_pos; /* current period position */
212 int sample_width; /* sample width */
222 * these are initialized by fsi_handler_init()
224 struct fsi_stream_handler *handler;
225 struct fsi_priv *priv;
228 * these are for DMAEngine
230 struct dma_chan *chan;
235 /* see [FSI clock] */
240 int (*set_rate)(struct device *dev,
241 struct fsi_priv *fsi);
250 struct fsi_master *master;
252 struct fsi_stream playback;
253 struct fsi_stream capture;
255 struct fsi_clk clock;
260 unsigned int clk_master:1;
261 unsigned int clk_cpg:1;
262 unsigned int spdif:1;
263 unsigned int enable_stream:1;
264 unsigned int bit_clk_inv:1;
265 unsigned int lr_clk_inv:1;
268 struct fsi_stream_handler {
269 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
270 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
271 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
272 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
273 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
274 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
277 #define fsi_stream_handler_call(io, func, args...) \
279 !((io)->handler->func) ? 0 : \
280 (io)->handler->func(args))
294 struct fsi_priv fsia;
295 struct fsi_priv fsib;
296 const struct fsi_core *core;
300 static inline int fsi_stream_is_play(struct fsi_priv *fsi,
301 struct fsi_stream *io)
303 return &fsi->playback == io;
308 * basic read write function
311 static void __fsi_reg_write(u32 __iomem *reg, u32 data)
313 /* valid data area is 24bit */
316 __raw_writel(data, reg);
319 static u32 __fsi_reg_read(u32 __iomem *reg)
321 return __raw_readl(reg);
324 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
326 u32 val = __fsi_reg_read(reg);
331 __fsi_reg_write(reg, val);
334 #define fsi_reg_write(p, r, d)\
335 __fsi_reg_write((p->base + REG_##r), d)
337 #define fsi_reg_read(p, r)\
338 __fsi_reg_read((p->base + REG_##r))
340 #define fsi_reg_mask_set(p, r, m, d)\
341 __fsi_reg_mask_set((p->base + REG_##r), m, d)
343 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
344 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
345 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
350 spin_lock_irqsave(&master->lock, flags);
351 ret = __fsi_reg_read(master->base + reg);
352 spin_unlock_irqrestore(&master->lock, flags);
357 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
358 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
359 static void _fsi_master_mask_set(struct fsi_master *master,
360 u32 reg, u32 mask, u32 data)
364 spin_lock_irqsave(&master->lock, flags);
365 __fsi_reg_mask_set(master->base + reg, mask, data);
366 spin_unlock_irqrestore(&master->lock, flags);
372 static int fsi_version(struct fsi_master *master)
374 return master->core->ver;
377 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
382 static int fsi_is_clk_master(struct fsi_priv *fsi)
384 return fsi->clk_master;
387 static int fsi_is_port_a(struct fsi_priv *fsi)
389 return fsi->master->base == fsi->base;
392 static int fsi_is_spdif(struct fsi_priv *fsi)
397 static int fsi_is_enable_stream(struct fsi_priv *fsi)
399 return fsi->enable_stream;
402 static int fsi_is_play(struct snd_pcm_substream *substream)
404 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
407 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
409 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
411 return asoc_rtd_to_cpu(rtd, 0);
414 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
416 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
419 return &master->fsia;
421 return &master->fsib;
424 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
426 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
429 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
431 int is_play = fsi_stream_is_play(fsi, io);
432 int is_porta = fsi_is_port_a(fsi);
436 shift = is_play ? AO_SHIFT : AI_SHIFT;
438 shift = is_play ? BO_SHIFT : BI_SHIFT;
443 static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
445 return frames * fsi->chan_num;
448 static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
450 return samples / fsi->chan_num;
453 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
454 struct fsi_stream *io)
456 int is_play = fsi_stream_is_play(fsi, io);
461 fsi_reg_read(fsi, DOFF_ST) :
462 fsi_reg_read(fsi, DIFF_ST);
464 frames = 0x1ff & (status >> 8);
466 return fsi_frame2sample(fsi, frames);
469 static void fsi_count_fifo_err(struct fsi_priv *fsi)
471 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
472 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
474 if (ostatus & ERR_OVER)
475 fsi->playback.oerr_num++;
477 if (ostatus & ERR_UNDER)
478 fsi->playback.uerr_num++;
480 if (istatus & ERR_OVER)
481 fsi->capture.oerr_num++;
483 if (istatus & ERR_UNDER)
484 fsi->capture.uerr_num++;
486 fsi_reg_write(fsi, DOFF_ST, 0);
487 fsi_reg_write(fsi, DIFF_ST, 0);
491 * fsi_stream_xx() function
493 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
494 struct snd_pcm_substream *substream)
496 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
499 static int fsi_stream_is_working(struct fsi_priv *fsi,
500 struct fsi_stream *io)
502 struct fsi_master *master = fsi_get_master(fsi);
506 spin_lock_irqsave(&master->lock, flags);
507 ret = !!(io->substream && io->substream->runtime);
508 spin_unlock_irqrestore(&master->lock, flags);
513 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
518 static void fsi_stream_init(struct fsi_priv *fsi,
519 struct fsi_stream *io,
520 struct snd_pcm_substream *substream)
522 struct snd_pcm_runtime *runtime = substream->runtime;
523 struct fsi_master *master = fsi_get_master(fsi);
526 spin_lock_irqsave(&master->lock, flags);
527 io->substream = substream;
528 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
529 io->buff_sample_pos = 0;
530 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
532 io->sample_width = samples_to_bytes(runtime, 1);
534 io->oerr_num = -1; /* ignore 1st err */
535 io->uerr_num = -1; /* ignore 1st err */
536 fsi_stream_handler_call(io, init, fsi, io);
537 spin_unlock_irqrestore(&master->lock, flags);
540 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
542 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
543 struct fsi_master *master = fsi_get_master(fsi);
546 spin_lock_irqsave(&master->lock, flags);
548 if (io->oerr_num > 0)
549 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
551 if (io->uerr_num > 0)
552 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
554 fsi_stream_handler_call(io, quit, fsi, io);
555 io->substream = NULL;
556 io->buff_sample_capa = 0;
557 io->buff_sample_pos = 0;
558 io->period_samples = 0;
560 io->sample_width = 0;
564 spin_unlock_irqrestore(&master->lock, flags);
567 static int fsi_stream_transfer(struct fsi_stream *io)
569 struct fsi_priv *fsi = fsi_stream_to_priv(io);
573 return fsi_stream_handler_call(io, transfer, fsi, io);
576 #define fsi_stream_start(fsi, io)\
577 fsi_stream_handler_call(io, start_stop, fsi, io, 1)
579 #define fsi_stream_stop(fsi, io)\
580 fsi_stream_handler_call(io, start_stop, fsi, io, 0)
582 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
584 struct fsi_stream *io;
588 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
591 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
601 static int fsi_stream_remove(struct fsi_priv *fsi)
603 struct fsi_stream *io;
607 ret1 = fsi_stream_handler_call(io, remove, fsi, io);
610 ret2 = fsi_stream_handler_call(io, remove, fsi, io);
621 * format/bus/dma setting
623 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
624 u32 bus, struct device *dev)
626 struct fsi_master *master = fsi_get_master(fsi);
627 int is_play = fsi_stream_is_play(fsi, io);
630 if (fsi_version(master) >= 2) {
634 * FSI2 needs DMA/Bus setting
637 case PACKAGE_24BITBUS_FRONT:
640 dev_dbg(dev, "24bit bus / package in front\n");
642 case PACKAGE_16BITBUS_STREAM:
645 dev_dbg(dev, "16bit bus / stream mode\n");
647 case PACKAGE_24BITBUS_BACK:
651 dev_dbg(dev, "24bit bus / package in back\n");
656 fsi_reg_write(fsi, OUT_DMAC, dma);
658 fsi_reg_write(fsi, IN_DMAC, dma);
662 fsi_reg_write(fsi, DO_FMT, fmt);
664 fsi_reg_write(fsi, DI_FMT, fmt);
671 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
673 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
674 struct fsi_master *master = fsi_get_master(fsi);
676 fsi_core_mask_set(master, imsk, data, data);
677 fsi_core_mask_set(master, iemsk, data, data);
680 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
682 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
683 struct fsi_master *master = fsi_get_master(fsi);
685 fsi_core_mask_set(master, imsk, data, 0);
686 fsi_core_mask_set(master, iemsk, data, 0);
689 static u32 fsi_irq_get_status(struct fsi_master *master)
691 return fsi_core_read(master, int_st);
694 static void fsi_irq_clear_status(struct fsi_priv *fsi)
697 struct fsi_master *master = fsi_get_master(fsi);
699 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
700 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
702 /* clear interrupt factor */
703 fsi_core_mask_set(master, int_st, data, 0);
707 * SPDIF master clock function
709 * These functions are used later FSI2
711 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
713 struct fsi_master *master = fsi_get_master(fsi);
717 val = enable ? mask : 0;
720 fsi_core_mask_set(master, a_mclk, mask, val) :
721 fsi_core_mask_set(master, b_mclk, mask, val);
727 static int fsi_clk_init(struct device *dev,
728 struct fsi_priv *fsi,
732 int (*set_rate)(struct device *dev,
733 struct fsi_priv *fsi))
735 struct fsi_clk *clock = &fsi->clock;
736 int is_porta = fsi_is_port_a(fsi);
743 clock->set_rate = set_rate;
745 clock->own = devm_clk_get(dev, NULL);
746 if (IS_ERR(clock->own))
751 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
752 if (IS_ERR(clock->xck)) {
753 dev_err(dev, "can't get xck clock\n");
756 if (clock->xck == clock->own) {
757 dev_err(dev, "cpu doesn't support xck clock\n");
762 /* FSIACLK/FSIBCLK */
764 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
765 if (IS_ERR(clock->ick)) {
766 dev_err(dev, "can't get ick clock\n");
769 if (clock->ick == clock->own) {
770 dev_err(dev, "cpu doesn't support ick clock\n");
777 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
778 if (IS_ERR(clock->div)) {
779 dev_err(dev, "can't get div clock\n");
782 if (clock->div == clock->own) {
783 dev_err(dev, "cpu doesn't support div clock\n");
791 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
792 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
794 fsi->clock.rate = rate;
797 static int fsi_clk_is_valid(struct fsi_priv *fsi)
799 return fsi->clock.set_rate &&
803 static int fsi_clk_enable(struct device *dev,
804 struct fsi_priv *fsi)
806 struct fsi_clk *clock = &fsi->clock;
809 if (!fsi_clk_is_valid(fsi))
812 if (0 == clock->count) {
813 ret = clock->set_rate(dev, fsi);
815 fsi_clk_invalid(fsi);
819 ret = clk_enable(clock->xck);
822 ret = clk_enable(clock->ick);
825 ret = clk_enable(clock->div);
835 clk_disable(clock->ick);
837 clk_disable(clock->xck);
842 static int fsi_clk_disable(struct device *dev,
843 struct fsi_priv *fsi)
845 struct fsi_clk *clock = &fsi->clock;
847 if (!fsi_clk_is_valid(fsi))
850 if (1 == clock->count--) {
851 clk_disable(clock->xck);
852 clk_disable(clock->ick);
853 clk_disable(clock->div);
859 static int fsi_clk_set_ackbpf(struct device *dev,
860 struct fsi_priv *fsi,
861 int ackmd, int bpfmd)
865 /* check ackmd/bpfmd relationship */
867 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
889 dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
914 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
918 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
920 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
926 static int fsi_clk_set_rate_external(struct device *dev,
927 struct fsi_priv *fsi)
929 struct clk *xck = fsi->clock.xck;
930 struct clk *ick = fsi->clock.ick;
931 unsigned long rate = fsi->clock.rate;
936 /* check clock rate */
937 xrate = clk_get_rate(xck);
939 dev_err(dev, "unsupported clock rate\n");
943 clk_set_parent(ick, xck);
944 clk_set_rate(ick, xrate);
946 bpfmd = fsi->chan_num * 32;
947 ackmd = xrate / rate;
949 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
951 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
953 dev_err(dev, "%s failed", __func__);
958 static int fsi_clk_set_rate_cpg(struct device *dev,
959 struct fsi_priv *fsi)
961 struct clk *ick = fsi->clock.ick;
962 struct clk *div = fsi->clock.div;
963 unsigned long rate = fsi->clock.rate;
964 unsigned long target = 0; /* 12288000 or 11289600 */
965 unsigned long actual, cout;
966 unsigned long diff, min;
967 unsigned long best_cout, best_act;
972 if (!(12288000 % rate))
974 if (!(11289600 % rate))
977 dev_err(dev, "unsupported rate\n");
981 bpfmd = fsi->chan_num * 32;
982 ackmd = target / rate;
983 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
985 dev_err(dev, "%s failed", __func__);
992 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
994 * But, it needs to find best match of CPG and FSI_DIV
995 * combination, since it is difficult to generate correct
996 * frequency of audio clock from ick clock only.
997 * Because ick is created from its parent clock.
999 * target = rate x [512/256/128/64]fs
1000 * cout = round(target x adjustment)
1001 * actual = cout / adjustment (by FSI-DIV) ~= target
1007 for (adj = 1; adj < 0xffff; adj++) {
1009 cout = target * adj;
1010 if (cout > 100000000) /* max clock = 100MHz */
1013 /* cout/actual audio clock */
1014 cout = clk_round_rate(ick, cout);
1015 actual = cout / adj;
1017 /* find best frequency */
1018 diff = abs(actual - target);
1026 ret = clk_set_rate(ick, best_cout);
1028 dev_err(dev, "ick clock failed\n");
1032 ret = clk_set_rate(div, clk_round_rate(div, best_act));
1034 dev_err(dev, "div clock failed\n");
1038 dev_dbg(dev, "ick/div = %ld/%ld\n",
1039 clk_get_rate(ick), clk_get_rate(div));
1044 static void fsi_pointer_update(struct fsi_stream *io, int size)
1046 io->buff_sample_pos += size;
1048 if (io->buff_sample_pos >=
1049 io->period_samples * (io->period_pos + 1)) {
1050 struct snd_pcm_substream *substream = io->substream;
1051 struct snd_pcm_runtime *runtime = substream->runtime;
1055 if (io->period_pos >= runtime->periods) {
1056 io->buff_sample_pos = 0;
1060 snd_pcm_period_elapsed(substream);
1065 * pio data transfer handler
1067 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
1071 if (fsi_is_enable_stream(fsi)) {
1075 * fsi_pio_push_init()
1077 u32 *buf = (u32 *)_buf;
1079 for (i = 0; i < samples / 2; i++)
1080 fsi_reg_write(fsi, DODT, buf[i]);
1083 u16 *buf = (u16 *)_buf;
1085 for (i = 0; i < samples; i++)
1086 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
1090 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
1092 u16 *buf = (u16 *)_buf;
1095 for (i = 0; i < samples; i++)
1096 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
1099 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
1101 u32 *buf = (u32 *)_buf;
1104 for (i = 0; i < samples; i++)
1105 fsi_reg_write(fsi, DODT, *(buf + i));
1108 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
1110 u32 *buf = (u32 *)_buf;
1113 for (i = 0; i < samples; i++)
1114 *(buf + i) = fsi_reg_read(fsi, DIDT);
1117 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
1119 struct snd_pcm_runtime *runtime = io->substream->runtime;
1121 return runtime->dma_area +
1122 samples_to_bytes(runtime, io->buff_sample_pos);
1125 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
1126 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
1127 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
1132 if (!fsi_stream_is_working(fsi, io))
1135 buf = fsi_pio_get_area(fsi, io);
1137 switch (io->sample_width) {
1139 run16(fsi, buf, samples);
1142 run32(fsi, buf, samples);
1148 fsi_pointer_update(io, samples);
1153 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
1155 int sample_residues; /* samples in FSI fifo */
1156 int sample_space; /* ALSA free samples space */
1159 sample_residues = fsi_get_current_fifo_samples(fsi, io);
1160 sample_space = io->buff_sample_capa - io->buff_sample_pos;
1162 samples = min(sample_residues, sample_space);
1164 return fsi_pio_transfer(fsi, io,
1170 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
1172 int sample_residues; /* ALSA residue samples */
1173 int sample_space; /* FSI fifo free samples space */
1176 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
1177 sample_space = io->fifo_sample_capa -
1178 fsi_get_current_fifo_samples(fsi, io);
1180 samples = min(sample_residues, sample_space);
1182 return fsi_pio_transfer(fsi, io,
1188 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1191 struct fsi_master *master = fsi_get_master(fsi);
1192 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1195 fsi_irq_enable(fsi, io);
1197 fsi_irq_disable(fsi, io);
1199 if (fsi_is_clk_master(fsi))
1200 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1205 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
1208 * we can use 16bit stream mode
1209 * when "playback" and "16bit data"
1210 * and platform allows "stream mode"
1214 if (fsi_is_enable_stream(fsi))
1215 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1216 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1218 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1219 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1223 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
1226 * always 24bit bus, package back when "capture"
1228 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1229 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1233 static struct fsi_stream_handler fsi_pio_push_handler = {
1234 .init = fsi_pio_push_init,
1235 .transfer = fsi_pio_push,
1236 .start_stop = fsi_pio_start_stop,
1239 static struct fsi_stream_handler fsi_pio_pop_handler = {
1240 .init = fsi_pio_pop_init,
1241 .transfer = fsi_pio_pop,
1242 .start_stop = fsi_pio_start_stop,
1245 static irqreturn_t fsi_interrupt(int irq, void *data)
1247 struct fsi_master *master = data;
1248 u32 int_st = fsi_irq_get_status(master);
1250 /* clear irq status */
1251 fsi_master_mask_set(master, SOFT_RST, IR, 0);
1252 fsi_master_mask_set(master, SOFT_RST, IR, IR);
1254 if (int_st & AB_IO(1, AO_SHIFT))
1255 fsi_stream_transfer(&master->fsia.playback);
1256 if (int_st & AB_IO(1, BO_SHIFT))
1257 fsi_stream_transfer(&master->fsib.playback);
1258 if (int_st & AB_IO(1, AI_SHIFT))
1259 fsi_stream_transfer(&master->fsia.capture);
1260 if (int_st & AB_IO(1, BI_SHIFT))
1261 fsi_stream_transfer(&master->fsib.capture);
1263 fsi_count_fifo_err(&master->fsia);
1264 fsi_count_fifo_err(&master->fsib);
1266 fsi_irq_clear_status(&master->fsia);
1267 fsi_irq_clear_status(&master->fsib);
1273 * dma data transfer handler
1275 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
1278 * 24bit data : 24bit bus / package in back
1279 * 16bit data : 16bit bus / stream mode
1281 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1282 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1287 static void fsi_dma_complete(void *data)
1289 struct fsi_stream *io = (struct fsi_stream *)data;
1290 struct fsi_priv *fsi = fsi_stream_to_priv(io);
1292 fsi_pointer_update(io, io->period_samples);
1294 fsi_count_fifo_err(fsi);
1297 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
1299 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
1300 struct snd_pcm_substream *substream = io->substream;
1301 struct dma_async_tx_descriptor *desc;
1302 int is_play = fsi_stream_is_play(fsi, io);
1303 enum dma_transfer_direction dir;
1307 dir = DMA_MEM_TO_DEV;
1309 dir = DMA_DEV_TO_MEM;
1311 desc = dmaengine_prep_dma_cyclic(io->chan,
1312 substream->runtime->dma_addr,
1313 snd_pcm_lib_buffer_bytes(substream),
1314 snd_pcm_lib_period_bytes(substream),
1316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1318 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n");
1319 goto fsi_dma_transfer_err;
1322 desc->callback = fsi_dma_complete;
1323 desc->callback_param = io;
1325 if (dmaengine_submit(desc) < 0) {
1326 dev_err(dai->dev, "tx_submit() fail\n");
1327 goto fsi_dma_transfer_err;
1330 dma_async_issue_pending(io->chan);
1335 * In DMAEngine case, codec and FSI cannot be started simultaneously
1336 * since FSI is using the scheduler work queue.
1337 * Therefore, in capture case, probably FSI FIFO will have got
1338 * overflow error in this point.
1339 * in that case, DMA cannot start transfer until error was cleared.
1342 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
1343 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1344 fsi_reg_write(fsi, DIFF_ST, 0);
1350 fsi_dma_transfer_err:
1354 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1357 struct fsi_master *master = fsi_get_master(fsi);
1358 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1359 u32 enable = start ? DMA_ON : 0;
1361 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
1363 dmaengine_terminate_all(io->chan);
1365 if (fsi_is_clk_master(fsi))
1366 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1371 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
1373 int is_play = fsi_stream_is_play(fsi, io);
1375 #ifdef CONFIG_SUPERH
1376 dma_cap_mask_t mask;
1378 dma_cap_set(DMA_SLAVE, mask);
1380 io->chan = dma_request_channel(mask, shdma_chan_filter,
1381 (void *)io->dma_id);
1383 io->chan = dma_request_slave_channel(dev, is_play ? "tx" : "rx");
1386 struct dma_slave_config cfg = {};
1390 cfg.dst_addr = fsi->phys + REG_DODT;
1391 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1392 cfg.direction = DMA_MEM_TO_DEV;
1394 cfg.src_addr = fsi->phys + REG_DIDT;
1395 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1396 cfg.direction = DMA_DEV_TO_MEM;
1399 ret = dmaengine_slave_config(io->chan, &cfg);
1401 dma_release_channel(io->chan);
1408 /* switch to PIO handler */
1410 fsi->playback.handler = &fsi_pio_push_handler;
1412 fsi->capture.handler = &fsi_pio_pop_handler;
1414 dev_info(dev, "switch handler (dma => pio)\n");
1417 return fsi_stream_probe(fsi, dev);
1423 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
1425 fsi_stream_stop(fsi, io);
1428 dma_release_channel(io->chan);
1434 static struct fsi_stream_handler fsi_dma_push_handler = {
1435 .init = fsi_dma_init,
1436 .probe = fsi_dma_probe,
1437 .transfer = fsi_dma_transfer,
1438 .remove = fsi_dma_remove,
1439 .start_stop = fsi_dma_push_start_stop,
1445 static void fsi_fifo_init(struct fsi_priv *fsi,
1446 struct fsi_stream *io,
1449 struct fsi_master *master = fsi_get_master(fsi);
1450 int is_play = fsi_stream_is_play(fsi, io);
1454 /* get on-chip RAM capacity */
1455 shift = fsi_master_read(master, FIFO_SZ);
1456 shift >>= fsi_get_port_shift(fsi, io);
1457 shift &= FIFO_SZ_MASK;
1458 frame_capa = 256 << shift;
1459 dev_dbg(dev, "fifo = %d words\n", frame_capa);
1462 * The maximum number of sample data varies depending
1463 * on the number of channels selected for the format.
1465 * FIFOs are used in 4-channel units in 3-channel mode
1466 * and in 8-channel units in 5- to 7-channel mode
1467 * meaning that more FIFOs than the required size of DPRAM
1470 * ex) if 256 words of DP-RAM is connected
1471 * 1 channel: 256 (256 x 1 = 256)
1472 * 2 channels: 128 (128 x 2 = 256)
1473 * 3 channels: 64 ( 64 x 3 = 192)
1474 * 4 channels: 64 ( 64 x 4 = 256)
1475 * 5 channels: 32 ( 32 x 5 = 160)
1476 * 6 channels: 32 ( 32 x 6 = 192)
1477 * 7 channels: 32 ( 32 x 7 = 224)
1478 * 8 channels: 32 ( 32 x 8 = 256)
1480 for (i = 1; i < fsi->chan_num; i <<= 1)
1482 dev_dbg(dev, "%d channel %d store\n",
1483 fsi->chan_num, frame_capa);
1485 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
1488 * set interrupt generation factor
1492 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
1493 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
1495 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
1496 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1500 static int fsi_hw_startup(struct fsi_priv *fsi,
1501 struct fsi_stream *io,
1507 if (fsi_is_clk_master(fsi))
1510 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
1512 /* clock inversion (CKG2) */
1514 if (fsi->bit_clk_inv)
1516 if (fsi->lr_clk_inv)
1518 if (fsi_is_clk_master(fsi))
1520 fsi_reg_write(fsi, CKG2, data);
1523 if (fsi_is_spdif(fsi)) {
1524 fsi_spdif_clk_ctrl(fsi, 1);
1525 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
1532 switch (io->sample_width) {
1534 data = BUSOP_GET(16, io->bus_option);
1537 data = BUSOP_GET(24, io->bus_option);
1540 fsi_format_bus_setup(fsi, io, data, dev);
1543 fsi_irq_disable(fsi, io);
1544 fsi_irq_clear_status(fsi);
1547 fsi_fifo_init(fsi, io, dev);
1549 /* start master clock */
1550 if (fsi_is_clk_master(fsi))
1551 return fsi_clk_enable(dev, fsi);
1556 static int fsi_hw_shutdown(struct fsi_priv *fsi,
1559 /* stop master clock */
1560 if (fsi_is_clk_master(fsi))
1561 return fsi_clk_disable(dev, fsi);
1566 static int fsi_dai_startup(struct snd_pcm_substream *substream,
1567 struct snd_soc_dai *dai)
1569 struct fsi_priv *fsi = fsi_get_priv(substream);
1571 fsi_clk_invalid(fsi);
1576 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
1577 struct snd_soc_dai *dai)
1579 struct fsi_priv *fsi = fsi_get_priv(substream);
1581 fsi_clk_invalid(fsi);
1584 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
1585 struct snd_soc_dai *dai)
1587 struct fsi_priv *fsi = fsi_get_priv(substream);
1588 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1592 case SNDRV_PCM_TRIGGER_START:
1593 fsi_stream_init(fsi, io, substream);
1595 ret = fsi_hw_startup(fsi, io, dai->dev);
1597 ret = fsi_stream_start(fsi, io);
1599 ret = fsi_stream_transfer(io);
1601 case SNDRV_PCM_TRIGGER_STOP:
1603 ret = fsi_hw_shutdown(fsi, dai->dev);
1604 fsi_stream_stop(fsi, io);
1605 fsi_stream_quit(fsi, io);
1612 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
1614 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1615 case SND_SOC_DAIFMT_I2S:
1619 case SND_SOC_DAIFMT_LEFT_J:
1630 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1632 struct fsi_master *master = fsi_get_master(fsi);
1634 if (fsi_version(master) < 2)
1637 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
1643 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1645 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1648 /* set clock master audio interface */
1649 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1650 case SND_SOC_DAIFMT_CBM_CFM:
1652 case SND_SOC_DAIFMT_CBS_CFS:
1653 fsi->clk_master = 1; /* cpu is master */
1659 /* set clock inversion */
1660 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1661 case SND_SOC_DAIFMT_NB_IF:
1662 fsi->bit_clk_inv = 0;
1663 fsi->lr_clk_inv = 1;
1665 case SND_SOC_DAIFMT_IB_NF:
1666 fsi->bit_clk_inv = 1;
1667 fsi->lr_clk_inv = 0;
1669 case SND_SOC_DAIFMT_IB_IF:
1670 fsi->bit_clk_inv = 1;
1671 fsi->lr_clk_inv = 1;
1673 case SND_SOC_DAIFMT_NB_NF:
1675 fsi->bit_clk_inv = 0;
1676 fsi->lr_clk_inv = 0;
1680 if (fsi_is_clk_master(fsi)) {
1682 fsi_clk_init(dai->dev, fsi, 0, 1, 1,
1683 fsi_clk_set_rate_cpg);
1685 fsi_clk_init(dai->dev, fsi, 1, 1, 0,
1686 fsi_clk_set_rate_external);
1690 if (fsi_is_spdif(fsi))
1691 ret = fsi_set_fmt_spdif(fsi);
1693 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1698 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1699 struct snd_pcm_hw_params *params,
1700 struct snd_soc_dai *dai)
1702 struct fsi_priv *fsi = fsi_get_priv(substream);
1704 if (fsi_is_clk_master(fsi))
1705 fsi_clk_valid(fsi, params_rate(params));
1711 * Select below from Sound Card, not auto
1712 * SND_SOC_DAIFMT_CBC_CFC
1713 * SND_SOC_DAIFMT_CBP_CFP
1715 static u64 fsi_dai_formats =
1716 SND_SOC_POSSIBLE_DAIFMT_I2S |
1717 SND_SOC_POSSIBLE_DAIFMT_LEFT_J |
1718 SND_SOC_POSSIBLE_DAIFMT_NB_NF |
1719 SND_SOC_POSSIBLE_DAIFMT_NB_IF |
1720 SND_SOC_POSSIBLE_DAIFMT_IB_NF |
1721 SND_SOC_POSSIBLE_DAIFMT_IB_IF;
1723 static const struct snd_soc_dai_ops fsi_dai_ops = {
1724 .startup = fsi_dai_startup,
1725 .shutdown = fsi_dai_shutdown,
1726 .trigger = fsi_dai_trigger,
1727 .set_fmt = fsi_dai_set_fmt,
1728 .hw_params = fsi_dai_hw_params,
1729 .auto_selectable_formats = &fsi_dai_formats,
1730 .num_auto_selectable_formats = 1,
1737 static const struct snd_pcm_hardware fsi_pcm_hardware = {
1738 .info = SNDRV_PCM_INFO_INTERLEAVED |
1739 SNDRV_PCM_INFO_MMAP |
1740 SNDRV_PCM_INFO_MMAP_VALID,
1741 .buffer_bytes_max = 64 * 1024,
1742 .period_bytes_min = 32,
1743 .period_bytes_max = 8192,
1749 static int fsi_pcm_open(struct snd_soc_component *component,
1750 struct snd_pcm_substream *substream)
1752 struct snd_pcm_runtime *runtime = substream->runtime;
1755 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1757 ret = snd_pcm_hw_constraint_integer(runtime,
1758 SNDRV_PCM_HW_PARAM_PERIODS);
1763 static snd_pcm_uframes_t fsi_pointer(struct snd_soc_component *component,
1764 struct snd_pcm_substream *substream)
1766 struct fsi_priv *fsi = fsi_get_priv(substream);
1767 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1769 return fsi_sample2frame(fsi, io->buff_sample_pos);
1776 #define PREALLOC_BUFFER (32 * 1024)
1777 #define PREALLOC_BUFFER_MAX (32 * 1024)
1779 static int fsi_pcm_new(struct snd_soc_component *component,
1780 struct snd_soc_pcm_runtime *rtd)
1782 snd_pcm_set_managed_buffer_all(
1785 rtd->card->snd_card->dev,
1786 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1794 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1799 .formats = FSI_FMTS,
1805 .formats = FSI_FMTS,
1809 .ops = &fsi_dai_ops,
1815 .formats = FSI_FMTS,
1821 .formats = FSI_FMTS,
1825 .ops = &fsi_dai_ops,
1829 static const struct snd_soc_component_driver fsi_soc_component = {
1831 .open = fsi_pcm_open,
1832 .pointer = fsi_pointer,
1833 .pcm_construct = fsi_pcm_new,
1839 static void fsi_of_parse(char *name,
1840 struct device_node *np,
1841 struct sh_fsi_port_info *info,
1846 unsigned long flags = 0;
1850 } of_parse_property[] = {
1851 { "spdif-connection", SH_FSI_FMT_SPDIF },
1852 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE },
1853 { "use-internal-clock", SH_FSI_CLK_CPG },
1856 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
1857 sprintf(prop, "%s,%s", name, of_parse_property[i].name);
1858 if (of_get_property(np, prop, NULL))
1859 flags |= of_parse_property[i].val;
1861 info->flags = flags;
1863 dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
1866 static void fsi_port_info_init(struct fsi_priv *fsi,
1867 struct sh_fsi_port_info *info)
1869 if (info->flags & SH_FSI_FMT_SPDIF)
1872 if (info->flags & SH_FSI_CLK_CPG)
1875 if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
1876 fsi->enable_stream = 1;
1879 static void fsi_handler_init(struct fsi_priv *fsi,
1880 struct sh_fsi_port_info *info)
1882 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
1883 fsi->playback.priv = fsi;
1884 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
1885 fsi->capture.priv = fsi;
1888 fsi->playback.dma_id = info->tx_id;
1889 fsi->playback.handler = &fsi_dma_push_handler;
1893 static const struct fsi_core fsi1_core = {
1902 static const struct fsi_core fsi2_core = {
1906 .int_st = CPU_INT_ST,
1909 .a_mclk = A_MST_CTLR,
1910 .b_mclk = B_MST_CTLR,
1913 static const struct of_device_id fsi_of_match[] = {
1914 { .compatible = "renesas,sh_fsi", .data = &fsi1_core},
1915 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core},
1918 MODULE_DEVICE_TABLE(of, fsi_of_match);
1920 static const struct platform_device_id fsi_id_table[] = {
1921 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1924 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1926 static int fsi_probe(struct platform_device *pdev)
1928 struct fsi_master *master;
1929 struct device_node *np = pdev->dev.of_node;
1930 struct sh_fsi_platform_info info;
1931 const struct fsi_core *core;
1932 struct fsi_priv *fsi;
1933 struct resource *res;
1937 memset(&info, 0, sizeof(info));
1941 core = of_device_get_match_data(&pdev->dev);
1942 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
1943 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
1945 const struct platform_device_id *id_entry = pdev->id_entry;
1947 core = (struct fsi_core *)id_entry->driver_data;
1949 if (pdev->dev.platform_data)
1950 memcpy(&info, pdev->dev.platform_data, sizeof(info));
1954 dev_err(&pdev->dev, "unknown fsi device\n");
1958 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1959 irq = platform_get_irq(pdev, 0);
1960 if (!res || (int)irq <= 0) {
1961 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1965 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1969 master->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1970 if (!master->base) {
1971 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1975 /* master setting */
1976 master->core = core;
1977 spin_lock_init(&master->lock);
1980 fsi = &master->fsia;
1981 fsi->base = master->base;
1982 fsi->phys = res->start;
1983 fsi->master = master;
1984 fsi_port_info_init(fsi, &info.port_a);
1985 fsi_handler_init(fsi, &info.port_a);
1986 ret = fsi_stream_probe(fsi, &pdev->dev);
1988 dev_err(&pdev->dev, "FSIA stream probe failed\n");
1993 fsi = &master->fsib;
1994 fsi->base = master->base + 0x40;
1995 fsi->phys = res->start + 0x40;
1996 fsi->master = master;
1997 fsi_port_info_init(fsi, &info.port_b);
1998 fsi_handler_init(fsi, &info.port_b);
1999 ret = fsi_stream_probe(fsi, &pdev->dev);
2001 dev_err(&pdev->dev, "FSIB stream probe failed\n");
2005 pm_runtime_enable(&pdev->dev);
2006 dev_set_drvdata(&pdev->dev, master);
2008 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
2009 dev_name(&pdev->dev), master);
2011 dev_err(&pdev->dev, "irq request err\n");
2015 ret = devm_snd_soc_register_component(&pdev->dev, &fsi_soc_component,
2016 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
2018 dev_err(&pdev->dev, "cannot snd component register\n");
2025 pm_runtime_disable(&pdev->dev);
2026 fsi_stream_remove(&master->fsib);
2028 fsi_stream_remove(&master->fsia);
2033 static int fsi_remove(struct platform_device *pdev)
2035 struct fsi_master *master;
2037 master = dev_get_drvdata(&pdev->dev);
2039 pm_runtime_disable(&pdev->dev);
2041 fsi_stream_remove(&master->fsia);
2042 fsi_stream_remove(&master->fsib);
2047 static void __fsi_suspend(struct fsi_priv *fsi,
2048 struct fsi_stream *io,
2051 if (!fsi_stream_is_working(fsi, io))
2054 fsi_stream_stop(fsi, io);
2055 fsi_hw_shutdown(fsi, dev);
2058 static void __fsi_resume(struct fsi_priv *fsi,
2059 struct fsi_stream *io,
2062 if (!fsi_stream_is_working(fsi, io))
2065 fsi_hw_startup(fsi, io, dev);
2066 fsi_stream_start(fsi, io);
2069 static int fsi_suspend(struct device *dev)
2071 struct fsi_master *master = dev_get_drvdata(dev);
2072 struct fsi_priv *fsia = &master->fsia;
2073 struct fsi_priv *fsib = &master->fsib;
2075 __fsi_suspend(fsia, &fsia->playback, dev);
2076 __fsi_suspend(fsia, &fsia->capture, dev);
2078 __fsi_suspend(fsib, &fsib->playback, dev);
2079 __fsi_suspend(fsib, &fsib->capture, dev);
2084 static int fsi_resume(struct device *dev)
2086 struct fsi_master *master = dev_get_drvdata(dev);
2087 struct fsi_priv *fsia = &master->fsia;
2088 struct fsi_priv *fsib = &master->fsib;
2090 __fsi_resume(fsia, &fsia->playback, dev);
2091 __fsi_resume(fsia, &fsia->capture, dev);
2093 __fsi_resume(fsib, &fsib->playback, dev);
2094 __fsi_resume(fsib, &fsib->capture, dev);
2099 static const struct dev_pm_ops fsi_pm_ops = {
2100 .suspend = fsi_suspend,
2101 .resume = fsi_resume,
2104 static struct platform_driver fsi_driver = {
2106 .name = "fsi-pcm-audio",
2108 .of_match_table = fsi_of_match,
2111 .remove = fsi_remove,
2112 .id_table = fsi_id_table,
2115 module_platform_driver(fsi_driver);
2117 MODULE_LICENSE("GPL v2");
2118 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
2119 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
2120 MODULE_ALIAS("platform:fsi-pcm-audio");