1 // SPDX-License-Identifier: GPL-2.0
3 // Fifo-attached Serial Interface (FSI) support for SH7724
5 // Copyright (C) 2009 Renesas Solutions Corp.
6 // Kuninori Morimoto <morimoto.kuninori@renesas.com>
9 // Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/pm_runtime.h>
16 #include <linux/scatterlist.h>
17 #include <linux/sh_dma.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/workqueue.h>
21 #include <sound/soc.h>
22 #include <sound/pcm_params.h>
23 #include <sound/sh_fsi.h>
25 /* PortA/PortB register */
26 #define REG_DO_FMT 0x0000
27 #define REG_DOFF_CTL 0x0004
28 #define REG_DOFF_ST 0x0008
29 #define REG_DI_FMT 0x000C
30 #define REG_DIFF_CTL 0x0010
31 #define REG_DIFF_ST 0x0014
32 #define REG_CKG1 0x0018
33 #define REG_CKG2 0x001C
34 #define REG_DIDT 0x0020
35 #define REG_DODT 0x0024
36 #define REG_MUTE_ST 0x0028
37 #define REG_OUT_DMAC 0x002C
38 #define REG_OUT_SEL 0x0030
39 #define REG_IN_DMAC 0x0038
42 #define MST_CLK_RST 0x0210
43 #define MST_SOFT_RST 0x0214
44 #define MST_FIFO_SZ 0x0218
46 /* core register (depend on FSI version) */
47 #define A_MST_CTLR 0x0180
48 #define B_MST_CTLR 0x01A0
49 #define CPU_INT_ST 0x01F4
50 #define CPU_IEMSK 0x01F8
51 #define CPU_IMSK 0x01FC
58 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */
59 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
60 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
61 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
63 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
64 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
65 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
67 #define CR_MONO (0x0 << 4)
68 #define CR_MONO_D (0x1 << 4)
69 #define CR_PCM (0x2 << 4)
70 #define CR_I2S (0x3 << 4)
71 #define CR_TDM (0x4 << 4)
72 #define CR_TDM_D (0x5 << 4)
76 #define VDMD_MASK (0x3 << 4)
77 #define VDMD_FRONT (0x0 << 4) /* Package in front */
78 #define VDMD_BACK (0x1 << 4) /* Package in back */
79 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
81 #define DMA_ON (0x1 << 0)
85 #define IRQ_HALF 0x00100000
86 #define FIFO_CLR 0x00000001
89 #define ERR_OVER 0x00000010
90 #define ERR_UNDER 0x00000001
91 #define ST_ERR (ERR_OVER | ERR_UNDER)
94 #define ACKMD_MASK 0x00007000
95 #define BPFMD_MASK 0x00000700
100 #define BP (1 << 4) /* Fix the signal of Biphase output */
101 #define SE (1 << 0) /* Fix the master clock */
107 /* IO SHIFT / MACRO */
112 #define AB_IO(param, shift) (param << shift)
115 #define PBSR (1 << 12) /* Port B Software Reset */
116 #define PASR (1 << 8) /* Port A Software Reset */
117 #define IR (1 << 4) /* Interrupt Reset */
118 #define FSISR (1 << 0) /* Software Reset */
121 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
122 /* 1: Biphase and serial */
125 #define FIFO_SZ_MASK 0x7
127 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
129 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
136 * A : sample widtht 16bit setting
137 * B : sample widtht 24bit setting
140 #define SHIFT_16DATA 0
141 #define SHIFT_24DATA 4
143 #define PACKAGE_24BITBUS_BACK 0
144 #define PACKAGE_24BITBUS_FRONT 1
145 #define PACKAGE_16BITBUS_STREAM 2
147 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
148 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
151 * FSI driver use below type name for variable
153 * xxx_num : number of data
154 * xxx_pos : position of data
155 * xxx_capa : capacity of data
159 * period/frame/sample image
163 * period pos period pos
165 * |<-------------------- period--------------------->|
166 * ==|============================================ ... =|==
168 * ||<----- frame ----->|<------ frame ----->| ... |
169 * |+--------------------+--------------------+- ... |
170 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
171 * |+--------------------+--------------------+- ... |
172 * ==|============================================ ... =|==
190 * FSIxCLK [CPG] (ick) -------> |
191 * |-> FSI_DIV (div)-> FSI2
192 * FSIxCK [external] (xck) ---> |
199 struct fsi_stream_handler;
203 * these are initialized by fsi_stream_init()
205 struct snd_pcm_substream *substream;
206 int fifo_sample_capa; /* sample capacity of FSI FIFO */
207 int buff_sample_capa; /* sample capacity of ALSA buffer */
208 int buff_sample_pos; /* sample position of ALSA buffer */
209 int period_samples; /* sample number / 1 period */
210 int period_pos; /* current period position */
211 int sample_width; /* sample width */
221 * these are initialized by fsi_handler_init()
223 struct fsi_stream_handler *handler;
224 struct fsi_priv *priv;
227 * these are for DMAEngine
229 struct dma_chan *chan;
234 /* see [FSI clock] */
239 int (*set_rate)(struct device *dev,
240 struct fsi_priv *fsi);
249 struct fsi_master *master;
251 struct fsi_stream playback;
252 struct fsi_stream capture;
254 struct fsi_clk clock;
259 unsigned int clk_master:1;
260 unsigned int clk_cpg:1;
261 unsigned int spdif:1;
262 unsigned int enable_stream:1;
263 unsigned int bit_clk_inv:1;
264 unsigned int lr_clk_inv:1;
267 struct fsi_stream_handler {
268 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
269 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
270 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
271 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
272 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
273 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
276 #define fsi_stream_handler_call(io, func, args...) \
278 !((io)->handler->func) ? 0 : \
279 (io)->handler->func(args))
293 struct fsi_priv fsia;
294 struct fsi_priv fsib;
295 const struct fsi_core *core;
299 static inline int fsi_stream_is_play(struct fsi_priv *fsi,
300 struct fsi_stream *io)
302 return &fsi->playback == io;
307 * basic read write function
310 static void __fsi_reg_write(u32 __iomem *reg, u32 data)
312 /* valid data area is 24bit */
315 __raw_writel(data, reg);
318 static u32 __fsi_reg_read(u32 __iomem *reg)
320 return __raw_readl(reg);
323 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
325 u32 val = __fsi_reg_read(reg);
330 __fsi_reg_write(reg, val);
333 #define fsi_reg_write(p, r, d)\
334 __fsi_reg_write((p->base + REG_##r), d)
336 #define fsi_reg_read(p, r)\
337 __fsi_reg_read((p->base + REG_##r))
339 #define fsi_reg_mask_set(p, r, m, d)\
340 __fsi_reg_mask_set((p->base + REG_##r), m, d)
342 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
343 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
344 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
349 spin_lock_irqsave(&master->lock, flags);
350 ret = __fsi_reg_read(master->base + reg);
351 spin_unlock_irqrestore(&master->lock, flags);
356 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
357 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
358 static void _fsi_master_mask_set(struct fsi_master *master,
359 u32 reg, u32 mask, u32 data)
363 spin_lock_irqsave(&master->lock, flags);
364 __fsi_reg_mask_set(master->base + reg, mask, data);
365 spin_unlock_irqrestore(&master->lock, flags);
371 static int fsi_version(struct fsi_master *master)
373 return master->core->ver;
376 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
381 static int fsi_is_clk_master(struct fsi_priv *fsi)
383 return fsi->clk_master;
386 static int fsi_is_port_a(struct fsi_priv *fsi)
388 return fsi->master->base == fsi->base;
391 static int fsi_is_spdif(struct fsi_priv *fsi)
396 static int fsi_is_enable_stream(struct fsi_priv *fsi)
398 return fsi->enable_stream;
401 static int fsi_is_play(struct snd_pcm_substream *substream)
403 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
406 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
408 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
410 return snd_soc_rtd_to_cpu(rtd, 0);
413 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
415 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
418 return &master->fsia;
420 return &master->fsib;
423 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
425 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
428 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
430 int is_play = fsi_stream_is_play(fsi, io);
431 int is_porta = fsi_is_port_a(fsi);
435 shift = is_play ? AO_SHIFT : AI_SHIFT;
437 shift = is_play ? BO_SHIFT : BI_SHIFT;
442 static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
444 return frames * fsi->chan_num;
447 static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
449 return samples / fsi->chan_num;
452 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
453 struct fsi_stream *io)
455 int is_play = fsi_stream_is_play(fsi, io);
460 fsi_reg_read(fsi, DOFF_ST) :
461 fsi_reg_read(fsi, DIFF_ST);
463 frames = 0x1ff & (status >> 8);
465 return fsi_frame2sample(fsi, frames);
468 static void fsi_count_fifo_err(struct fsi_priv *fsi)
470 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
471 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
473 if (ostatus & ERR_OVER)
474 fsi->playback.oerr_num++;
476 if (ostatus & ERR_UNDER)
477 fsi->playback.uerr_num++;
479 if (istatus & ERR_OVER)
480 fsi->capture.oerr_num++;
482 if (istatus & ERR_UNDER)
483 fsi->capture.uerr_num++;
485 fsi_reg_write(fsi, DOFF_ST, 0);
486 fsi_reg_write(fsi, DIFF_ST, 0);
490 * fsi_stream_xx() function
492 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
493 struct snd_pcm_substream *substream)
495 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
498 static int fsi_stream_is_working(struct fsi_priv *fsi,
499 struct fsi_stream *io)
501 struct fsi_master *master = fsi_get_master(fsi);
505 spin_lock_irqsave(&master->lock, flags);
506 ret = !!(io->substream && io->substream->runtime);
507 spin_unlock_irqrestore(&master->lock, flags);
512 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
517 static void fsi_stream_init(struct fsi_priv *fsi,
518 struct fsi_stream *io,
519 struct snd_pcm_substream *substream)
521 struct snd_pcm_runtime *runtime = substream->runtime;
522 struct fsi_master *master = fsi_get_master(fsi);
525 spin_lock_irqsave(&master->lock, flags);
526 io->substream = substream;
527 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
528 io->buff_sample_pos = 0;
529 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
531 io->sample_width = samples_to_bytes(runtime, 1);
533 io->oerr_num = -1; /* ignore 1st err */
534 io->uerr_num = -1; /* ignore 1st err */
535 fsi_stream_handler_call(io, init, fsi, io);
536 spin_unlock_irqrestore(&master->lock, flags);
539 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
541 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
542 struct fsi_master *master = fsi_get_master(fsi);
545 spin_lock_irqsave(&master->lock, flags);
547 if (io->oerr_num > 0)
548 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
550 if (io->uerr_num > 0)
551 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
553 fsi_stream_handler_call(io, quit, fsi, io);
554 io->substream = NULL;
555 io->buff_sample_capa = 0;
556 io->buff_sample_pos = 0;
557 io->period_samples = 0;
559 io->sample_width = 0;
563 spin_unlock_irqrestore(&master->lock, flags);
566 static int fsi_stream_transfer(struct fsi_stream *io)
568 struct fsi_priv *fsi = fsi_stream_to_priv(io);
572 return fsi_stream_handler_call(io, transfer, fsi, io);
575 #define fsi_stream_start(fsi, io)\
576 fsi_stream_handler_call(io, start_stop, fsi, io, 1)
578 #define fsi_stream_stop(fsi, io)\
579 fsi_stream_handler_call(io, start_stop, fsi, io, 0)
581 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
583 struct fsi_stream *io;
587 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
590 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
600 static int fsi_stream_remove(struct fsi_priv *fsi)
602 struct fsi_stream *io;
606 ret1 = fsi_stream_handler_call(io, remove, fsi, io);
609 ret2 = fsi_stream_handler_call(io, remove, fsi, io);
620 * format/bus/dma setting
622 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
623 u32 bus, struct device *dev)
625 struct fsi_master *master = fsi_get_master(fsi);
626 int is_play = fsi_stream_is_play(fsi, io);
629 if (fsi_version(master) >= 2) {
633 * FSI2 needs DMA/Bus setting
636 case PACKAGE_24BITBUS_FRONT:
639 dev_dbg(dev, "24bit bus / package in front\n");
641 case PACKAGE_16BITBUS_STREAM:
644 dev_dbg(dev, "16bit bus / stream mode\n");
646 case PACKAGE_24BITBUS_BACK:
650 dev_dbg(dev, "24bit bus / package in back\n");
655 fsi_reg_write(fsi, OUT_DMAC, dma);
657 fsi_reg_write(fsi, IN_DMAC, dma);
661 fsi_reg_write(fsi, DO_FMT, fmt);
663 fsi_reg_write(fsi, DI_FMT, fmt);
670 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
672 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
673 struct fsi_master *master = fsi_get_master(fsi);
675 fsi_core_mask_set(master, imsk, data, data);
676 fsi_core_mask_set(master, iemsk, data, data);
679 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
681 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
682 struct fsi_master *master = fsi_get_master(fsi);
684 fsi_core_mask_set(master, imsk, data, 0);
685 fsi_core_mask_set(master, iemsk, data, 0);
688 static u32 fsi_irq_get_status(struct fsi_master *master)
690 return fsi_core_read(master, int_st);
693 static void fsi_irq_clear_status(struct fsi_priv *fsi)
696 struct fsi_master *master = fsi_get_master(fsi);
698 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
699 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
701 /* clear interrupt factor */
702 fsi_core_mask_set(master, int_st, data, 0);
706 * SPDIF master clock function
708 * These functions are used later FSI2
710 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
712 struct fsi_master *master = fsi_get_master(fsi);
716 val = enable ? mask : 0;
719 fsi_core_mask_set(master, a_mclk, mask, val) :
720 fsi_core_mask_set(master, b_mclk, mask, val);
726 static int fsi_clk_init(struct device *dev,
727 struct fsi_priv *fsi,
731 int (*set_rate)(struct device *dev,
732 struct fsi_priv *fsi))
734 struct fsi_clk *clock = &fsi->clock;
735 int is_porta = fsi_is_port_a(fsi);
742 clock->set_rate = set_rate;
744 clock->own = devm_clk_get(dev, NULL);
745 if (IS_ERR(clock->own))
750 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
751 if (IS_ERR(clock->xck)) {
752 dev_err(dev, "can't get xck clock\n");
755 if (clock->xck == clock->own) {
756 dev_err(dev, "cpu doesn't support xck clock\n");
761 /* FSIACLK/FSIBCLK */
763 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
764 if (IS_ERR(clock->ick)) {
765 dev_err(dev, "can't get ick clock\n");
768 if (clock->ick == clock->own) {
769 dev_err(dev, "cpu doesn't support ick clock\n");
776 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
777 if (IS_ERR(clock->div)) {
778 dev_err(dev, "can't get div clock\n");
781 if (clock->div == clock->own) {
782 dev_err(dev, "cpu doesn't support div clock\n");
790 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
791 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
793 fsi->clock.rate = rate;
796 static int fsi_clk_is_valid(struct fsi_priv *fsi)
798 return fsi->clock.set_rate &&
802 static int fsi_clk_enable(struct device *dev,
803 struct fsi_priv *fsi)
805 struct fsi_clk *clock = &fsi->clock;
808 if (!fsi_clk_is_valid(fsi))
811 if (0 == clock->count) {
812 ret = clock->set_rate(dev, fsi);
814 fsi_clk_invalid(fsi);
818 ret = clk_enable(clock->xck);
821 ret = clk_enable(clock->ick);
824 ret = clk_enable(clock->div);
834 clk_disable(clock->ick);
836 clk_disable(clock->xck);
841 static int fsi_clk_disable(struct device *dev,
842 struct fsi_priv *fsi)
844 struct fsi_clk *clock = &fsi->clock;
846 if (!fsi_clk_is_valid(fsi))
849 if (1 == clock->count--) {
850 clk_disable(clock->xck);
851 clk_disable(clock->ick);
852 clk_disable(clock->div);
858 static int fsi_clk_set_ackbpf(struct device *dev,
859 struct fsi_priv *fsi,
860 int ackmd, int bpfmd)
864 /* check ackmd/bpfmd relationship */
866 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
888 dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
913 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
917 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
919 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
925 static int fsi_clk_set_rate_external(struct device *dev,
926 struct fsi_priv *fsi)
928 struct clk *xck = fsi->clock.xck;
929 struct clk *ick = fsi->clock.ick;
930 unsigned long rate = fsi->clock.rate;
935 /* check clock rate */
936 xrate = clk_get_rate(xck);
938 dev_err(dev, "unsupported clock rate\n");
942 clk_set_parent(ick, xck);
943 clk_set_rate(ick, xrate);
945 bpfmd = fsi->chan_num * 32;
946 ackmd = xrate / rate;
948 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
950 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
952 dev_err(dev, "%s failed", __func__);
957 static int fsi_clk_set_rate_cpg(struct device *dev,
958 struct fsi_priv *fsi)
960 struct clk *ick = fsi->clock.ick;
961 struct clk *div = fsi->clock.div;
962 unsigned long rate = fsi->clock.rate;
963 unsigned long target = 0; /* 12288000 or 11289600 */
964 unsigned long actual, cout;
965 unsigned long diff, min;
966 unsigned long best_cout, best_act;
971 if (!(12288000 % rate))
973 if (!(11289600 % rate))
976 dev_err(dev, "unsupported rate\n");
980 bpfmd = fsi->chan_num * 32;
981 ackmd = target / rate;
982 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
984 dev_err(dev, "%s failed", __func__);
991 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
993 * But, it needs to find best match of CPG and FSI_DIV
994 * combination, since it is difficult to generate correct
995 * frequency of audio clock from ick clock only.
996 * Because ick is created from its parent clock.
998 * target = rate x [512/256/128/64]fs
999 * cout = round(target x adjustment)
1000 * actual = cout / adjustment (by FSI-DIV) ~= target
1006 for (adj = 1; adj < 0xffff; adj++) {
1008 cout = target * adj;
1009 if (cout > 100000000) /* max clock = 100MHz */
1012 /* cout/actual audio clock */
1013 cout = clk_round_rate(ick, cout);
1014 actual = cout / adj;
1016 /* find best frequency */
1017 diff = abs(actual - target);
1025 ret = clk_set_rate(ick, best_cout);
1027 dev_err(dev, "ick clock failed\n");
1031 ret = clk_set_rate(div, clk_round_rate(div, best_act));
1033 dev_err(dev, "div clock failed\n");
1037 dev_dbg(dev, "ick/div = %ld/%ld\n",
1038 clk_get_rate(ick), clk_get_rate(div));
1043 static void fsi_pointer_update(struct fsi_stream *io, int size)
1045 io->buff_sample_pos += size;
1047 if (io->buff_sample_pos >=
1048 io->period_samples * (io->period_pos + 1)) {
1049 struct snd_pcm_substream *substream = io->substream;
1050 struct snd_pcm_runtime *runtime = substream->runtime;
1054 if (io->period_pos >= runtime->periods) {
1055 io->buff_sample_pos = 0;
1059 snd_pcm_period_elapsed(substream);
1064 * pio data transfer handler
1066 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
1070 if (fsi_is_enable_stream(fsi)) {
1074 * fsi_pio_push_init()
1076 u32 *buf = (u32 *)_buf;
1078 for (i = 0; i < samples / 2; i++)
1079 fsi_reg_write(fsi, DODT, buf[i]);
1082 u16 *buf = (u16 *)_buf;
1084 for (i = 0; i < samples; i++)
1085 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
1089 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
1091 u16 *buf = (u16 *)_buf;
1094 for (i = 0; i < samples; i++)
1095 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
1098 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
1100 u32 *buf = (u32 *)_buf;
1103 for (i = 0; i < samples; i++)
1104 fsi_reg_write(fsi, DODT, *(buf + i));
1107 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
1109 u32 *buf = (u32 *)_buf;
1112 for (i = 0; i < samples; i++)
1113 *(buf + i) = fsi_reg_read(fsi, DIDT);
1116 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
1118 struct snd_pcm_runtime *runtime = io->substream->runtime;
1120 return runtime->dma_area +
1121 samples_to_bytes(runtime, io->buff_sample_pos);
1124 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
1125 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
1126 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
1131 if (!fsi_stream_is_working(fsi, io))
1134 buf = fsi_pio_get_area(fsi, io);
1136 switch (io->sample_width) {
1138 run16(fsi, buf, samples);
1141 run32(fsi, buf, samples);
1147 fsi_pointer_update(io, samples);
1152 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
1154 int sample_residues; /* samples in FSI fifo */
1155 int sample_space; /* ALSA free samples space */
1158 sample_residues = fsi_get_current_fifo_samples(fsi, io);
1159 sample_space = io->buff_sample_capa - io->buff_sample_pos;
1161 samples = min(sample_residues, sample_space);
1163 return fsi_pio_transfer(fsi, io,
1169 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
1171 int sample_residues; /* ALSA residue samples */
1172 int sample_space; /* FSI fifo free samples space */
1175 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
1176 sample_space = io->fifo_sample_capa -
1177 fsi_get_current_fifo_samples(fsi, io);
1179 samples = min(sample_residues, sample_space);
1181 return fsi_pio_transfer(fsi, io,
1187 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1190 struct fsi_master *master = fsi_get_master(fsi);
1191 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1194 fsi_irq_enable(fsi, io);
1196 fsi_irq_disable(fsi, io);
1198 if (fsi_is_clk_master(fsi))
1199 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1204 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
1207 * we can use 16bit stream mode
1208 * when "playback" and "16bit data"
1209 * and platform allows "stream mode"
1213 if (fsi_is_enable_stream(fsi))
1214 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1215 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1217 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1218 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1222 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
1225 * always 24bit bus, package back when "capture"
1227 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1228 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1232 static struct fsi_stream_handler fsi_pio_push_handler = {
1233 .init = fsi_pio_push_init,
1234 .transfer = fsi_pio_push,
1235 .start_stop = fsi_pio_start_stop,
1238 static struct fsi_stream_handler fsi_pio_pop_handler = {
1239 .init = fsi_pio_pop_init,
1240 .transfer = fsi_pio_pop,
1241 .start_stop = fsi_pio_start_stop,
1244 static irqreturn_t fsi_interrupt(int irq, void *data)
1246 struct fsi_master *master = data;
1247 u32 int_st = fsi_irq_get_status(master);
1249 /* clear irq status */
1250 fsi_master_mask_set(master, SOFT_RST, IR, 0);
1251 fsi_master_mask_set(master, SOFT_RST, IR, IR);
1253 if (int_st & AB_IO(1, AO_SHIFT))
1254 fsi_stream_transfer(&master->fsia.playback);
1255 if (int_st & AB_IO(1, BO_SHIFT))
1256 fsi_stream_transfer(&master->fsib.playback);
1257 if (int_st & AB_IO(1, AI_SHIFT))
1258 fsi_stream_transfer(&master->fsia.capture);
1259 if (int_st & AB_IO(1, BI_SHIFT))
1260 fsi_stream_transfer(&master->fsib.capture);
1262 fsi_count_fifo_err(&master->fsia);
1263 fsi_count_fifo_err(&master->fsib);
1265 fsi_irq_clear_status(&master->fsia);
1266 fsi_irq_clear_status(&master->fsib);
1272 * dma data transfer handler
1274 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
1277 * 24bit data : 24bit bus / package in back
1278 * 16bit data : 16bit bus / stream mode
1280 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1281 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1286 static void fsi_dma_complete(void *data)
1288 struct fsi_stream *io = (struct fsi_stream *)data;
1289 struct fsi_priv *fsi = fsi_stream_to_priv(io);
1291 fsi_pointer_update(io, io->period_samples);
1293 fsi_count_fifo_err(fsi);
1296 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
1298 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
1299 struct snd_pcm_substream *substream = io->substream;
1300 struct dma_async_tx_descriptor *desc;
1301 int is_play = fsi_stream_is_play(fsi, io);
1302 enum dma_transfer_direction dir;
1306 dir = DMA_MEM_TO_DEV;
1308 dir = DMA_DEV_TO_MEM;
1310 desc = dmaengine_prep_dma_cyclic(io->chan,
1311 substream->runtime->dma_addr,
1312 snd_pcm_lib_buffer_bytes(substream),
1313 snd_pcm_lib_period_bytes(substream),
1315 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1317 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n");
1318 goto fsi_dma_transfer_err;
1321 desc->callback = fsi_dma_complete;
1322 desc->callback_param = io;
1324 if (dmaengine_submit(desc) < 0) {
1325 dev_err(dai->dev, "tx_submit() fail\n");
1326 goto fsi_dma_transfer_err;
1329 dma_async_issue_pending(io->chan);
1334 * In DMAEngine case, codec and FSI cannot be started simultaneously
1335 * since FSI is using the scheduler work queue.
1336 * Therefore, in capture case, probably FSI FIFO will have got
1337 * overflow error in this point.
1338 * in that case, DMA cannot start transfer until error was cleared.
1341 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
1342 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1343 fsi_reg_write(fsi, DIFF_ST, 0);
1349 fsi_dma_transfer_err:
1353 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1356 struct fsi_master *master = fsi_get_master(fsi);
1357 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1358 u32 enable = start ? DMA_ON : 0;
1360 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
1362 dmaengine_terminate_all(io->chan);
1364 if (fsi_is_clk_master(fsi))
1365 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1370 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
1372 int is_play = fsi_stream_is_play(fsi, io);
1374 #ifdef CONFIG_SUPERH
1375 dma_cap_mask_t mask;
1377 dma_cap_set(DMA_SLAVE, mask);
1379 io->chan = dma_request_channel(mask, shdma_chan_filter,
1380 (void *)io->dma_id);
1382 io->chan = dma_request_slave_channel(dev, is_play ? "tx" : "rx");
1385 struct dma_slave_config cfg = {};
1389 cfg.dst_addr = fsi->phys + REG_DODT;
1390 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1391 cfg.direction = DMA_MEM_TO_DEV;
1393 cfg.src_addr = fsi->phys + REG_DIDT;
1394 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1395 cfg.direction = DMA_DEV_TO_MEM;
1398 ret = dmaengine_slave_config(io->chan, &cfg);
1400 dma_release_channel(io->chan);
1407 /* switch to PIO handler */
1409 fsi->playback.handler = &fsi_pio_push_handler;
1411 fsi->capture.handler = &fsi_pio_pop_handler;
1413 dev_info(dev, "switch handler (dma => pio)\n");
1416 return fsi_stream_probe(fsi, dev);
1422 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
1424 fsi_stream_stop(fsi, io);
1427 dma_release_channel(io->chan);
1433 static struct fsi_stream_handler fsi_dma_push_handler = {
1434 .init = fsi_dma_init,
1435 .probe = fsi_dma_probe,
1436 .transfer = fsi_dma_transfer,
1437 .remove = fsi_dma_remove,
1438 .start_stop = fsi_dma_push_start_stop,
1444 static void fsi_fifo_init(struct fsi_priv *fsi,
1445 struct fsi_stream *io,
1448 struct fsi_master *master = fsi_get_master(fsi);
1449 int is_play = fsi_stream_is_play(fsi, io);
1453 /* get on-chip RAM capacity */
1454 shift = fsi_master_read(master, FIFO_SZ);
1455 shift >>= fsi_get_port_shift(fsi, io);
1456 shift &= FIFO_SZ_MASK;
1457 frame_capa = 256 << shift;
1458 dev_dbg(dev, "fifo = %d words\n", frame_capa);
1461 * The maximum number of sample data varies depending
1462 * on the number of channels selected for the format.
1464 * FIFOs are used in 4-channel units in 3-channel mode
1465 * and in 8-channel units in 5- to 7-channel mode
1466 * meaning that more FIFOs than the required size of DPRAM
1469 * ex) if 256 words of DP-RAM is connected
1470 * 1 channel: 256 (256 x 1 = 256)
1471 * 2 channels: 128 (128 x 2 = 256)
1472 * 3 channels: 64 ( 64 x 3 = 192)
1473 * 4 channels: 64 ( 64 x 4 = 256)
1474 * 5 channels: 32 ( 32 x 5 = 160)
1475 * 6 channels: 32 ( 32 x 6 = 192)
1476 * 7 channels: 32 ( 32 x 7 = 224)
1477 * 8 channels: 32 ( 32 x 8 = 256)
1479 for (i = 1; i < fsi->chan_num; i <<= 1)
1481 dev_dbg(dev, "%d channel %d store\n",
1482 fsi->chan_num, frame_capa);
1484 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
1487 * set interrupt generation factor
1491 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
1492 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
1494 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
1495 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1499 static int fsi_hw_startup(struct fsi_priv *fsi,
1500 struct fsi_stream *io,
1506 if (fsi_is_clk_master(fsi))
1509 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
1511 /* clock inversion (CKG2) */
1513 if (fsi->bit_clk_inv)
1515 if (fsi->lr_clk_inv)
1517 if (fsi_is_clk_master(fsi))
1519 fsi_reg_write(fsi, CKG2, data);
1522 if (fsi_is_spdif(fsi)) {
1523 fsi_spdif_clk_ctrl(fsi, 1);
1524 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
1531 switch (io->sample_width) {
1533 data = BUSOP_GET(16, io->bus_option);
1536 data = BUSOP_GET(24, io->bus_option);
1539 fsi_format_bus_setup(fsi, io, data, dev);
1542 fsi_irq_disable(fsi, io);
1543 fsi_irq_clear_status(fsi);
1546 fsi_fifo_init(fsi, io, dev);
1548 /* start master clock */
1549 if (fsi_is_clk_master(fsi))
1550 return fsi_clk_enable(dev, fsi);
1555 static int fsi_hw_shutdown(struct fsi_priv *fsi,
1558 /* stop master clock */
1559 if (fsi_is_clk_master(fsi))
1560 return fsi_clk_disable(dev, fsi);
1565 static int fsi_dai_startup(struct snd_pcm_substream *substream,
1566 struct snd_soc_dai *dai)
1568 struct fsi_priv *fsi = fsi_get_priv(substream);
1570 fsi_clk_invalid(fsi);
1575 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
1576 struct snd_soc_dai *dai)
1578 struct fsi_priv *fsi = fsi_get_priv(substream);
1580 fsi_clk_invalid(fsi);
1583 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
1584 struct snd_soc_dai *dai)
1586 struct fsi_priv *fsi = fsi_get_priv(substream);
1587 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1591 case SNDRV_PCM_TRIGGER_START:
1592 fsi_stream_init(fsi, io, substream);
1594 ret = fsi_hw_startup(fsi, io, dai->dev);
1596 ret = fsi_stream_start(fsi, io);
1598 ret = fsi_stream_transfer(io);
1600 case SNDRV_PCM_TRIGGER_STOP:
1602 ret = fsi_hw_shutdown(fsi, dai->dev);
1603 fsi_stream_stop(fsi, io);
1604 fsi_stream_quit(fsi, io);
1611 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
1613 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1614 case SND_SOC_DAIFMT_I2S:
1618 case SND_SOC_DAIFMT_LEFT_J:
1629 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1631 struct fsi_master *master = fsi_get_master(fsi);
1633 if (fsi_version(master) < 2)
1636 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
1642 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1644 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1647 /* set clock master audio interface */
1648 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1649 case SND_SOC_DAIFMT_BC_FC:
1651 case SND_SOC_DAIFMT_BP_FP:
1652 fsi->clk_master = 1; /* cpu is master */
1658 /* set clock inversion */
1659 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1660 case SND_SOC_DAIFMT_NB_IF:
1661 fsi->bit_clk_inv = 0;
1662 fsi->lr_clk_inv = 1;
1664 case SND_SOC_DAIFMT_IB_NF:
1665 fsi->bit_clk_inv = 1;
1666 fsi->lr_clk_inv = 0;
1668 case SND_SOC_DAIFMT_IB_IF:
1669 fsi->bit_clk_inv = 1;
1670 fsi->lr_clk_inv = 1;
1672 case SND_SOC_DAIFMT_NB_NF:
1674 fsi->bit_clk_inv = 0;
1675 fsi->lr_clk_inv = 0;
1679 if (fsi_is_clk_master(fsi)) {
1681 fsi_clk_init(dai->dev, fsi, 0, 1, 1,
1682 fsi_clk_set_rate_cpg);
1684 fsi_clk_init(dai->dev, fsi, 1, 1, 0,
1685 fsi_clk_set_rate_external);
1689 if (fsi_is_spdif(fsi))
1690 ret = fsi_set_fmt_spdif(fsi);
1692 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1697 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1698 struct snd_pcm_hw_params *params,
1699 struct snd_soc_dai *dai)
1701 struct fsi_priv *fsi = fsi_get_priv(substream);
1703 if (fsi_is_clk_master(fsi))
1704 fsi_clk_valid(fsi, params_rate(params));
1710 * Select below from Sound Card, not auto
1711 * SND_SOC_DAIFMT_CBC_CFC
1712 * SND_SOC_DAIFMT_CBP_CFP
1714 static u64 fsi_dai_formats =
1715 SND_SOC_POSSIBLE_DAIFMT_I2S |
1716 SND_SOC_POSSIBLE_DAIFMT_LEFT_J |
1717 SND_SOC_POSSIBLE_DAIFMT_NB_NF |
1718 SND_SOC_POSSIBLE_DAIFMT_NB_IF |
1719 SND_SOC_POSSIBLE_DAIFMT_IB_NF |
1720 SND_SOC_POSSIBLE_DAIFMT_IB_IF;
1722 static const struct snd_soc_dai_ops fsi_dai_ops = {
1723 .startup = fsi_dai_startup,
1724 .shutdown = fsi_dai_shutdown,
1725 .trigger = fsi_dai_trigger,
1726 .set_fmt = fsi_dai_set_fmt,
1727 .hw_params = fsi_dai_hw_params,
1728 .auto_selectable_formats = &fsi_dai_formats,
1729 .num_auto_selectable_formats = 1,
1736 static const struct snd_pcm_hardware fsi_pcm_hardware = {
1737 .info = SNDRV_PCM_INFO_INTERLEAVED |
1738 SNDRV_PCM_INFO_MMAP |
1739 SNDRV_PCM_INFO_MMAP_VALID,
1740 .buffer_bytes_max = 64 * 1024,
1741 .period_bytes_min = 32,
1742 .period_bytes_max = 8192,
1748 static int fsi_pcm_open(struct snd_soc_component *component,
1749 struct snd_pcm_substream *substream)
1751 struct snd_pcm_runtime *runtime = substream->runtime;
1754 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1756 ret = snd_pcm_hw_constraint_integer(runtime,
1757 SNDRV_PCM_HW_PARAM_PERIODS);
1762 static snd_pcm_uframes_t fsi_pointer(struct snd_soc_component *component,
1763 struct snd_pcm_substream *substream)
1765 struct fsi_priv *fsi = fsi_get_priv(substream);
1766 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1768 return fsi_sample2frame(fsi, io->buff_sample_pos);
1775 #define PREALLOC_BUFFER (32 * 1024)
1776 #define PREALLOC_BUFFER_MAX (32 * 1024)
1778 static int fsi_pcm_new(struct snd_soc_component *component,
1779 struct snd_soc_pcm_runtime *rtd)
1781 snd_pcm_set_managed_buffer_all(
1784 rtd->card->snd_card->dev,
1785 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1793 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1798 .formats = FSI_FMTS,
1804 .formats = FSI_FMTS,
1808 .ops = &fsi_dai_ops,
1814 .formats = FSI_FMTS,
1820 .formats = FSI_FMTS,
1824 .ops = &fsi_dai_ops,
1828 static const struct snd_soc_component_driver fsi_soc_component = {
1830 .open = fsi_pcm_open,
1831 .pointer = fsi_pointer,
1832 .pcm_construct = fsi_pcm_new,
1838 static void fsi_of_parse(char *name,
1839 struct device_node *np,
1840 struct sh_fsi_port_info *info,
1845 unsigned long flags = 0;
1849 } of_parse_property[] = {
1850 { "spdif-connection", SH_FSI_FMT_SPDIF },
1851 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE },
1852 { "use-internal-clock", SH_FSI_CLK_CPG },
1855 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
1856 sprintf(prop, "%s,%s", name, of_parse_property[i].name);
1857 if (of_property_present(np, prop))
1858 flags |= of_parse_property[i].val;
1860 info->flags = flags;
1862 dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
1865 static void fsi_port_info_init(struct fsi_priv *fsi,
1866 struct sh_fsi_port_info *info)
1868 if (info->flags & SH_FSI_FMT_SPDIF)
1871 if (info->flags & SH_FSI_CLK_CPG)
1874 if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
1875 fsi->enable_stream = 1;
1878 static void fsi_handler_init(struct fsi_priv *fsi,
1879 struct sh_fsi_port_info *info)
1881 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
1882 fsi->playback.priv = fsi;
1883 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
1884 fsi->capture.priv = fsi;
1887 fsi->playback.dma_id = info->tx_id;
1888 fsi->playback.handler = &fsi_dma_push_handler;
1892 static const struct fsi_core fsi1_core = {
1901 static const struct fsi_core fsi2_core = {
1905 .int_st = CPU_INT_ST,
1908 .a_mclk = A_MST_CTLR,
1909 .b_mclk = B_MST_CTLR,
1912 static const struct of_device_id fsi_of_match[] = {
1913 { .compatible = "renesas,sh_fsi", .data = &fsi1_core},
1914 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core},
1917 MODULE_DEVICE_TABLE(of, fsi_of_match);
1919 static const struct platform_device_id fsi_id_table[] = {
1920 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1923 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1925 static int fsi_probe(struct platform_device *pdev)
1927 struct fsi_master *master;
1928 struct device_node *np = pdev->dev.of_node;
1929 struct sh_fsi_platform_info info;
1930 const struct fsi_core *core;
1931 struct fsi_priv *fsi;
1932 struct resource *res;
1936 memset(&info, 0, sizeof(info));
1940 core = of_device_get_match_data(&pdev->dev);
1941 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
1942 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
1944 const struct platform_device_id *id_entry = pdev->id_entry;
1946 core = (struct fsi_core *)id_entry->driver_data;
1948 if (pdev->dev.platform_data)
1949 memcpy(&info, pdev->dev.platform_data, sizeof(info));
1953 dev_err(&pdev->dev, "unknown fsi device\n");
1957 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1958 irq = platform_get_irq(pdev, 0);
1959 if (!res || (int)irq <= 0) {
1960 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1964 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1968 master->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1969 if (!master->base) {
1970 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1974 /* master setting */
1975 master->core = core;
1976 spin_lock_init(&master->lock);
1979 fsi = &master->fsia;
1980 fsi->base = master->base;
1981 fsi->phys = res->start;
1982 fsi->master = master;
1983 fsi_port_info_init(fsi, &info.port_a);
1984 fsi_handler_init(fsi, &info.port_a);
1985 ret = fsi_stream_probe(fsi, &pdev->dev);
1987 dev_err(&pdev->dev, "FSIA stream probe failed\n");
1992 fsi = &master->fsib;
1993 fsi->base = master->base + 0x40;
1994 fsi->phys = res->start + 0x40;
1995 fsi->master = master;
1996 fsi_port_info_init(fsi, &info.port_b);
1997 fsi_handler_init(fsi, &info.port_b);
1998 ret = fsi_stream_probe(fsi, &pdev->dev);
2000 dev_err(&pdev->dev, "FSIB stream probe failed\n");
2004 pm_runtime_enable(&pdev->dev);
2005 dev_set_drvdata(&pdev->dev, master);
2007 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
2008 dev_name(&pdev->dev), master);
2010 dev_err(&pdev->dev, "irq request err\n");
2014 ret = devm_snd_soc_register_component(&pdev->dev, &fsi_soc_component,
2015 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
2017 dev_err(&pdev->dev, "cannot snd component register\n");
2024 pm_runtime_disable(&pdev->dev);
2025 fsi_stream_remove(&master->fsib);
2027 fsi_stream_remove(&master->fsia);
2032 static void fsi_remove(struct platform_device *pdev)
2034 struct fsi_master *master;
2036 master = dev_get_drvdata(&pdev->dev);
2038 pm_runtime_disable(&pdev->dev);
2040 fsi_stream_remove(&master->fsia);
2041 fsi_stream_remove(&master->fsib);
2044 static void __fsi_suspend(struct fsi_priv *fsi,
2045 struct fsi_stream *io,
2048 if (!fsi_stream_is_working(fsi, io))
2051 fsi_stream_stop(fsi, io);
2052 fsi_hw_shutdown(fsi, dev);
2055 static void __fsi_resume(struct fsi_priv *fsi,
2056 struct fsi_stream *io,
2059 if (!fsi_stream_is_working(fsi, io))
2062 fsi_hw_startup(fsi, io, dev);
2063 fsi_stream_start(fsi, io);
2066 static int fsi_suspend(struct device *dev)
2068 struct fsi_master *master = dev_get_drvdata(dev);
2069 struct fsi_priv *fsia = &master->fsia;
2070 struct fsi_priv *fsib = &master->fsib;
2072 __fsi_suspend(fsia, &fsia->playback, dev);
2073 __fsi_suspend(fsia, &fsia->capture, dev);
2075 __fsi_suspend(fsib, &fsib->playback, dev);
2076 __fsi_suspend(fsib, &fsib->capture, dev);
2081 static int fsi_resume(struct device *dev)
2083 struct fsi_master *master = dev_get_drvdata(dev);
2084 struct fsi_priv *fsia = &master->fsia;
2085 struct fsi_priv *fsib = &master->fsib;
2087 __fsi_resume(fsia, &fsia->playback, dev);
2088 __fsi_resume(fsia, &fsia->capture, dev);
2090 __fsi_resume(fsib, &fsib->playback, dev);
2091 __fsi_resume(fsib, &fsib->capture, dev);
2096 static const struct dev_pm_ops fsi_pm_ops = {
2097 .suspend = fsi_suspend,
2098 .resume = fsi_resume,
2101 static struct platform_driver fsi_driver = {
2103 .name = "fsi-pcm-audio",
2105 .of_match_table = fsi_of_match,
2108 .remove_new = fsi_remove,
2109 .id_table = fsi_id_table,
2112 module_platform_driver(fsi_driver);
2114 MODULE_LICENSE("GPL v2");
2115 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
2116 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
2117 MODULE_ALIAS("platform:fsi-pcm-audio");