2 * Fifo-attached Serial Interface (FSI) support for SH7724
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/pm_runtime.h>
20 #include <linux/of_device.h>
21 #include <linux/scatterlist.h>
22 #include <linux/sh_dma.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/workqueue.h>
26 #include <sound/soc.h>
27 #include <sound/pcm_params.h>
28 #include <sound/sh_fsi.h>
30 /* PortA/PortB register */
31 #define REG_DO_FMT 0x0000
32 #define REG_DOFF_CTL 0x0004
33 #define REG_DOFF_ST 0x0008
34 #define REG_DI_FMT 0x000C
35 #define REG_DIFF_CTL 0x0010
36 #define REG_DIFF_ST 0x0014
37 #define REG_CKG1 0x0018
38 #define REG_CKG2 0x001C
39 #define REG_DIDT 0x0020
40 #define REG_DODT 0x0024
41 #define REG_MUTE_ST 0x0028
42 #define REG_OUT_DMAC 0x002C
43 #define REG_OUT_SEL 0x0030
44 #define REG_IN_DMAC 0x0038
47 #define MST_CLK_RST 0x0210
48 #define MST_SOFT_RST 0x0214
49 #define MST_FIFO_SZ 0x0218
51 /* core register (depend on FSI version) */
52 #define A_MST_CTLR 0x0180
53 #define B_MST_CTLR 0x01A0
54 #define CPU_INT_ST 0x01F4
55 #define CPU_IEMSK 0x01F8
56 #define CPU_IMSK 0x01FC
63 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */
64 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
65 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
66 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
68 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
69 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
70 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
72 #define CR_MONO (0x0 << 4)
73 #define CR_MONO_D (0x1 << 4)
74 #define CR_PCM (0x2 << 4)
75 #define CR_I2S (0x3 << 4)
76 #define CR_TDM (0x4 << 4)
77 #define CR_TDM_D (0x5 << 4)
81 #define VDMD_MASK (0x3 << 4)
82 #define VDMD_FRONT (0x0 << 4) /* Package in front */
83 #define VDMD_BACK (0x1 << 4) /* Package in back */
84 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
86 #define DMA_ON (0x1 << 0)
90 #define IRQ_HALF 0x00100000
91 #define FIFO_CLR 0x00000001
94 #define ERR_OVER 0x00000010
95 #define ERR_UNDER 0x00000001
96 #define ST_ERR (ERR_OVER | ERR_UNDER)
99 #define ACKMD_MASK 0x00007000
100 #define BPFMD_MASK 0x00000700
101 #define DIMD (1 << 4)
102 #define DOMD (1 << 0)
105 #define BP (1 << 4) /* Fix the signal of Biphase output */
106 #define SE (1 << 0) /* Fix the master clock */
112 /* IO SHIFT / MACRO */
117 #define AB_IO(param, shift) (param << shift)
120 #define PBSR (1 << 12) /* Port B Software Reset */
121 #define PASR (1 << 8) /* Port A Software Reset */
122 #define IR (1 << 4) /* Interrupt Reset */
123 #define FSISR (1 << 0) /* Software Reset */
126 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
127 /* 1: Biphase and serial */
130 #define FIFO_SZ_MASK 0x7
132 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
134 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
141 * A : sample widtht 16bit setting
142 * B : sample widtht 24bit setting
145 #define SHIFT_16DATA 0
146 #define SHIFT_24DATA 4
148 #define PACKAGE_24BITBUS_BACK 0
149 #define PACKAGE_24BITBUS_FRONT 1
150 #define PACKAGE_16BITBUS_STREAM 2
152 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
153 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
156 * FSI driver use below type name for variable
158 * xxx_num : number of data
159 * xxx_pos : position of data
160 * xxx_capa : capacity of data
164 * period/frame/sample image
168 * period pos period pos
170 * |<-------------------- period--------------------->|
171 * ==|============================================ ... =|==
173 * ||<----- frame ----->|<------ frame ----->| ... |
174 * |+--------------------+--------------------+- ... |
175 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
176 * |+--------------------+--------------------+- ... |
177 * ==|============================================ ... =|==
195 * FSIxCLK [CPG] (ick) -------> |
196 * |-> FSI_DIV (div)-> FSI2
197 * FSIxCK [external] (xck) ---> |
204 struct fsi_stream_handler;
208 * these are initialized by fsi_stream_init()
210 struct snd_pcm_substream *substream;
211 int fifo_sample_capa; /* sample capacity of FSI FIFO */
212 int buff_sample_capa; /* sample capacity of ALSA buffer */
213 int buff_sample_pos; /* sample position of ALSA buffer */
214 int period_samples; /* sample number / 1 period */
215 int period_pos; /* current period position */
216 int sample_width; /* sample width */
226 * thse are initialized by fsi_handler_init()
228 struct fsi_stream_handler *handler;
229 struct fsi_priv *priv;
232 * these are for DMAEngine
234 struct dma_chan *chan;
239 /* see [FSI clock] */
244 int (*set_rate)(struct device *dev,
245 struct fsi_priv *fsi);
254 struct fsi_master *master;
256 struct fsi_stream playback;
257 struct fsi_stream capture;
259 struct fsi_clk clock;
264 unsigned int clk_master:1;
265 unsigned int clk_cpg:1;
266 unsigned int spdif:1;
267 unsigned int enable_stream:1;
268 unsigned int bit_clk_inv:1;
269 unsigned int lr_clk_inv:1;
272 struct fsi_stream_handler {
273 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
274 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
275 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
276 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
277 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
278 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
281 #define fsi_stream_handler_call(io, func, args...) \
283 !((io)->handler->func) ? 0 : \
284 (io)->handler->func(args))
298 struct fsi_priv fsia;
299 struct fsi_priv fsib;
300 const struct fsi_core *core;
304 static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
307 * basic read write function
310 static void __fsi_reg_write(u32 __iomem *reg, u32 data)
312 /* valid data area is 24bit */
315 __raw_writel(data, reg);
318 static u32 __fsi_reg_read(u32 __iomem *reg)
320 return __raw_readl(reg);
323 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
325 u32 val = __fsi_reg_read(reg);
330 __fsi_reg_write(reg, val);
333 #define fsi_reg_write(p, r, d)\
334 __fsi_reg_write((p->base + REG_##r), d)
336 #define fsi_reg_read(p, r)\
337 __fsi_reg_read((p->base + REG_##r))
339 #define fsi_reg_mask_set(p, r, m, d)\
340 __fsi_reg_mask_set((p->base + REG_##r), m, d)
342 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
343 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
344 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
349 spin_lock_irqsave(&master->lock, flags);
350 ret = __fsi_reg_read(master->base + reg);
351 spin_unlock_irqrestore(&master->lock, flags);
356 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
357 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
358 static void _fsi_master_mask_set(struct fsi_master *master,
359 u32 reg, u32 mask, u32 data)
363 spin_lock_irqsave(&master->lock, flags);
364 __fsi_reg_mask_set(master->base + reg, mask, data);
365 spin_unlock_irqrestore(&master->lock, flags);
371 static int fsi_version(struct fsi_master *master)
373 return master->core->ver;
376 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
381 static int fsi_is_clk_master(struct fsi_priv *fsi)
383 return fsi->clk_master;
386 static int fsi_is_port_a(struct fsi_priv *fsi)
388 return fsi->master->base == fsi->base;
391 static int fsi_is_spdif(struct fsi_priv *fsi)
396 static int fsi_is_enable_stream(struct fsi_priv *fsi)
398 return fsi->enable_stream;
401 static int fsi_is_play(struct snd_pcm_substream *substream)
403 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
406 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
408 struct snd_soc_pcm_runtime *rtd = substream->private_data;
413 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
415 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
418 return &master->fsia;
420 return &master->fsib;
423 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
425 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
428 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
430 int is_play = fsi_stream_is_play(fsi, io);
431 int is_porta = fsi_is_port_a(fsi);
435 shift = is_play ? AO_SHIFT : AI_SHIFT;
437 shift = is_play ? BO_SHIFT : BI_SHIFT;
442 static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
444 return frames * fsi->chan_num;
447 static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
449 return samples / fsi->chan_num;
452 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
453 struct fsi_stream *io)
455 int is_play = fsi_stream_is_play(fsi, io);
460 fsi_reg_read(fsi, DOFF_ST) :
461 fsi_reg_read(fsi, DIFF_ST);
463 frames = 0x1ff & (status >> 8);
465 return fsi_frame2sample(fsi, frames);
468 static void fsi_count_fifo_err(struct fsi_priv *fsi)
470 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
471 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
473 if (ostatus & ERR_OVER)
474 fsi->playback.oerr_num++;
476 if (ostatus & ERR_UNDER)
477 fsi->playback.uerr_num++;
479 if (istatus & ERR_OVER)
480 fsi->capture.oerr_num++;
482 if (istatus & ERR_UNDER)
483 fsi->capture.uerr_num++;
485 fsi_reg_write(fsi, DOFF_ST, 0);
486 fsi_reg_write(fsi, DIFF_ST, 0);
490 * fsi_stream_xx() function
492 static inline int fsi_stream_is_play(struct fsi_priv *fsi,
493 struct fsi_stream *io)
495 return &fsi->playback == io;
498 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
499 struct snd_pcm_substream *substream)
501 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
504 static int fsi_stream_is_working(struct fsi_priv *fsi,
505 struct fsi_stream *io)
507 struct fsi_master *master = fsi_get_master(fsi);
511 spin_lock_irqsave(&master->lock, flags);
512 ret = !!(io->substream && io->substream->runtime);
513 spin_unlock_irqrestore(&master->lock, flags);
518 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
523 static void fsi_stream_init(struct fsi_priv *fsi,
524 struct fsi_stream *io,
525 struct snd_pcm_substream *substream)
527 struct snd_pcm_runtime *runtime = substream->runtime;
528 struct fsi_master *master = fsi_get_master(fsi);
531 spin_lock_irqsave(&master->lock, flags);
532 io->substream = substream;
533 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
534 io->buff_sample_pos = 0;
535 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
537 io->sample_width = samples_to_bytes(runtime, 1);
539 io->oerr_num = -1; /* ignore 1st err */
540 io->uerr_num = -1; /* ignore 1st err */
541 fsi_stream_handler_call(io, init, fsi, io);
542 spin_unlock_irqrestore(&master->lock, flags);
545 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
547 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
548 struct fsi_master *master = fsi_get_master(fsi);
551 spin_lock_irqsave(&master->lock, flags);
553 if (io->oerr_num > 0)
554 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
556 if (io->uerr_num > 0)
557 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
559 fsi_stream_handler_call(io, quit, fsi, io);
560 io->substream = NULL;
561 io->buff_sample_capa = 0;
562 io->buff_sample_pos = 0;
563 io->period_samples = 0;
565 io->sample_width = 0;
569 spin_unlock_irqrestore(&master->lock, flags);
572 static int fsi_stream_transfer(struct fsi_stream *io)
574 struct fsi_priv *fsi = fsi_stream_to_priv(io);
578 return fsi_stream_handler_call(io, transfer, fsi, io);
581 #define fsi_stream_start(fsi, io)\
582 fsi_stream_handler_call(io, start_stop, fsi, io, 1)
584 #define fsi_stream_stop(fsi, io)\
585 fsi_stream_handler_call(io, start_stop, fsi, io, 0)
587 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
589 struct fsi_stream *io;
593 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
596 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
606 static int fsi_stream_remove(struct fsi_priv *fsi)
608 struct fsi_stream *io;
612 ret1 = fsi_stream_handler_call(io, remove, fsi, io);
615 ret2 = fsi_stream_handler_call(io, remove, fsi, io);
626 * format/bus/dma setting
628 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
629 u32 bus, struct device *dev)
631 struct fsi_master *master = fsi_get_master(fsi);
632 int is_play = fsi_stream_is_play(fsi, io);
635 if (fsi_version(master) >= 2) {
639 * FSI2 needs DMA/Bus setting
642 case PACKAGE_24BITBUS_FRONT:
645 dev_dbg(dev, "24bit bus / package in front\n");
647 case PACKAGE_16BITBUS_STREAM:
650 dev_dbg(dev, "16bit bus / stream mode\n");
652 case PACKAGE_24BITBUS_BACK:
656 dev_dbg(dev, "24bit bus / package in back\n");
661 fsi_reg_write(fsi, OUT_DMAC, dma);
663 fsi_reg_write(fsi, IN_DMAC, dma);
667 fsi_reg_write(fsi, DO_FMT, fmt);
669 fsi_reg_write(fsi, DI_FMT, fmt);
676 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
678 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
679 struct fsi_master *master = fsi_get_master(fsi);
681 fsi_core_mask_set(master, imsk, data, data);
682 fsi_core_mask_set(master, iemsk, data, data);
685 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
687 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
688 struct fsi_master *master = fsi_get_master(fsi);
690 fsi_core_mask_set(master, imsk, data, 0);
691 fsi_core_mask_set(master, iemsk, data, 0);
694 static u32 fsi_irq_get_status(struct fsi_master *master)
696 return fsi_core_read(master, int_st);
699 static void fsi_irq_clear_status(struct fsi_priv *fsi)
702 struct fsi_master *master = fsi_get_master(fsi);
704 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
705 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
707 /* clear interrupt factor */
708 fsi_core_mask_set(master, int_st, data, 0);
712 * SPDIF master clock function
714 * These functions are used later FSI2
716 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
718 struct fsi_master *master = fsi_get_master(fsi);
722 val = enable ? mask : 0;
725 fsi_core_mask_set(master, a_mclk, mask, val) :
726 fsi_core_mask_set(master, b_mclk, mask, val);
732 static int fsi_clk_init(struct device *dev,
733 struct fsi_priv *fsi,
737 int (*set_rate)(struct device *dev,
738 struct fsi_priv *fsi))
740 struct fsi_clk *clock = &fsi->clock;
741 int is_porta = fsi_is_port_a(fsi);
748 clock->set_rate = set_rate;
750 clock->own = devm_clk_get(dev, NULL);
751 if (IS_ERR(clock->own))
756 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
757 if (IS_ERR(clock->xck)) {
758 dev_err(dev, "can't get xck clock\n");
761 if (clock->xck == clock->own) {
762 dev_err(dev, "cpu doesn't support xck clock\n");
767 /* FSIACLK/FSIBCLK */
769 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
770 if (IS_ERR(clock->ick)) {
771 dev_err(dev, "can't get ick clock\n");
774 if (clock->ick == clock->own) {
775 dev_err(dev, "cpu doesn't support ick clock\n");
782 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
783 if (IS_ERR(clock->div)) {
784 dev_err(dev, "can't get div clock\n");
787 if (clock->div == clock->own) {
788 dev_err(dev, "cpu doens't support div clock\n");
796 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
797 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
799 fsi->clock.rate = rate;
802 static int fsi_clk_is_valid(struct fsi_priv *fsi)
804 return fsi->clock.set_rate &&
808 static int fsi_clk_enable(struct device *dev,
809 struct fsi_priv *fsi)
811 struct fsi_clk *clock = &fsi->clock;
814 if (!fsi_clk_is_valid(fsi))
817 if (0 == clock->count) {
818 ret = clock->set_rate(dev, fsi);
820 fsi_clk_invalid(fsi);
824 ret = clk_enable(clock->xck);
827 ret = clk_enable(clock->ick);
830 ret = clk_enable(clock->div);
840 clk_disable(clock->ick);
842 clk_disable(clock->xck);
847 static int fsi_clk_disable(struct device *dev,
848 struct fsi_priv *fsi)
850 struct fsi_clk *clock = &fsi->clock;
852 if (!fsi_clk_is_valid(fsi))
855 if (1 == clock->count--) {
856 clk_disable(clock->xck);
857 clk_disable(clock->ick);
858 clk_disable(clock->div);
864 static int fsi_clk_set_ackbpf(struct device *dev,
865 struct fsi_priv *fsi,
866 int ackmd, int bpfmd)
870 /* check ackmd/bpfmd relationship */
872 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
894 dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
919 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
923 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
925 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
931 static int fsi_clk_set_rate_external(struct device *dev,
932 struct fsi_priv *fsi)
934 struct clk *xck = fsi->clock.xck;
935 struct clk *ick = fsi->clock.ick;
936 unsigned long rate = fsi->clock.rate;
941 /* check clock rate */
942 xrate = clk_get_rate(xck);
944 dev_err(dev, "unsupported clock rate\n");
948 clk_set_parent(ick, xck);
949 clk_set_rate(ick, xrate);
951 bpfmd = fsi->chan_num * 32;
952 ackmd = xrate / rate;
954 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
956 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
958 dev_err(dev, "%s failed", __func__);
963 static int fsi_clk_set_rate_cpg(struct device *dev,
964 struct fsi_priv *fsi)
966 struct clk *ick = fsi->clock.ick;
967 struct clk *div = fsi->clock.div;
968 unsigned long rate = fsi->clock.rate;
969 unsigned long target = 0; /* 12288000 or 11289600 */
970 unsigned long actual, cout;
971 unsigned long diff, min;
972 unsigned long best_cout, best_act;
977 if (!(12288000 % rate))
979 if (!(11289600 % rate))
982 dev_err(dev, "unsupported rate\n");
986 bpfmd = fsi->chan_num * 32;
987 ackmd = target / rate;
988 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
990 dev_err(dev, "%s failed", __func__);
997 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
999 * But, it needs to find best match of CPG and FSI_DIV
1000 * combination, since it is difficult to generate correct
1001 * frequency of audio clock from ick clock only.
1002 * Because ick is created from its parent clock.
1004 * target = rate x [512/256/128/64]fs
1005 * cout = round(target x adjustment)
1006 * actual = cout / adjustment (by FSI-DIV) ~= target
1012 for (adj = 1; adj < 0xffff; adj++) {
1014 cout = target * adj;
1015 if (cout > 100000000) /* max clock = 100MHz */
1018 /* cout/actual audio clock */
1019 cout = clk_round_rate(ick, cout);
1020 actual = cout / adj;
1022 /* find best frequency */
1023 diff = abs(actual - target);
1031 ret = clk_set_rate(ick, best_cout);
1033 dev_err(dev, "ick clock failed\n");
1037 ret = clk_set_rate(div, clk_round_rate(div, best_act));
1039 dev_err(dev, "div clock failed\n");
1043 dev_dbg(dev, "ick/div = %ld/%ld\n",
1044 clk_get_rate(ick), clk_get_rate(div));
1049 static void fsi_pointer_update(struct fsi_stream *io, int size)
1051 io->buff_sample_pos += size;
1053 if (io->buff_sample_pos >=
1054 io->period_samples * (io->period_pos + 1)) {
1055 struct snd_pcm_substream *substream = io->substream;
1056 struct snd_pcm_runtime *runtime = substream->runtime;
1060 if (io->period_pos >= runtime->periods) {
1061 io->buff_sample_pos = 0;
1065 snd_pcm_period_elapsed(substream);
1070 * pio data transfer handler
1072 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
1076 if (fsi_is_enable_stream(fsi)) {
1080 * fsi_pio_push_init()
1082 u32 *buf = (u32 *)_buf;
1084 for (i = 0; i < samples / 2; i++)
1085 fsi_reg_write(fsi, DODT, buf[i]);
1088 u16 *buf = (u16 *)_buf;
1090 for (i = 0; i < samples; i++)
1091 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
1095 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
1097 u16 *buf = (u16 *)_buf;
1100 for (i = 0; i < samples; i++)
1101 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
1104 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
1106 u32 *buf = (u32 *)_buf;
1109 for (i = 0; i < samples; i++)
1110 fsi_reg_write(fsi, DODT, *(buf + i));
1113 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
1115 u32 *buf = (u32 *)_buf;
1118 for (i = 0; i < samples; i++)
1119 *(buf + i) = fsi_reg_read(fsi, DIDT);
1122 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
1124 struct snd_pcm_runtime *runtime = io->substream->runtime;
1126 return runtime->dma_area +
1127 samples_to_bytes(runtime, io->buff_sample_pos);
1130 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
1131 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
1132 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
1137 if (!fsi_stream_is_working(fsi, io))
1140 buf = fsi_pio_get_area(fsi, io);
1142 switch (io->sample_width) {
1144 run16(fsi, buf, samples);
1147 run32(fsi, buf, samples);
1153 fsi_pointer_update(io, samples);
1158 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
1160 int sample_residues; /* samples in FSI fifo */
1161 int sample_space; /* ALSA free samples space */
1164 sample_residues = fsi_get_current_fifo_samples(fsi, io);
1165 sample_space = io->buff_sample_capa - io->buff_sample_pos;
1167 samples = min(sample_residues, sample_space);
1169 return fsi_pio_transfer(fsi, io,
1175 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
1177 int sample_residues; /* ALSA residue samples */
1178 int sample_space; /* FSI fifo free samples space */
1181 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
1182 sample_space = io->fifo_sample_capa -
1183 fsi_get_current_fifo_samples(fsi, io);
1185 samples = min(sample_residues, sample_space);
1187 return fsi_pio_transfer(fsi, io,
1193 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1196 struct fsi_master *master = fsi_get_master(fsi);
1197 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1200 fsi_irq_enable(fsi, io);
1202 fsi_irq_disable(fsi, io);
1204 if (fsi_is_clk_master(fsi))
1205 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1210 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
1213 * we can use 16bit stream mode
1214 * when "playback" and "16bit data"
1215 * and platform allows "stream mode"
1219 if (fsi_is_enable_stream(fsi))
1220 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1221 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1223 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1224 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1228 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
1231 * always 24bit bus, package back when "capture"
1233 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1234 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1238 static struct fsi_stream_handler fsi_pio_push_handler = {
1239 .init = fsi_pio_push_init,
1240 .transfer = fsi_pio_push,
1241 .start_stop = fsi_pio_start_stop,
1244 static struct fsi_stream_handler fsi_pio_pop_handler = {
1245 .init = fsi_pio_pop_init,
1246 .transfer = fsi_pio_pop,
1247 .start_stop = fsi_pio_start_stop,
1250 static irqreturn_t fsi_interrupt(int irq, void *data)
1252 struct fsi_master *master = data;
1253 u32 int_st = fsi_irq_get_status(master);
1255 /* clear irq status */
1256 fsi_master_mask_set(master, SOFT_RST, IR, 0);
1257 fsi_master_mask_set(master, SOFT_RST, IR, IR);
1259 if (int_st & AB_IO(1, AO_SHIFT))
1260 fsi_stream_transfer(&master->fsia.playback);
1261 if (int_st & AB_IO(1, BO_SHIFT))
1262 fsi_stream_transfer(&master->fsib.playback);
1263 if (int_st & AB_IO(1, AI_SHIFT))
1264 fsi_stream_transfer(&master->fsia.capture);
1265 if (int_st & AB_IO(1, BI_SHIFT))
1266 fsi_stream_transfer(&master->fsib.capture);
1268 fsi_count_fifo_err(&master->fsia);
1269 fsi_count_fifo_err(&master->fsib);
1271 fsi_irq_clear_status(&master->fsia);
1272 fsi_irq_clear_status(&master->fsib);
1278 * dma data transfer handler
1280 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
1283 * 24bit data : 24bit bus / package in back
1284 * 16bit data : 16bit bus / stream mode
1286 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1287 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1292 static void fsi_dma_complete(void *data)
1294 struct fsi_stream *io = (struct fsi_stream *)data;
1295 struct fsi_priv *fsi = fsi_stream_to_priv(io);
1297 fsi_pointer_update(io, io->period_samples);
1299 fsi_count_fifo_err(fsi);
1302 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
1304 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
1305 struct snd_pcm_substream *substream = io->substream;
1306 struct dma_async_tx_descriptor *desc;
1307 int is_play = fsi_stream_is_play(fsi, io);
1308 enum dma_transfer_direction dir;
1312 dir = DMA_MEM_TO_DEV;
1314 dir = DMA_DEV_TO_MEM;
1316 desc = dmaengine_prep_dma_cyclic(io->chan,
1317 substream->runtime->dma_addr,
1318 snd_pcm_lib_buffer_bytes(substream),
1319 snd_pcm_lib_period_bytes(substream),
1321 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1323 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n");
1324 goto fsi_dma_transfer_err;
1327 desc->callback = fsi_dma_complete;
1328 desc->callback_param = io;
1330 if (dmaengine_submit(desc) < 0) {
1331 dev_err(dai->dev, "tx_submit() fail\n");
1332 goto fsi_dma_transfer_err;
1335 dma_async_issue_pending(io->chan);
1340 * In DMAEngine case, codec and FSI cannot be started simultaneously
1341 * since FSI is using the scheduler work queue.
1342 * Therefore, in capture case, probably FSI FIFO will have got
1343 * overflow error in this point.
1344 * in that case, DMA cannot start transfer until error was cleared.
1347 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
1348 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1349 fsi_reg_write(fsi, DIFF_ST, 0);
1355 fsi_dma_transfer_err:
1359 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1362 struct fsi_master *master = fsi_get_master(fsi);
1363 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1364 u32 enable = start ? DMA_ON : 0;
1366 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
1368 dmaengine_terminate_all(io->chan);
1370 if (fsi_is_clk_master(fsi))
1371 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1376 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
1378 int is_play = fsi_stream_is_play(fsi, io);
1380 #ifdef CONFIG_SUPERH
1381 dma_cap_mask_t mask;
1383 dma_cap_set(DMA_SLAVE, mask);
1385 io->chan = dma_request_channel(mask, shdma_chan_filter,
1386 (void *)io->dma_id);
1388 io->chan = dma_request_slave_channel(dev, is_play ? "tx" : "rx");
1391 struct dma_slave_config cfg = {};
1395 cfg.dst_addr = fsi->phys + REG_DODT;
1396 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1397 cfg.direction = DMA_MEM_TO_DEV;
1399 cfg.src_addr = fsi->phys + REG_DIDT;
1400 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1401 cfg.direction = DMA_DEV_TO_MEM;
1404 ret = dmaengine_slave_config(io->chan, &cfg);
1406 dma_release_channel(io->chan);
1413 /* switch to PIO handler */
1415 fsi->playback.handler = &fsi_pio_push_handler;
1417 fsi->capture.handler = &fsi_pio_pop_handler;
1419 dev_info(dev, "switch handler (dma => pio)\n");
1422 return fsi_stream_probe(fsi, dev);
1428 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
1430 fsi_stream_stop(fsi, io);
1433 dma_release_channel(io->chan);
1439 static struct fsi_stream_handler fsi_dma_push_handler = {
1440 .init = fsi_dma_init,
1441 .probe = fsi_dma_probe,
1442 .transfer = fsi_dma_transfer,
1443 .remove = fsi_dma_remove,
1444 .start_stop = fsi_dma_push_start_stop,
1450 static void fsi_fifo_init(struct fsi_priv *fsi,
1451 struct fsi_stream *io,
1454 struct fsi_master *master = fsi_get_master(fsi);
1455 int is_play = fsi_stream_is_play(fsi, io);
1459 /* get on-chip RAM capacity */
1460 shift = fsi_master_read(master, FIFO_SZ);
1461 shift >>= fsi_get_port_shift(fsi, io);
1462 shift &= FIFO_SZ_MASK;
1463 frame_capa = 256 << shift;
1464 dev_dbg(dev, "fifo = %d words\n", frame_capa);
1467 * The maximum number of sample data varies depending
1468 * on the number of channels selected for the format.
1470 * FIFOs are used in 4-channel units in 3-channel mode
1471 * and in 8-channel units in 5- to 7-channel mode
1472 * meaning that more FIFOs than the required size of DPRAM
1475 * ex) if 256 words of DP-RAM is connected
1476 * 1 channel: 256 (256 x 1 = 256)
1477 * 2 channels: 128 (128 x 2 = 256)
1478 * 3 channels: 64 ( 64 x 3 = 192)
1479 * 4 channels: 64 ( 64 x 4 = 256)
1480 * 5 channels: 32 ( 32 x 5 = 160)
1481 * 6 channels: 32 ( 32 x 6 = 192)
1482 * 7 channels: 32 ( 32 x 7 = 224)
1483 * 8 channels: 32 ( 32 x 8 = 256)
1485 for (i = 1; i < fsi->chan_num; i <<= 1)
1487 dev_dbg(dev, "%d channel %d store\n",
1488 fsi->chan_num, frame_capa);
1490 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
1493 * set interrupt generation factor
1497 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
1498 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
1500 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
1501 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1505 static int fsi_hw_startup(struct fsi_priv *fsi,
1506 struct fsi_stream *io,
1512 if (fsi_is_clk_master(fsi))
1515 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
1517 /* clock inversion (CKG2) */
1519 if (fsi->bit_clk_inv)
1521 if (fsi->lr_clk_inv)
1523 if (fsi_is_clk_master(fsi))
1525 fsi_reg_write(fsi, CKG2, data);
1528 if (fsi_is_spdif(fsi)) {
1529 fsi_spdif_clk_ctrl(fsi, 1);
1530 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
1537 switch (io->sample_width) {
1539 data = BUSOP_GET(16, io->bus_option);
1542 data = BUSOP_GET(24, io->bus_option);
1545 fsi_format_bus_setup(fsi, io, data, dev);
1548 fsi_irq_disable(fsi, io);
1549 fsi_irq_clear_status(fsi);
1552 fsi_fifo_init(fsi, io, dev);
1554 /* start master clock */
1555 if (fsi_is_clk_master(fsi))
1556 return fsi_clk_enable(dev, fsi);
1561 static int fsi_hw_shutdown(struct fsi_priv *fsi,
1564 /* stop master clock */
1565 if (fsi_is_clk_master(fsi))
1566 return fsi_clk_disable(dev, fsi);
1571 static int fsi_dai_startup(struct snd_pcm_substream *substream,
1572 struct snd_soc_dai *dai)
1574 struct fsi_priv *fsi = fsi_get_priv(substream);
1576 fsi_clk_invalid(fsi);
1581 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
1582 struct snd_soc_dai *dai)
1584 struct fsi_priv *fsi = fsi_get_priv(substream);
1586 fsi_clk_invalid(fsi);
1589 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
1590 struct snd_soc_dai *dai)
1592 struct fsi_priv *fsi = fsi_get_priv(substream);
1593 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1597 case SNDRV_PCM_TRIGGER_START:
1598 fsi_stream_init(fsi, io, substream);
1600 ret = fsi_hw_startup(fsi, io, dai->dev);
1602 ret = fsi_stream_start(fsi, io);
1604 ret = fsi_stream_transfer(io);
1606 case SNDRV_PCM_TRIGGER_STOP:
1608 ret = fsi_hw_shutdown(fsi, dai->dev);
1609 fsi_stream_stop(fsi, io);
1610 fsi_stream_quit(fsi, io);
1617 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
1619 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1620 case SND_SOC_DAIFMT_I2S:
1624 case SND_SOC_DAIFMT_LEFT_J:
1635 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1637 struct fsi_master *master = fsi_get_master(fsi);
1639 if (fsi_version(master) < 2)
1642 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
1648 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1650 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1653 /* set master/slave audio interface */
1654 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1655 case SND_SOC_DAIFMT_CBM_CFM:
1657 case SND_SOC_DAIFMT_CBS_CFS:
1658 fsi->clk_master = 1; /* codec is slave, cpu is master */
1664 /* set clock inversion */
1665 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1666 case SND_SOC_DAIFMT_NB_IF:
1667 fsi->bit_clk_inv = 0;
1668 fsi->lr_clk_inv = 1;
1670 case SND_SOC_DAIFMT_IB_NF:
1671 fsi->bit_clk_inv = 1;
1672 fsi->lr_clk_inv = 0;
1674 case SND_SOC_DAIFMT_IB_IF:
1675 fsi->bit_clk_inv = 1;
1676 fsi->lr_clk_inv = 1;
1678 case SND_SOC_DAIFMT_NB_NF:
1680 fsi->bit_clk_inv = 0;
1681 fsi->lr_clk_inv = 0;
1685 if (fsi_is_clk_master(fsi)) {
1687 fsi_clk_init(dai->dev, fsi, 0, 1, 1,
1688 fsi_clk_set_rate_cpg);
1690 fsi_clk_init(dai->dev, fsi, 1, 1, 0,
1691 fsi_clk_set_rate_external);
1695 if (fsi_is_spdif(fsi))
1696 ret = fsi_set_fmt_spdif(fsi);
1698 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1703 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1704 struct snd_pcm_hw_params *params,
1705 struct snd_soc_dai *dai)
1707 struct fsi_priv *fsi = fsi_get_priv(substream);
1709 if (fsi_is_clk_master(fsi))
1710 fsi_clk_valid(fsi, params_rate(params));
1715 static const struct snd_soc_dai_ops fsi_dai_ops = {
1716 .startup = fsi_dai_startup,
1717 .shutdown = fsi_dai_shutdown,
1718 .trigger = fsi_dai_trigger,
1719 .set_fmt = fsi_dai_set_fmt,
1720 .hw_params = fsi_dai_hw_params,
1727 static struct snd_pcm_hardware fsi_pcm_hardware = {
1728 .info = SNDRV_PCM_INFO_INTERLEAVED |
1729 SNDRV_PCM_INFO_MMAP |
1730 SNDRV_PCM_INFO_MMAP_VALID,
1731 .buffer_bytes_max = 64 * 1024,
1732 .period_bytes_min = 32,
1733 .period_bytes_max = 8192,
1739 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1741 struct snd_pcm_runtime *runtime = substream->runtime;
1744 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1746 ret = snd_pcm_hw_constraint_integer(runtime,
1747 SNDRV_PCM_HW_PARAM_PERIODS);
1752 static int fsi_hw_params(struct snd_pcm_substream *substream,
1753 struct snd_pcm_hw_params *hw_params)
1755 return snd_pcm_lib_malloc_pages(substream,
1756 params_buffer_bytes(hw_params));
1759 static int fsi_hw_free(struct snd_pcm_substream *substream)
1761 return snd_pcm_lib_free_pages(substream);
1764 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1766 struct fsi_priv *fsi = fsi_get_priv(substream);
1767 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1769 return fsi_sample2frame(fsi, io->buff_sample_pos);
1772 static struct snd_pcm_ops fsi_pcm_ops = {
1773 .open = fsi_pcm_open,
1774 .ioctl = snd_pcm_lib_ioctl,
1775 .hw_params = fsi_hw_params,
1776 .hw_free = fsi_hw_free,
1777 .pointer = fsi_pointer,
1784 #define PREALLOC_BUFFER (32 * 1024)
1785 #define PREALLOC_BUFFER_MAX (32 * 1024)
1787 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
1789 return snd_pcm_lib_preallocate_pages_for_all(
1792 rtd->card->snd_card->dev,
1793 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1800 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1805 .formats = FSI_FMTS,
1811 .formats = FSI_FMTS,
1815 .ops = &fsi_dai_ops,
1821 .formats = FSI_FMTS,
1827 .formats = FSI_FMTS,
1831 .ops = &fsi_dai_ops,
1835 static struct snd_soc_platform_driver fsi_soc_platform = {
1836 .ops = &fsi_pcm_ops,
1837 .pcm_new = fsi_pcm_new,
1840 static const struct snd_soc_component_driver fsi_soc_component = {
1847 static void fsi_of_parse(char *name,
1848 struct device_node *np,
1849 struct sh_fsi_port_info *info,
1854 unsigned long flags = 0;
1858 } of_parse_property[] = {
1859 { "spdif-connection", SH_FSI_FMT_SPDIF },
1860 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE },
1861 { "use-internal-clock", SH_FSI_CLK_CPG },
1864 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
1865 sprintf(prop, "%s,%s", name, of_parse_property[i].name);
1866 if (of_get_property(np, prop, NULL))
1867 flags |= of_parse_property[i].val;
1869 info->flags = flags;
1871 dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
1874 static void fsi_port_info_init(struct fsi_priv *fsi,
1875 struct sh_fsi_port_info *info)
1877 if (info->flags & SH_FSI_FMT_SPDIF)
1880 if (info->flags & SH_FSI_CLK_CPG)
1883 if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
1884 fsi->enable_stream = 1;
1887 static void fsi_handler_init(struct fsi_priv *fsi,
1888 struct sh_fsi_port_info *info)
1890 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
1891 fsi->playback.priv = fsi;
1892 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
1893 fsi->capture.priv = fsi;
1896 fsi->playback.dma_id = info->tx_id;
1897 fsi->playback.handler = &fsi_dma_push_handler;
1901 static const struct fsi_core fsi1_core = {
1910 static const struct fsi_core fsi2_core = {
1914 .int_st = CPU_INT_ST,
1917 .a_mclk = A_MST_CTLR,
1918 .b_mclk = B_MST_CTLR,
1921 static const struct of_device_id fsi_of_match[] = {
1922 { .compatible = "renesas,sh_fsi", .data = &fsi1_core},
1923 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core},
1926 MODULE_DEVICE_TABLE(of, fsi_of_match);
1928 static const struct platform_device_id fsi_id_table[] = {
1929 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1932 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1934 static int fsi_probe(struct platform_device *pdev)
1936 struct fsi_master *master;
1937 struct device_node *np = pdev->dev.of_node;
1938 struct sh_fsi_platform_info info;
1939 const struct fsi_core *core;
1940 struct fsi_priv *fsi;
1941 struct resource *res;
1945 memset(&info, 0, sizeof(info));
1949 const struct of_device_id *of_id;
1951 of_id = of_match_device(fsi_of_match, &pdev->dev);
1954 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
1955 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
1958 const struct platform_device_id *id_entry = pdev->id_entry;
1960 core = (struct fsi_core *)id_entry->driver_data;
1962 if (pdev->dev.platform_data)
1963 memcpy(&info, pdev->dev.platform_data, sizeof(info));
1967 dev_err(&pdev->dev, "unknown fsi device\n");
1971 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1972 irq = platform_get_irq(pdev, 0);
1973 if (!res || (int)irq <= 0) {
1974 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1978 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1980 dev_err(&pdev->dev, "Could not allocate master\n");
1984 master->base = devm_ioremap_nocache(&pdev->dev,
1985 res->start, resource_size(res));
1986 if (!master->base) {
1987 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1991 /* master setting */
1992 master->core = core;
1993 spin_lock_init(&master->lock);
1996 fsi = &master->fsia;
1997 fsi->base = master->base;
1998 fsi->phys = res->start;
1999 fsi->master = master;
2000 fsi_port_info_init(fsi, &info.port_a);
2001 fsi_handler_init(fsi, &info.port_a);
2002 ret = fsi_stream_probe(fsi, &pdev->dev);
2004 dev_err(&pdev->dev, "FSIA stream probe failed\n");
2009 fsi = &master->fsib;
2010 fsi->base = master->base + 0x40;
2011 fsi->phys = res->start + 0x40;
2012 fsi->master = master;
2013 fsi_port_info_init(fsi, &info.port_b);
2014 fsi_handler_init(fsi, &info.port_b);
2015 ret = fsi_stream_probe(fsi, &pdev->dev);
2017 dev_err(&pdev->dev, "FSIB stream probe failed\n");
2021 pm_runtime_enable(&pdev->dev);
2022 dev_set_drvdata(&pdev->dev, master);
2024 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
2025 dev_name(&pdev->dev), master);
2027 dev_err(&pdev->dev, "irq request err\n");
2031 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
2033 dev_err(&pdev->dev, "cannot snd soc register\n");
2037 ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component,
2038 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
2040 dev_err(&pdev->dev, "cannot snd component register\n");
2047 snd_soc_unregister_platform(&pdev->dev);
2049 pm_runtime_disable(&pdev->dev);
2050 fsi_stream_remove(&master->fsib);
2052 fsi_stream_remove(&master->fsia);
2057 static int fsi_remove(struct platform_device *pdev)
2059 struct fsi_master *master;
2061 master = dev_get_drvdata(&pdev->dev);
2063 pm_runtime_disable(&pdev->dev);
2065 snd_soc_unregister_component(&pdev->dev);
2066 snd_soc_unregister_platform(&pdev->dev);
2068 fsi_stream_remove(&master->fsia);
2069 fsi_stream_remove(&master->fsib);
2074 static void __fsi_suspend(struct fsi_priv *fsi,
2075 struct fsi_stream *io,
2078 if (!fsi_stream_is_working(fsi, io))
2081 fsi_stream_stop(fsi, io);
2082 fsi_hw_shutdown(fsi, dev);
2085 static void __fsi_resume(struct fsi_priv *fsi,
2086 struct fsi_stream *io,
2089 if (!fsi_stream_is_working(fsi, io))
2092 fsi_hw_startup(fsi, io, dev);
2093 fsi_stream_start(fsi, io);
2096 static int fsi_suspend(struct device *dev)
2098 struct fsi_master *master = dev_get_drvdata(dev);
2099 struct fsi_priv *fsia = &master->fsia;
2100 struct fsi_priv *fsib = &master->fsib;
2102 __fsi_suspend(fsia, &fsia->playback, dev);
2103 __fsi_suspend(fsia, &fsia->capture, dev);
2105 __fsi_suspend(fsib, &fsib->playback, dev);
2106 __fsi_suspend(fsib, &fsib->capture, dev);
2111 static int fsi_resume(struct device *dev)
2113 struct fsi_master *master = dev_get_drvdata(dev);
2114 struct fsi_priv *fsia = &master->fsia;
2115 struct fsi_priv *fsib = &master->fsib;
2117 __fsi_resume(fsia, &fsia->playback, dev);
2118 __fsi_resume(fsia, &fsia->capture, dev);
2120 __fsi_resume(fsib, &fsib->playback, dev);
2121 __fsi_resume(fsib, &fsib->capture, dev);
2126 static struct dev_pm_ops fsi_pm_ops = {
2127 .suspend = fsi_suspend,
2128 .resume = fsi_resume,
2131 static struct platform_driver fsi_driver = {
2133 .name = "fsi-pcm-audio",
2135 .of_match_table = fsi_of_match,
2138 .remove = fsi_remove,
2139 .id_table = fsi_id_table,
2142 module_platform_driver(fsi_driver);
2144 MODULE_LICENSE("GPL v2");
2145 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
2146 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
2147 MODULE_ALIAS("platform:fsi-pcm-audio");