1 /* ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
3 * Copyright (c) 2006 Wolfson Microelectronics PLC.
4 * Graeme Gregory graeme.gregory@wolfsonmicro.com
5 * linux@wolfsonmicro.com
7 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
8 * http://armlinux.simtec.co.uk/
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 #include <linux/module.h>
18 #include <linux/delay.h>
19 #include <linux/clk.h>
22 #include <sound/soc.h>
23 #include <sound/pcm_params.h>
25 #include "regs-i2s-v2.h"
26 #include "s3c-i2s-v2.h"
28 #undef S3C_IIS_V2_SUPPORTED
30 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) \
31 || defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_CPU_S5PV210)
32 #define S3C_IIS_V2_SUPPORTED
35 #ifndef S3C_IIS_V2_SUPPORTED
36 #error Unsupported CPU model
39 #define S3C2412_I2S_DEBUG_CON 0
41 static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
43 return snd_soc_dai_get_drvdata(cpu_dai);
46 #define bit_set(v, b) (((v) & (b)) ? 1 : 0)
48 #if S3C2412_I2S_DEBUG_CON
49 static void dbg_showcon(const char *fn, u32 con)
51 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
52 bit_set(con, S3C2412_IISCON_LRINDEX),
53 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
54 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
55 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
56 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
58 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
60 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
61 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
62 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
63 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
64 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
65 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
66 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
67 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
70 static inline void dbg_showcon(const char *fn, u32 con)
76 /* Turn on or off the transmission path. */
77 static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
79 void __iomem *regs = i2s->regs;
82 pr_debug("%s(%d)\n", __func__, on);
84 fic = readl(regs + S3C2412_IISFIC);
85 con = readl(regs + S3C2412_IISCON);
86 mod = readl(regs + S3C2412_IISMOD);
88 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
91 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
92 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
93 con &= ~S3C2412_IISCON_TXCH_PAUSE;
95 switch (mod & S3C2412_IISMOD_MODE_MASK) {
96 case S3C2412_IISMOD_MODE_TXONLY:
97 case S3C2412_IISMOD_MODE_TXRX:
98 /* do nothing, we are in the right mode */
101 case S3C2412_IISMOD_MODE_RXONLY:
102 mod &= ~S3C2412_IISMOD_MODE_MASK;
103 mod |= S3C2412_IISMOD_MODE_TXRX;
107 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
108 mod & S3C2412_IISMOD_MODE_MASK);
112 writel(con, regs + S3C2412_IISCON);
113 writel(mod, regs + S3C2412_IISMOD);
115 /* Note, we do not have any indication that the FIFO problems
116 * tha the S3C2410/2440 had apply here, so we should be able
117 * to disable the DMA and TX without resetting the FIFOS.
120 con |= S3C2412_IISCON_TXDMA_PAUSE;
121 con |= S3C2412_IISCON_TXCH_PAUSE;
122 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
124 switch (mod & S3C2412_IISMOD_MODE_MASK) {
125 case S3C2412_IISMOD_MODE_TXRX:
126 mod &= ~S3C2412_IISMOD_MODE_MASK;
127 mod |= S3C2412_IISMOD_MODE_RXONLY;
130 case S3C2412_IISMOD_MODE_TXONLY:
131 mod &= ~S3C2412_IISMOD_MODE_MASK;
132 con &= ~S3C2412_IISCON_IIS_ACTIVE;
136 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
137 mod & S3C2412_IISMOD_MODE_MASK);
141 writel(mod, regs + S3C2412_IISMOD);
142 writel(con, regs + S3C2412_IISCON);
145 fic = readl(regs + S3C2412_IISFIC);
146 dbg_showcon(__func__, con);
147 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
150 static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
152 void __iomem *regs = i2s->regs;
155 pr_debug("%s(%d)\n", __func__, on);
157 fic = readl(regs + S3C2412_IISFIC);
158 con = readl(regs + S3C2412_IISCON);
159 mod = readl(regs + S3C2412_IISMOD);
161 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
164 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
165 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
166 con &= ~S3C2412_IISCON_RXCH_PAUSE;
168 switch (mod & S3C2412_IISMOD_MODE_MASK) {
169 case S3C2412_IISMOD_MODE_TXRX:
170 case S3C2412_IISMOD_MODE_RXONLY:
171 /* do nothing, we are in the right mode */
174 case S3C2412_IISMOD_MODE_TXONLY:
175 mod &= ~S3C2412_IISMOD_MODE_MASK;
176 mod |= S3C2412_IISMOD_MODE_TXRX;
180 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
181 mod & S3C2412_IISMOD_MODE_MASK);
184 writel(mod, regs + S3C2412_IISMOD);
185 writel(con, regs + S3C2412_IISCON);
187 /* See txctrl notes on FIFOs. */
189 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
190 con |= S3C2412_IISCON_RXDMA_PAUSE;
191 con |= S3C2412_IISCON_RXCH_PAUSE;
193 switch (mod & S3C2412_IISMOD_MODE_MASK) {
194 case S3C2412_IISMOD_MODE_RXONLY:
195 con &= ~S3C2412_IISCON_IIS_ACTIVE;
196 mod &= ~S3C2412_IISMOD_MODE_MASK;
199 case S3C2412_IISMOD_MODE_TXRX:
200 mod &= ~S3C2412_IISMOD_MODE_MASK;
201 mod |= S3C2412_IISMOD_MODE_TXONLY;
205 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
206 mod & S3C2412_IISMOD_MODE_MASK);
209 writel(con, regs + S3C2412_IISCON);
210 writel(mod, regs + S3C2412_IISMOD);
213 fic = readl(regs + S3C2412_IISFIC);
214 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
217 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
220 * Wait for the LR signal to allow synchronisation to the L/R clock
221 * from the codec. May only be needed for slave mode.
223 static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
226 unsigned long loops = msecs_to_loops(5);
228 pr_debug("Entered %s\n", __func__);
231 iiscon = readl(i2s->regs + S3C2412_IISCON);
232 if (iiscon & S3C2412_IISCON_LRINDEX)
239 printk(KERN_ERR "%s: timeout\n", __func__);
247 * Set S3C2412 I2S DAI format
249 static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
252 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
255 pr_debug("Entered %s\n", __func__);
257 iismod = readl(i2s->regs + S3C2412_IISMOD);
258 pr_debug("hw_params r: IISMOD: %x \n", iismod);
260 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
261 case SND_SOC_DAIFMT_CBM_CFM:
263 iismod |= S3C2412_IISMOD_SLAVE;
265 case SND_SOC_DAIFMT_CBS_CFS:
267 iismod &= ~S3C2412_IISMOD_SLAVE;
270 pr_err("unknown master/slave format\n");
274 iismod &= ~S3C2412_IISMOD_SDF_MASK;
276 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
277 case SND_SOC_DAIFMT_RIGHT_J:
278 iismod |= S3C2412_IISMOD_LR_RLOW;
279 iismod |= S3C2412_IISMOD_SDF_MSB;
281 case SND_SOC_DAIFMT_LEFT_J:
282 iismod |= S3C2412_IISMOD_LR_RLOW;
283 iismod |= S3C2412_IISMOD_SDF_LSB;
285 case SND_SOC_DAIFMT_I2S:
286 iismod &= ~S3C2412_IISMOD_LR_RLOW;
287 iismod |= S3C2412_IISMOD_SDF_IIS;
290 pr_err("Unknown data format\n");
294 writel(iismod, i2s->regs + S3C2412_IISMOD);
295 pr_debug("hw_params w: IISMOD: %x \n", iismod);
299 static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream,
300 struct snd_pcm_hw_params *params,
301 struct snd_soc_dai *dai)
303 struct s3c_i2sv2_info *i2s = to_info(dai);
304 struct snd_dmaengine_dai_dma_data *dma_data;
307 pr_debug("Entered %s\n", __func__);
309 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
310 dma_data = i2s->dma_playback;
312 dma_data = i2s->dma_capture;
314 snd_soc_dai_set_dma_data(dai, substream, dma_data);
316 /* Working copies of register */
317 iismod = readl(i2s->regs + S3C2412_IISMOD);
318 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
320 iismod &= ~S3C64XX_IISMOD_BLC_MASK;
322 switch (params_width(params)) {
324 iismod |= S3C64XX_IISMOD_BLC_8BIT;
329 iismod |= S3C64XX_IISMOD_BLC_24BIT;
333 writel(iismod, i2s->regs + S3C2412_IISMOD);
334 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
339 static int s3c_i2sv2_set_sysclk(struct snd_soc_dai *cpu_dai,
340 int clk_id, unsigned int freq, int dir)
342 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
343 u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
345 pr_debug("Entered %s\n", __func__);
346 pr_debug("%s r: IISMOD: %x\n", __func__, iismod);
349 case S3C_I2SV2_CLKSRC_PCLK:
350 iismod &= ~S3C2412_IISMOD_IMS_SYSMUX;
353 case S3C_I2SV2_CLKSRC_AUDIOBUS:
354 iismod |= S3C2412_IISMOD_IMS_SYSMUX;
357 case S3C_I2SV2_CLKSRC_CDCLK:
358 /* Error if controller doesn't have the CDCLKCON bit */
359 if (!(i2s->feature & S3C_FEATURE_CDCLKCON))
363 case SND_SOC_CLOCK_IN:
364 iismod |= S3C64XX_IISMOD_CDCLKCON;
366 case SND_SOC_CLOCK_OUT:
367 iismod &= ~S3C64XX_IISMOD_CDCLKCON;
378 writel(iismod, i2s->regs + S3C2412_IISMOD);
379 pr_debug("%s w: IISMOD: %x\n", __func__, iismod);
384 static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
385 struct snd_soc_dai *dai)
387 struct snd_soc_pcm_runtime *rtd = substream->private_data;
388 struct s3c_i2sv2_info *i2s = to_info(rtd->cpu_dai);
389 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
393 pr_debug("Entered %s\n", __func__);
396 case SNDRV_PCM_TRIGGER_START:
397 /* On start, ensure that the FIFOs are cleared and reset. */
399 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
400 i2s->regs + S3C2412_IISFIC);
402 /* clear again, just in case */
403 writel(0x0, i2s->regs + S3C2412_IISFIC);
405 case SNDRV_PCM_TRIGGER_RESUME:
406 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
408 ret = s3c2412_snd_lrsync(i2s);
413 local_irq_save(irqs);
416 s3c2412_snd_rxctrl(i2s, 1);
418 s3c2412_snd_txctrl(i2s, 1);
420 local_irq_restore(irqs);
424 case SNDRV_PCM_TRIGGER_STOP:
425 case SNDRV_PCM_TRIGGER_SUSPEND:
426 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
427 local_irq_save(irqs);
430 s3c2412_snd_rxctrl(i2s, 0);
432 s3c2412_snd_txctrl(i2s, 0);
434 local_irq_restore(irqs);
446 * Set S3C2412 Clock dividers
448 static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
451 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
454 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
457 case S3C_I2SV2_DIV_BCLK:
460 div = S3C2412_IISMOD_BCLK_16FS;
464 div = S3C2412_IISMOD_BCLK_32FS;
468 div = S3C2412_IISMOD_BCLK_24FS;
472 div = S3C2412_IISMOD_BCLK_48FS;
479 reg = readl(i2s->regs + S3C2412_IISMOD);
480 reg &= ~S3C2412_IISMOD_BCLK_MASK;
481 writel(reg | div, i2s->regs + S3C2412_IISMOD);
483 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
486 case S3C_I2SV2_DIV_RCLK:
489 div = S3C2412_IISMOD_RCLK_256FS;
493 div = S3C2412_IISMOD_RCLK_384FS;
497 div = S3C2412_IISMOD_RCLK_512FS;
501 div = S3C2412_IISMOD_RCLK_768FS;
508 reg = readl(i2s->regs + S3C2412_IISMOD);
509 reg &= ~S3C2412_IISMOD_RCLK_MASK;
510 writel(reg | div, i2s->regs + S3C2412_IISMOD);
511 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
514 case S3C_I2SV2_DIV_PRESCALER:
516 writel((div << 8) | S3C2412_IISPSR_PSREN,
517 i2s->regs + S3C2412_IISPSR);
519 writel(0x0, i2s->regs + S3C2412_IISPSR);
521 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
531 static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
532 struct snd_soc_dai *dai)
534 struct s3c_i2sv2_info *i2s = to_info(dai);
535 u32 reg = readl(i2s->regs + S3C2412_IISFIC);
536 snd_pcm_sframes_t delay;
538 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
539 delay = S3C2412_IISFIC_TXCOUNT(reg);
541 delay = S3C2412_IISFIC_RXCOUNT(reg);
546 struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai)
548 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
549 u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
551 if (iismod & S3C2412_IISMOD_IMS_SYSMUX)
552 return i2s->iis_cclk;
554 return i2s->iis_pclk;
556 EXPORT_SYMBOL_GPL(s3c_i2sv2_get_clock);
558 /* default table of all avaialable root fs divisors */
559 static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
561 int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
563 unsigned int rate, struct clk *clk)
565 unsigned long clkrate = clk_get_rate(clk);
571 signed int deviation = 0;
572 unsigned int best_fs = 0;
573 unsigned int best_div = 0;
574 unsigned int best_rate = 0;
575 unsigned int best_deviation = INT_MAX;
577 pr_debug("Input clock rate %ldHz\n", clkrate);
582 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
583 fsdiv = iis_fs_tab[fs];
585 fsclk = clkrate / fsdiv;
588 if ((fsclk % rate) > (rate / 2))
594 actual = clkrate / (fsdiv * div);
595 deviation = actual - rate;
597 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
598 fsdiv, div, actual, deviation);
600 deviation = abs(deviation);
602 if (deviation < best_deviation) {
606 best_deviation = deviation;
613 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
614 best_fs, best_div, best_rate);
616 info->fs_div = best_fs;
617 info->clk_div = best_div;
621 EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
623 int s3c_i2sv2_probe(struct snd_soc_dai *dai,
624 struct s3c_i2sv2_info *i2s,
627 struct device *dev = dai->dev;
632 /* record our i2s structure for later use in the callbacks */
633 snd_soc_dai_set_drvdata(dai, i2s);
635 i2s->iis_pclk = clk_get(dev, "iis");
636 if (IS_ERR(i2s->iis_pclk)) {
637 dev_err(dev, "failed to get iis_clock\n");
642 clk_enable(i2s->iis_pclk);
644 /* Mark ourselves as in TXRX mode so we can run through our cleanup
645 * process without warnings. */
646 iismod = readl(i2s->regs + S3C2412_IISMOD);
647 iismod |= S3C2412_IISMOD_MODE_TXRX;
648 writel(iismod, i2s->regs + S3C2412_IISMOD);
649 s3c2412_snd_txctrl(i2s, 0);
650 s3c2412_snd_rxctrl(i2s, 0);
654 EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
657 static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
659 struct s3c_i2sv2_info *i2s = to_info(dai);
663 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
664 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
665 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
667 /* some basic suspend checks */
669 iismod = readl(i2s->regs + S3C2412_IISMOD);
671 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
672 pr_warning("%s: RXDMA active?\n", __func__);
674 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
675 pr_warning("%s: TXDMA active?\n", __func__);
677 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
678 pr_warning("%s: IIS active\n", __func__);
684 static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
686 struct s3c_i2sv2_info *i2s = to_info(dai);
688 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
689 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
692 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
693 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
694 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
696 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
697 i2s->regs + S3C2412_IISFIC);
700 writel(0x0, i2s->regs + S3C2412_IISFIC);
706 #define s3c2412_i2s_suspend NULL
707 #define s3c2412_i2s_resume NULL
710 int s3c_i2sv2_register_component(struct device *dev, int id,
711 const struct snd_soc_component_driver *cmp_drv,
712 struct snd_soc_dai_driver *dai_drv)
714 struct snd_soc_dai_ops *ops = (struct snd_soc_dai_ops *)dai_drv->ops;
716 ops->trigger = s3c2412_i2s_trigger;
718 ops->hw_params = s3c_i2sv2_hw_params;
719 ops->set_fmt = s3c2412_i2s_set_fmt;
720 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
721 ops->set_sysclk = s3c_i2sv2_set_sysclk;
723 /* Allow overriding by (for example) IISv4 */
725 ops->delay = s3c2412_i2s_delay;
727 dai_drv->suspend = s3c2412_i2s_suspend;
728 dai_drv->resume = s3c2412_i2s_resume;
730 return devm_snd_soc_register_component(dev, cmp_drv, dai_drv, 1);
732 EXPORT_SYMBOL_GPL(s3c_i2sv2_register_component);
734 MODULE_LICENSE("GPL");