1 /* sound/soc/samsung/i2s.c
3 * ALSA SoC Audio Layer - Samsung I2S Controller driver
5 * Copyright (c) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassisinghbrar@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <dt-bindings/sound/samsung-i2s.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
19 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/pm_runtime.h>
25 #include <sound/soc.h>
26 #include <sound/pcm_params.h>
28 #include <linux/platform_data/asoc-s3c.h>
35 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
37 enum samsung_dai_type {
42 struct samsung_i2s_variant_regs {
47 unsigned int rclksrc_off;
49 unsigned int cdclkcon_off;
51 unsigned int bfs_mask;
52 unsigned int rfs_mask;
53 unsigned int ftx0cnt_off;
56 struct samsung_i2s_dai_data {
59 const struct samsung_i2s_variant_regs *i2s_variant_regs;
63 /* Platform device for this DAI */
64 struct platform_device *pdev;
65 /* Memory mapped SFR region */
67 /* Rate of RCLK source clock */
68 unsigned long rclk_srcrate;
72 * Specifically requested RCLK,BCLK by MACHINE Driver.
73 * 0 indicates CPU driver is free to choose any value.
76 /* I2S Controller's core clock */
78 /* Clock for generating I2S signals */
80 /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
81 struct i2s_dai *pri_dai;
82 /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
83 struct i2s_dai *sec_dai;
84 #define DAI_OPENED (1 << 0) /* Dai is opened */
85 #define DAI_MANAGER (1 << 1) /* Dai is the manager */
87 /* Driver for this DAI */
88 struct snd_soc_dai_driver i2s_dai_drv;
90 struct snd_dmaengine_dai_dma_data dma_playback;
91 struct snd_dmaengine_dai_dma_data dma_capture;
92 struct snd_dmaengine_dai_dma_data idma_playback;
98 const struct samsung_i2s_variant_regs *variant_regs;
100 /* Spinlock protecting access to the device's registers */
104 /* Below fields are only valid if this is the primary FIFO */
105 struct clk *clk_table[3];
106 struct clk_onecell_data clk_data;
109 /* Lock for cross i/f checks */
110 static DEFINE_SPINLOCK(lock);
112 /* If this is the 'overlay' stereo DAI */
113 static inline bool is_secondary(struct i2s_dai *i2s)
115 return i2s->pri_dai ? true : false;
118 /* If operating in SoC-Slave mode */
119 static inline bool is_slave(struct i2s_dai *i2s)
121 u32 mod = readl(i2s->addr + I2SMOD);
122 return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false;
125 /* If this interface of the controller is transmitting data */
126 static inline bool tx_active(struct i2s_dai *i2s)
133 active = readl(i2s->addr + I2SCON);
135 if (is_secondary(i2s))
136 active &= CON_TXSDMA_ACTIVE;
138 active &= CON_TXDMA_ACTIVE;
140 return active ? true : false;
143 /* Return pointer to the other DAI */
144 static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s)
146 return i2s->pri_dai ? : i2s->sec_dai;
149 /* If the other interface of the controller is transmitting data */
150 static inline bool other_tx_active(struct i2s_dai *i2s)
152 struct i2s_dai *other = get_other_dai(i2s);
154 return tx_active(other);
157 /* If any interface of the controller is transmitting data */
158 static inline bool any_tx_active(struct i2s_dai *i2s)
160 return tx_active(i2s) || other_tx_active(i2s);
163 /* If this interface of the controller is receiving data */
164 static inline bool rx_active(struct i2s_dai *i2s)
171 active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE;
173 return active ? true : false;
176 /* If the other interface of the controller is receiving data */
177 static inline bool other_rx_active(struct i2s_dai *i2s)
179 struct i2s_dai *other = get_other_dai(i2s);
181 return rx_active(other);
184 /* If any interface of the controller is receiving data */
185 static inline bool any_rx_active(struct i2s_dai *i2s)
187 return rx_active(i2s) || other_rx_active(i2s);
190 /* If the other DAI is transmitting or receiving data */
191 static inline bool other_active(struct i2s_dai *i2s)
193 return other_rx_active(i2s) || other_tx_active(i2s);
196 /* If this DAI is transmitting or receiving data */
197 static inline bool this_active(struct i2s_dai *i2s)
199 return tx_active(i2s) || rx_active(i2s);
202 /* If the controller is active anyway */
203 static inline bool any_active(struct i2s_dai *i2s)
205 return this_active(i2s) || other_active(i2s);
208 static inline struct i2s_dai *to_info(struct snd_soc_dai *dai)
210 return snd_soc_dai_get_drvdata(dai);
213 static inline bool is_opened(struct i2s_dai *i2s)
215 if (i2s && (i2s->mode & DAI_OPENED))
221 static inline bool is_manager(struct i2s_dai *i2s)
223 if (is_opened(i2s) && (i2s->mode & DAI_MANAGER))
229 /* Read RCLK of I2S (in multiples of LRCLK) */
230 static inline unsigned get_rfs(struct i2s_dai *i2s)
233 rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off;
234 rfs &= i2s->variant_regs->rfs_mask;
248 /* Write RCLK of I2S (in multiples of LRCLK) */
249 static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
251 u32 mod = readl(i2s->addr + I2SMOD);
252 int rfs_shift = i2s->variant_regs->rfs_off;
254 mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift);
258 mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift);
261 mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift);
264 mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift);
267 mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift);
270 mod |= (MOD_RCLK_768FS << rfs_shift);
273 mod |= (MOD_RCLK_512FS << rfs_shift);
276 mod |= (MOD_RCLK_384FS << rfs_shift);
279 mod |= (MOD_RCLK_256FS << rfs_shift);
283 writel(mod, i2s->addr + I2SMOD);
286 /* Read Bit-Clock of I2S (in multiples of LRCLK) */
287 static inline unsigned get_bfs(struct i2s_dai *i2s)
290 bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off;
291 bfs &= i2s->variant_regs->bfs_mask;
306 /* Write Bit-Clock of I2S (in multiples of LRCLK) */
307 static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
309 u32 mod = readl(i2s->addr + I2SMOD);
310 int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM;
311 int bfs_shift = i2s->variant_regs->bfs_off;
313 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */
314 if (!tdm && bfs > 48) {
315 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n");
319 mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift);
323 mod |= (MOD_BCLK_48FS << bfs_shift);
326 mod |= (MOD_BCLK_32FS << bfs_shift);
329 mod |= (MOD_BCLK_24FS << bfs_shift);
332 mod |= (MOD_BCLK_16FS << bfs_shift);
335 mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift);
338 mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift);
341 mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift);
344 mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift);
347 mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift);
350 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n");
354 writel(mod, i2s->addr + I2SMOD);
358 static inline int get_blc(struct i2s_dai *i2s)
360 int blc = readl(i2s->addr + I2SMOD);
362 blc = (blc >> 13) & 0x3;
371 /* TX Channel Control */
372 static void i2s_txctrl(struct i2s_dai *i2s, int on)
374 void __iomem *addr = i2s->addr;
375 int txr_off = i2s->variant_regs->txr_off;
376 u32 con = readl(addr + I2SCON);
377 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
381 con &= ~CON_TXCH_PAUSE;
383 if (is_secondary(i2s)) {
384 con |= CON_TXSDMA_ACTIVE;
385 con &= ~CON_TXSDMA_PAUSE;
387 con |= CON_TXDMA_ACTIVE;
388 con &= ~CON_TXDMA_PAUSE;
391 if (any_rx_active(i2s))
396 if (is_secondary(i2s)) {
397 con |= CON_TXSDMA_PAUSE;
398 con &= ~CON_TXSDMA_ACTIVE;
400 con |= CON_TXDMA_PAUSE;
401 con &= ~CON_TXDMA_ACTIVE;
404 if (other_tx_active(i2s)) {
405 writel(con, addr + I2SCON);
409 con |= CON_TXCH_PAUSE;
411 if (any_rx_active(i2s))
417 writel(mod, addr + I2SMOD);
418 writel(con, addr + I2SCON);
421 /* RX Channel Control */
422 static void i2s_rxctrl(struct i2s_dai *i2s, int on)
424 void __iomem *addr = i2s->addr;
425 int txr_off = i2s->variant_regs->txr_off;
426 u32 con = readl(addr + I2SCON);
427 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
430 con |= CON_RXDMA_ACTIVE | CON_ACTIVE;
431 con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE);
433 if (any_tx_active(i2s))
438 con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE;
439 con &= ~CON_RXDMA_ACTIVE;
441 if (any_tx_active(i2s))
447 writel(mod, addr + I2SMOD);
448 writel(con, addr + I2SCON);
451 /* Flush FIFO of an interface */
452 static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush)
460 if (is_secondary(i2s))
461 fic = i2s->addr + I2SFICS;
463 fic = i2s->addr + I2SFIC;
466 writel(readl(fic) | flush, fic);
469 val = msecs_to_loops(1) / 1000; /* 1 usec */
473 writel(readl(fic) & ~flush, fic);
476 static int i2s_set_sysclk(struct snd_soc_dai *dai,
477 int clk_id, unsigned int rfs, int dir)
479 struct i2s_dai *i2s = to_info(dai);
480 struct i2s_dai *other = get_other_dai(i2s);
481 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
482 unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off;
483 unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off;
484 u32 mod, mask, val = 0;
487 spin_lock_irqsave(i2s->lock, flags);
488 mod = readl(i2s->addr + I2SMOD);
489 spin_unlock_irqrestore(i2s->lock, flags);
492 case SAMSUNG_I2S_OPCLK:
493 mask = MOD_OPCLK_MASK;
496 case SAMSUNG_I2S_CDCLK:
497 mask = 1 << i2s_regs->cdclkcon_off;
498 /* Shouldn't matter in GATING(CLOCK_IN) mode */
499 if (dir == SND_SOC_CLOCK_IN)
502 if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
504 (((dir == SND_SOC_CLOCK_IN)
505 && !(mod & cdcon_mask)) ||
506 ((dir == SND_SOC_CLOCK_OUT)
507 && (mod & cdcon_mask))))) {
508 dev_err(&i2s->pdev->dev,
509 "%s:%d Other DAI busy\n", __func__, __LINE__);
513 if (dir == SND_SOC_CLOCK_IN)
514 val = 1 << i2s_regs->cdclkcon_off;
519 case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */
520 case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */
521 mask = 1 << i2s_regs->rclksrc_off;
523 if ((i2s->quirks & QUIRK_NO_MUXPSR)
524 || (clk_id == SAMSUNG_I2S_RCLKSRC_0))
529 if (!any_active(i2s)) {
530 if (i2s->op_clk && !IS_ERR(i2s->op_clk)) {
531 if ((clk_id && !(mod & rsrc_mask)) ||
532 (!clk_id && (mod & rsrc_mask))) {
533 clk_disable_unprepare(i2s->op_clk);
534 clk_put(i2s->op_clk);
537 clk_get_rate(i2s->op_clk);
543 i2s->op_clk = clk_get(&i2s->pdev->dev,
546 i2s->op_clk = clk_get(&i2s->pdev->dev,
549 if (WARN_ON(IS_ERR(i2s->op_clk)))
550 return PTR_ERR(i2s->op_clk);
552 clk_prepare_enable(i2s->op_clk);
553 i2s->rclk_srcrate = clk_get_rate(i2s->op_clk);
555 /* Over-ride the other's */
557 other->op_clk = i2s->op_clk;
558 other->rclk_srcrate = i2s->rclk_srcrate;
560 } else if ((!clk_id && (mod & rsrc_mask))
561 || (clk_id && !(mod & rsrc_mask))) {
562 dev_err(&i2s->pdev->dev,
563 "%s:%d Other DAI busy\n", __func__, __LINE__);
566 /* Call can't be on the active DAI */
567 i2s->op_clk = other->op_clk;
568 i2s->rclk_srcrate = other->rclk_srcrate;
573 val = 1 << i2s_regs->rclksrc_off;
576 dev_err(&i2s->pdev->dev, "We don't serve that!\n");
580 spin_lock_irqsave(i2s->lock, flags);
581 mod = readl(i2s->addr + I2SMOD);
582 mod = (mod & ~mask) | val;
583 writel(mod, i2s->addr + I2SMOD);
584 spin_unlock_irqrestore(i2s->lock, flags);
589 static int i2s_set_fmt(struct snd_soc_dai *dai,
592 struct i2s_dai *i2s = to_info(dai);
593 int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave;
597 lrp_shift = i2s->variant_regs->lrp_off;
598 sdf_shift = i2s->variant_regs->sdf_off;
599 mod_slave = 1 << i2s->variant_regs->mss_off;
601 sdf_mask = MOD_SDF_MASK << sdf_shift;
602 lrp_rlow = MOD_LR_RLOW << lrp_shift;
604 /* Format is priority */
605 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
606 case SND_SOC_DAIFMT_RIGHT_J:
608 tmp |= (MOD_SDF_MSB << sdf_shift);
610 case SND_SOC_DAIFMT_LEFT_J:
612 tmp |= (MOD_SDF_LSB << sdf_shift);
614 case SND_SOC_DAIFMT_I2S:
615 tmp |= (MOD_SDF_IIS << sdf_shift);
618 dev_err(&i2s->pdev->dev, "Format not supported\n");
623 * INV flag is relative to the FORMAT flag - if set it simply
624 * flips the polarity specified by the Standard
626 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
627 case SND_SOC_DAIFMT_NB_NF:
629 case SND_SOC_DAIFMT_NB_IF:
636 dev_err(&i2s->pdev->dev, "Polarity not supported\n");
640 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
641 case SND_SOC_DAIFMT_CBM_CFM:
644 case SND_SOC_DAIFMT_CBS_CFS:
646 * Set default source clock in Master mode, only when the
647 * CLK_I2S_RCLK_SRC clock is not exposed so we ensure any
648 * clock configuration assigned in DT is not overwritten.
650 if (i2s->rclk_srcrate == 0 && i2s->clk_data.clks == NULL)
651 i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
652 0, SND_SOC_CLOCK_IN);
655 dev_err(&i2s->pdev->dev, "master/slave format not supported\n");
659 spin_lock_irqsave(i2s->lock, flags);
660 mod = readl(i2s->addr + I2SMOD);
662 * Don't change the I2S mode if any controller is active on this
665 if (any_active(i2s) &&
666 ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) {
667 spin_unlock_irqrestore(i2s->lock, flags);
668 dev_err(&i2s->pdev->dev,
669 "%s:%d Other DAI busy\n", __func__, __LINE__);
673 mod &= ~(sdf_mask | lrp_rlow | mod_slave);
675 writel(mod, i2s->addr + I2SMOD);
676 spin_unlock_irqrestore(i2s->lock, flags);
681 static int i2s_hw_params(struct snd_pcm_substream *substream,
682 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
684 struct i2s_dai *i2s = to_info(dai);
685 u32 mod, mask = 0, val = 0;
688 if (!is_secondary(i2s))
689 mask |= (MOD_DC2_EN | MOD_DC1_EN);
691 switch (params_channels(params)) {
698 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
699 i2s->dma_playback.addr_width = 4;
701 i2s->dma_capture.addr_width = 4;
704 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
705 i2s->dma_playback.addr_width = 2;
707 i2s->dma_capture.addr_width = 2;
711 dev_err(&i2s->pdev->dev, "%d channels not supported\n",
712 params_channels(params));
716 if (is_secondary(i2s))
717 mask |= MOD_BLCS_MASK;
719 mask |= MOD_BLCP_MASK;
722 mask |= MOD_BLC_MASK;
724 switch (params_width(params)) {
726 if (is_secondary(i2s))
727 val |= MOD_BLCS_8BIT;
729 val |= MOD_BLCP_8BIT;
734 if (is_secondary(i2s))
735 val |= MOD_BLCS_16BIT;
737 val |= MOD_BLCP_16BIT;
739 val |= MOD_BLC_16BIT;
742 if (is_secondary(i2s))
743 val |= MOD_BLCS_24BIT;
745 val |= MOD_BLCP_24BIT;
747 val |= MOD_BLC_24BIT;
750 dev_err(&i2s->pdev->dev, "Format(%d) not supported\n",
751 params_format(params));
755 spin_lock_irqsave(i2s->lock, flags);
756 mod = readl(i2s->addr + I2SMOD);
757 mod = (mod & ~mask) | val;
758 writel(mod, i2s->addr + I2SMOD);
759 spin_unlock_irqrestore(i2s->lock, flags);
761 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
763 i2s->frmclk = params_rate(params);
768 /* We set constraints on the substream acc to the version of I2S */
769 static int i2s_startup(struct snd_pcm_substream *substream,
770 struct snd_soc_dai *dai)
772 struct i2s_dai *i2s = to_info(dai);
773 struct i2s_dai *other = get_other_dai(i2s);
776 spin_lock_irqsave(&lock, flags);
778 i2s->mode |= DAI_OPENED;
780 if (is_manager(other))
781 i2s->mode &= ~DAI_MANAGER;
783 i2s->mode |= DAI_MANAGER;
785 if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR))
786 writel(CON_RSTCLR, i2s->addr + I2SCON);
788 spin_unlock_irqrestore(&lock, flags);
793 static void i2s_shutdown(struct snd_pcm_substream *substream,
794 struct snd_soc_dai *dai)
796 struct i2s_dai *i2s = to_info(dai);
797 struct i2s_dai *other = get_other_dai(i2s);
800 spin_lock_irqsave(&lock, flags);
802 i2s->mode &= ~DAI_OPENED;
803 i2s->mode &= ~DAI_MANAGER;
805 if (is_opened(other))
806 other->mode |= DAI_MANAGER;
808 /* Reset any constraint on RFS and BFS */
812 spin_unlock_irqrestore(&lock, flags);
815 static int config_setup(struct i2s_dai *i2s)
817 struct i2s_dai *other = get_other_dai(i2s);
818 unsigned rfs, bfs, blc;
828 /* Select least possible multiple(2) if no constraint set */
837 if ((rfs == 256 || rfs == 512) && (blc == 24)) {
838 dev_err(&i2s->pdev->dev,
839 "%d-RFS not supported for 24-blc\n", rfs);
844 if (bfs == 16 || bfs == 32)
850 /* If already setup and running */
851 if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) {
852 dev_err(&i2s->pdev->dev,
853 "%s:%d Other DAI busy\n", __func__, __LINE__);
860 /* Don't bother with PSR in Slave mode */
864 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
865 struct clk *rclksrc = i2s->clk_table[CLK_I2S_RCLK_SRC];
867 if (i2s->rclk_srcrate == 0 && rclksrc && !IS_ERR(rclksrc))
868 i2s->rclk_srcrate = clk_get_rate(rclksrc);
870 psr = i2s->rclk_srcrate / i2s->frmclk / rfs;
871 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR);
872 dev_dbg(&i2s->pdev->dev,
873 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n",
874 i2s->rclk_srcrate, psr, rfs, bfs);
880 static int i2s_trigger(struct snd_pcm_substream *substream,
881 int cmd, struct snd_soc_dai *dai)
883 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
884 struct snd_soc_pcm_runtime *rtd = substream->private_data;
885 struct i2s_dai *i2s = to_info(rtd->cpu_dai);
889 case SNDRV_PCM_TRIGGER_START:
890 case SNDRV_PCM_TRIGGER_RESUME:
891 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
892 spin_lock_irqsave(i2s->lock, flags);
894 if (config_setup(i2s)) {
895 spin_unlock_irqrestore(i2s->lock, flags);
904 spin_unlock_irqrestore(i2s->lock, flags);
906 case SNDRV_PCM_TRIGGER_STOP:
907 case SNDRV_PCM_TRIGGER_SUSPEND:
908 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
909 spin_lock_irqsave(i2s->lock, flags);
913 i2s_fifo(i2s, FIC_RXFLUSH);
916 i2s_fifo(i2s, FIC_TXFLUSH);
919 spin_unlock_irqrestore(i2s->lock, flags);
926 static int i2s_set_clkdiv(struct snd_soc_dai *dai,
929 struct i2s_dai *i2s = to_info(dai);
930 struct i2s_dai *other = get_other_dai(i2s);
933 case SAMSUNG_I2S_DIV_BCLK:
934 if ((any_active(i2s) && div && (get_bfs(i2s) != div))
935 || (other && other->bfs && (other->bfs != div))) {
936 dev_err(&i2s->pdev->dev,
937 "%s:%d Other DAI busy\n", __func__, __LINE__);
943 dev_err(&i2s->pdev->dev,
944 "Invalid clock divider(%d)\n", div_id);
951 static snd_pcm_sframes_t
952 i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
954 struct i2s_dai *i2s = to_info(dai);
955 u32 reg = readl(i2s->addr + I2SFIC);
956 snd_pcm_sframes_t delay;
957 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
959 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
960 delay = FIC_RXCOUNT(reg);
961 else if (is_secondary(i2s))
962 delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS));
964 delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f;
970 static int i2s_suspend(struct snd_soc_dai *dai)
972 struct i2s_dai *i2s = to_info(dai);
974 i2s->suspend_i2smod = readl(i2s->addr + I2SMOD);
975 i2s->suspend_i2scon = readl(i2s->addr + I2SCON);
976 i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR);
981 static int i2s_resume(struct snd_soc_dai *dai)
983 struct i2s_dai *i2s = to_info(dai);
985 writel(i2s->suspend_i2scon, i2s->addr + I2SCON);
986 writel(i2s->suspend_i2smod, i2s->addr + I2SMOD);
987 writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR);
992 #define i2s_suspend NULL
993 #define i2s_resume NULL
996 static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
998 struct i2s_dai *i2s = to_info(dai);
999 struct i2s_dai *other = get_other_dai(i2s);
1000 unsigned long flags;
1002 if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */
1003 snd_soc_dai_init_dma_data(dai, &other->sec_dai->dma_playback,
1006 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback,
1009 if (i2s->quirks & QUIRK_NEED_RSTCLR)
1010 writel(CON_RSTCLR, i2s->addr + I2SCON);
1012 if (i2s->quirks & QUIRK_SUPPORTS_IDMA)
1013 idma_reg_addr_init(i2s->addr,
1014 i2s->sec_dai->idma_playback.addr);
1017 /* Reset any constraint on RFS and BFS */
1020 i2s->rclk_srcrate = 0;
1022 spin_lock_irqsave(i2s->lock, flags);
1025 i2s_fifo(i2s, FIC_TXFLUSH);
1026 i2s_fifo(other, FIC_TXFLUSH);
1027 i2s_fifo(i2s, FIC_RXFLUSH);
1028 spin_unlock_irqrestore(i2s->lock, flags);
1030 /* Gate CDCLK by default */
1031 if (!is_opened(other))
1032 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
1033 0, SND_SOC_CLOCK_IN);
1038 static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
1040 struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai);
1041 unsigned long flags;
1043 if (!is_secondary(i2s)) {
1044 if (i2s->quirks & QUIRK_NEED_RSTCLR) {
1045 spin_lock_irqsave(i2s->lock, flags);
1046 writel(0, i2s->addr + I2SCON);
1047 spin_unlock_irqrestore(i2s->lock, flags);
1054 static const struct snd_soc_dai_ops samsung_i2s_dai_ops = {
1055 .trigger = i2s_trigger,
1056 .hw_params = i2s_hw_params,
1057 .set_fmt = i2s_set_fmt,
1058 .set_clkdiv = i2s_set_clkdiv,
1059 .set_sysclk = i2s_set_sysclk,
1060 .startup = i2s_startup,
1061 .shutdown = i2s_shutdown,
1065 static const struct snd_soc_component_driver samsung_i2s_component = {
1066 .name = "samsung-i2s",
1069 #define SAMSUNG_I2S_RATES SNDRV_PCM_RATE_8000_96000
1071 #define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1072 SNDRV_PCM_FMTBIT_S16_LE | \
1073 SNDRV_PCM_FMTBIT_S24_LE)
1075 static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev, bool sec)
1077 struct i2s_dai *i2s;
1080 i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL);
1085 i2s->pri_dai = NULL;
1086 i2s->sec_dai = NULL;
1087 i2s->i2s_dai_drv.symmetric_rates = 1;
1088 i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe;
1089 i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove;
1090 i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops;
1091 i2s->i2s_dai_drv.suspend = i2s_suspend;
1092 i2s->i2s_dai_drv.resume = i2s_resume;
1093 i2s->i2s_dai_drv.playback.channels_min = 1;
1094 i2s->i2s_dai_drv.playback.channels_max = 2;
1095 i2s->i2s_dai_drv.playback.rates = SAMSUNG_I2S_RATES;
1096 i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS;
1099 i2s->i2s_dai_drv.capture.channels_min = 1;
1100 i2s->i2s_dai_drv.capture.channels_max = 2;
1101 i2s->i2s_dai_drv.capture.rates = SAMSUNG_I2S_RATES;
1102 i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS;
1103 dev_set_drvdata(&i2s->pdev->dev, i2s);
1104 } else { /* Create a new platform_device for Secondary */
1105 i2s->pdev = platform_device_alloc("samsung-i2s-sec", -1);
1109 i2s->pdev->dev.parent = &pdev->dev;
1111 platform_set_drvdata(i2s->pdev, i2s);
1112 ret = platform_device_add(i2s->pdev);
1120 static void i2s_free_sec_dai(struct i2s_dai *i2s)
1122 platform_device_del(i2s->pdev);
1126 static int i2s_runtime_suspend(struct device *dev)
1128 struct i2s_dai *i2s = dev_get_drvdata(dev);
1130 clk_disable_unprepare(i2s->clk);
1135 static int i2s_runtime_resume(struct device *dev)
1137 struct i2s_dai *i2s = dev_get_drvdata(dev);
1139 clk_prepare_enable(i2s->clk);
1143 #endif /* CONFIG_PM */
1145 static void i2s_unregister_clocks(struct i2s_dai *i2s)
1149 for (i = 0; i < i2s->clk_data.clk_num; i++) {
1150 if (!IS_ERR(i2s->clk_table[i]))
1151 clk_unregister(i2s->clk_table[i]);
1155 static void i2s_unregister_clock_provider(struct platform_device *pdev)
1157 struct i2s_dai *i2s = dev_get_drvdata(&pdev->dev);
1159 of_clk_del_provider(pdev->dev.of_node);
1160 i2s_unregister_clocks(i2s);
1163 static int i2s_register_clock_provider(struct platform_device *pdev)
1165 struct device *dev = &pdev->dev;
1166 struct i2s_dai *i2s = dev_get_drvdata(dev);
1167 const char *clk_name[2] = { "i2s_opclk0", "i2s_opclk1" };
1168 const char *p_names[2] = { NULL };
1169 const struct samsung_i2s_variant_regs *reg_info = i2s->variant_regs;
1170 struct clk *rclksrc;
1173 /* Register the clock provider only if it's expected in the DTB */
1174 if (!of_find_property(dev->of_node, "#clock-cells", NULL))
1177 /* Get the RCLKSRC mux clock parent clock names */
1178 for (i = 0; i < ARRAY_SIZE(p_names); i++) {
1179 rclksrc = clk_get(dev, clk_name[i]);
1180 if (IS_ERR(rclksrc))
1182 p_names[i] = __clk_get_name(rclksrc);
1186 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
1187 /* Activate the prescaler */
1188 u32 val = readl(i2s->addr + I2SPSR);
1189 writel(val | PSR_PSREN, i2s->addr + I2SPSR);
1191 i2s->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(NULL,
1192 "i2s_rclksrc", p_names, ARRAY_SIZE(p_names),
1193 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
1194 i2s->addr + I2SMOD, reg_info->rclksrc_off,
1197 i2s->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(NULL,
1198 "i2s_presc", "i2s_rclksrc",
1199 CLK_SET_RATE_PARENT,
1200 i2s->addr + I2SPSR, 8, 6, 0, i2s->lock);
1202 p_names[0] = "i2s_presc";
1203 i2s->clk_data.clk_num = 2;
1205 of_property_read_string_index(dev->of_node,
1206 "clock-output-names", 0, &clk_name[0]);
1208 i2s->clk_table[CLK_I2S_CDCLK] = clk_register_gate(NULL, clk_name[0],
1209 p_names[0], CLK_SET_RATE_PARENT,
1210 i2s->addr + I2SMOD, reg_info->cdclkcon_off,
1211 CLK_GATE_SET_TO_DISABLE, i2s->lock);
1213 i2s->clk_data.clk_num += 1;
1214 i2s->clk_data.clks = i2s->clk_table;
1216 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
1219 dev_err(dev, "failed to add clock provider: %d\n", ret);
1220 i2s_unregister_clocks(i2s);
1226 static int samsung_i2s_probe(struct platform_device *pdev)
1228 struct i2s_dai *pri_dai, *sec_dai = NULL;
1229 struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data;
1230 struct samsung_i2s *i2s_cfg = NULL;
1231 struct resource *res;
1232 u32 regs_base, quirks = 0, idma_addr = 0;
1233 struct device_node *np = pdev->dev.of_node;
1234 const struct samsung_i2s_dai_data *i2s_dai_data;
1237 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
1238 i2s_dai_data = of_device_get_match_data(&pdev->dev);
1240 i2s_dai_data = (struct samsung_i2s_dai_data *)
1241 platform_get_device_id(pdev)->driver_data;
1243 /* Call during the secondary interface registration */
1244 if (i2s_dai_data->dai_type == TYPE_SEC) {
1245 sec_dai = dev_get_drvdata(&pdev->dev);
1247 dev_err(&pdev->dev, "Unable to get drvdata\n");
1250 ret = samsung_asoc_dma_platform_register(&pdev->dev,
1251 sec_dai->filter, "tx-sec", NULL);
1255 return devm_snd_soc_register_component(&sec_dai->pdev->dev,
1256 &samsung_i2s_component,
1257 &sec_dai->i2s_dai_drv, 1);
1260 pri_dai = i2s_alloc_dai(pdev, false);
1262 dev_err(&pdev->dev, "Unable to alloc I2S_pri\n");
1266 spin_lock_init(&pri_dai->spinlock);
1267 pri_dai->lock = &pri_dai->spinlock;
1270 if (i2s_pdata == NULL) {
1271 dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n");
1275 pri_dai->dma_playback.filter_data = i2s_pdata->dma_playback;
1276 pri_dai->dma_capture.filter_data = i2s_pdata->dma_capture;
1277 pri_dai->filter = i2s_pdata->dma_filter;
1279 if (&i2s_pdata->type)
1280 i2s_cfg = &i2s_pdata->type.i2s;
1283 quirks = i2s_cfg->quirks;
1284 idma_addr = i2s_cfg->idma_addr;
1287 quirks = i2s_dai_data->quirks;
1288 if (of_property_read_u32(np, "samsung,idma-addr",
1290 if (quirks & QUIRK_SUPPORTS_IDMA) {
1291 dev_info(&pdev->dev, "idma address is not"\
1297 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1298 pri_dai->addr = devm_ioremap_resource(&pdev->dev, res);
1299 if (IS_ERR(pri_dai->addr))
1300 return PTR_ERR(pri_dai->addr);
1302 regs_base = res->start;
1304 pri_dai->clk = devm_clk_get(&pdev->dev, "iis");
1305 if (IS_ERR(pri_dai->clk)) {
1306 dev_err(&pdev->dev, "Failed to get iis clock\n");
1307 return PTR_ERR(pri_dai->clk);
1310 ret = clk_prepare_enable(pri_dai->clk);
1312 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
1315 pri_dai->dma_playback.addr = regs_base + I2STXD;
1316 pri_dai->dma_capture.addr = regs_base + I2SRXD;
1317 pri_dai->dma_playback.chan_name = "tx";
1318 pri_dai->dma_capture.chan_name = "rx";
1319 pri_dai->dma_playback.addr_width = 4;
1320 pri_dai->dma_capture.addr_width = 4;
1321 pri_dai->quirks = quirks;
1322 pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs;
1324 if (quirks & QUIRK_PRI_6CHAN)
1325 pri_dai->i2s_dai_drv.playback.channels_max = 6;
1327 ret = samsung_asoc_dma_platform_register(&pdev->dev, pri_dai->filter,
1330 goto err_disable_clk;
1332 if (quirks & QUIRK_SEC_DAI) {
1333 sec_dai = i2s_alloc_dai(pdev, true);
1335 dev_err(&pdev->dev, "Unable to alloc I2S_sec\n");
1337 goto err_disable_clk;
1340 sec_dai->lock = &pri_dai->spinlock;
1341 sec_dai->variant_regs = pri_dai->variant_regs;
1342 sec_dai->dma_playback.addr = regs_base + I2STXDS;
1343 sec_dai->dma_playback.chan_name = "tx-sec";
1346 sec_dai->dma_playback.filter_data = i2s_pdata->dma_play_sec;
1347 sec_dai->filter = i2s_pdata->dma_filter;
1350 sec_dai->dma_playback.addr_width = 4;
1351 sec_dai->addr = pri_dai->addr;
1352 sec_dai->clk = pri_dai->clk;
1353 sec_dai->quirks = quirks;
1354 sec_dai->idma_playback.addr = idma_addr;
1355 sec_dai->pri_dai = pri_dai;
1356 pri_dai->sec_dai = sec_dai;
1359 if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
1360 dev_err(&pdev->dev, "Unable to configure gpio\n");
1362 goto err_disable_clk;
1365 ret = devm_snd_soc_register_component(&pri_dai->pdev->dev,
1366 &samsung_i2s_component,
1367 &pri_dai->i2s_dai_drv, 1);
1372 pm_runtime_enable(&pdev->dev);
1374 ret = i2s_register_clock_provider(pdev);
1378 pm_runtime_disable(&pdev->dev);
1381 i2s_free_sec_dai(sec_dai);
1383 clk_disable_unprepare(pri_dai->clk);
1387 static int samsung_i2s_remove(struct platform_device *pdev)
1389 struct i2s_dai *i2s, *other;
1391 i2s = dev_get_drvdata(&pdev->dev);
1392 other = get_other_dai(i2s);
1395 other->pri_dai = NULL;
1396 other->sec_dai = NULL;
1398 pm_runtime_disable(&pdev->dev);
1401 if (!is_secondary(i2s)) {
1402 i2s_unregister_clock_provider(pdev);
1403 clk_disable_unprepare(i2s->clk);
1406 i2s->pri_dai = NULL;
1407 i2s->sec_dai = NULL;
1412 static const struct samsung_i2s_variant_regs i2sv3_regs = {
1426 static const struct samsung_i2s_variant_regs i2sv6_regs = {
1440 static const struct samsung_i2s_variant_regs i2sv7_regs = {
1454 static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = {
1468 static const struct samsung_i2s_dai_data i2sv3_dai_type = {
1469 .dai_type = TYPE_PRI,
1470 .quirks = QUIRK_NO_MUXPSR,
1471 .i2s_variant_regs = &i2sv3_regs,
1474 static const struct samsung_i2s_dai_data i2sv5_dai_type = {
1475 .dai_type = TYPE_PRI,
1476 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1477 QUIRK_SUPPORTS_IDMA,
1478 .i2s_variant_regs = &i2sv3_regs,
1481 static const struct samsung_i2s_dai_data i2sv6_dai_type = {
1482 .dai_type = TYPE_PRI,
1483 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1484 QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
1485 .i2s_variant_regs = &i2sv6_regs,
1488 static const struct samsung_i2s_dai_data i2sv7_dai_type = {
1489 .dai_type = TYPE_PRI,
1490 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1492 .i2s_variant_regs = &i2sv7_regs,
1495 static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = {
1496 .dai_type = TYPE_PRI,
1497 .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR,
1498 .i2s_variant_regs = &i2sv5_i2s1_regs,
1501 static const struct samsung_i2s_dai_data samsung_dai_type_sec = {
1502 .dai_type = TYPE_SEC,
1505 static const struct platform_device_id samsung_i2s_driver_ids[] = {
1507 .name = "samsung-i2s",
1508 .driver_data = (kernel_ulong_t)&i2sv3_dai_type,
1510 .name = "samsung-i2s-sec",
1511 .driver_data = (kernel_ulong_t)&samsung_dai_type_sec,
1515 MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids);
1518 static const struct of_device_id exynos_i2s_match[] = {
1520 .compatible = "samsung,s3c6410-i2s",
1521 .data = &i2sv3_dai_type,
1523 .compatible = "samsung,s5pv210-i2s",
1524 .data = &i2sv5_dai_type,
1526 .compatible = "samsung,exynos5420-i2s",
1527 .data = &i2sv6_dai_type,
1529 .compatible = "samsung,exynos7-i2s",
1530 .data = &i2sv7_dai_type,
1532 .compatible = "samsung,exynos7-i2s1",
1533 .data = &i2sv5_dai_type_i2s1,
1537 MODULE_DEVICE_TABLE(of, exynos_i2s_match);
1540 static const struct dev_pm_ops samsung_i2s_pm = {
1541 SET_RUNTIME_PM_OPS(i2s_runtime_suspend,
1542 i2s_runtime_resume, NULL)
1545 static struct platform_driver samsung_i2s_driver = {
1546 .probe = samsung_i2s_probe,
1547 .remove = samsung_i2s_remove,
1548 .id_table = samsung_i2s_driver_ids,
1550 .name = "samsung-i2s",
1551 .of_match_table = of_match_ptr(exynos_i2s_match),
1552 .pm = &samsung_i2s_pm,
1556 module_platform_driver(samsung_i2s_driver);
1558 /* Module information */
1559 MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
1560 MODULE_DESCRIPTION("Samsung I2S Interface");
1561 MODULE_ALIAS("platform:samsung-i2s");
1562 MODULE_LICENSE("GPL");