1 /* sound/soc/rockchip/rk_spdif.c
3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6 * Author: Jianqun <jay.xu@rock-chips.com>
7 * Copyright (c) 2015 Collabora Ltd.
8 * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/of_gpio.h>
18 #include <linux/clk.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/regmap.h>
22 #include <sound/pcm_params.h>
23 #include <sound/dmaengine_pcm.h>
25 #include "rockchip_spdif.h"
34 #define RK3288_GRF_SOC_CON2 0x24c
42 struct snd_dmaengine_dai_dma_data playback_dma_data;
44 struct regmap *regmap;
47 static const struct of_device_id rk_spdif_match[] = {
48 { .compatible = "rockchip,rk3066-spdif",
49 .data = (void *)RK_SPDIF_RK3066 },
50 { .compatible = "rockchip,rk3188-spdif",
51 .data = (void *)RK_SPDIF_RK3188 },
52 { .compatible = "rockchip,rk3288-spdif",
53 .data = (void *)RK_SPDIF_RK3288 },
54 { .compatible = "rockchip,rk3366-spdif",
55 .data = (void *)RK_SPDIF_RK3366 },
56 { .compatible = "rockchip,rk3368-spdif",
57 .data = (void *)RK_SPDIF_RK3366 },
58 { .compatible = "rockchip,rk3399-spdif",
59 .data = (void *)RK_SPDIF_RK3366 },
62 MODULE_DEVICE_TABLE(of, rk_spdif_match);
64 static int __maybe_unused rk_spdif_runtime_suspend(struct device *dev)
66 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
68 regcache_cache_only(spdif->regmap, true);
69 clk_disable_unprepare(spdif->mclk);
70 clk_disable_unprepare(spdif->hclk);
75 static int __maybe_unused rk_spdif_runtime_resume(struct device *dev)
77 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
80 ret = clk_prepare_enable(spdif->mclk);
82 dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
86 ret = clk_prepare_enable(spdif->hclk);
88 dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
92 regcache_cache_only(spdif->regmap, false);
93 regcache_mark_dirty(spdif->regmap);
95 ret = regcache_sync(spdif->regmap);
97 clk_disable_unprepare(spdif->mclk);
98 clk_disable_unprepare(spdif->hclk);
104 static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
105 struct snd_pcm_hw_params *params,
106 struct snd_soc_dai *dai)
108 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
109 unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
113 srate = params_rate(params);
116 switch (params_format(params)) {
117 case SNDRV_PCM_FORMAT_S16_LE:
118 val |= SPDIF_CFGR_VDW_16;
120 case SNDRV_PCM_FORMAT_S20_3LE:
121 val |= SPDIF_CFGR_VDW_20;
123 case SNDRV_PCM_FORMAT_S24_LE:
124 val |= SPDIF_CFGR_VDW_24;
130 /* Set clock and calculate divider */
131 ret = clk_set_rate(spdif->mclk, mclk);
133 dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
138 ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
139 SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE |
146 static int rk_spdif_trigger(struct snd_pcm_substream *substream,
147 int cmd, struct snd_soc_dai *dai)
149 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
153 case SNDRV_PCM_TRIGGER_START:
154 case SNDRV_PCM_TRIGGER_RESUME:
155 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
156 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
157 SPDIF_DMACR_TDE_ENABLE |
158 SPDIF_DMACR_TDL_MASK,
159 SPDIF_DMACR_TDE_ENABLE |
160 SPDIF_DMACR_TDL(16));
165 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
166 SPDIF_XFER_TXS_START,
167 SPDIF_XFER_TXS_START);
169 case SNDRV_PCM_TRIGGER_SUSPEND:
170 case SNDRV_PCM_TRIGGER_STOP:
171 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
172 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
173 SPDIF_DMACR_TDE_ENABLE,
174 SPDIF_DMACR_TDE_DISABLE);
179 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
180 SPDIF_XFER_TXS_START,
181 SPDIF_XFER_TXS_STOP);
191 static int rk_spdif_dai_probe(struct snd_soc_dai *dai)
193 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
195 dai->playback_dma_data = &spdif->playback_dma_data;
200 static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
201 .hw_params = rk_spdif_hw_params,
202 .trigger = rk_spdif_trigger,
205 static struct snd_soc_dai_driver rk_spdif_dai = {
206 .probe = rk_spdif_dai_probe,
208 .stream_name = "Playback",
211 .rates = (SNDRV_PCM_RATE_32000 |
212 SNDRV_PCM_RATE_44100 |
213 SNDRV_PCM_RATE_48000 |
214 SNDRV_PCM_RATE_96000 |
215 SNDRV_PCM_RATE_192000),
216 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
217 SNDRV_PCM_FMTBIT_S20_3LE |
218 SNDRV_PCM_FMTBIT_S24_LE),
220 .ops = &rk_spdif_dai_ops,
223 static const struct snd_soc_component_driver rk_spdif_component = {
224 .name = "rockchip-spdif",
227 static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
241 static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
255 static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg)
266 static const struct regmap_config rk_spdif_regmap_config = {
270 .max_register = SPDIF_SMPDR,
271 .writeable_reg = rk_spdif_wr_reg,
272 .readable_reg = rk_spdif_rd_reg,
273 .volatile_reg = rk_spdif_volatile_reg,
274 .cache_type = REGCACHE_FLAT,
277 static int rk_spdif_probe(struct platform_device *pdev)
279 struct device_node *np = pdev->dev.of_node;
280 struct rk_spdif_dev *spdif;
281 const struct of_device_id *match;
282 struct resource *res;
286 match = of_match_node(rk_spdif_match, np);
287 if (match->data == (void *)RK_SPDIF_RK3288) {
290 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
293 "rockchip_spdif missing 'rockchip,grf' \n");
297 /* Select the 8 channel SPDIF solution on RK3288 as
298 * the 2 channel one does not appear to work
300 regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16);
303 spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
307 spdif->hclk = devm_clk_get(&pdev->dev, "hclk");
308 if (IS_ERR(spdif->hclk)) {
309 dev_err(&pdev->dev, "Can't retrieve rk_spdif bus clock\n");
310 return PTR_ERR(spdif->hclk);
312 ret = clk_prepare_enable(spdif->hclk);
314 dev_err(spdif->dev, "hclock enable failed %d\n", ret);
318 spdif->mclk = devm_clk_get(&pdev->dev, "mclk");
319 if (IS_ERR(spdif->mclk)) {
320 dev_err(&pdev->dev, "Can't retrieve rk_spdif master clock\n");
321 ret = PTR_ERR(spdif->mclk);
322 goto err_disable_hclk;
325 ret = clk_prepare_enable(spdif->mclk);
327 dev_err(spdif->dev, "clock enable failed %d\n", ret);
328 goto err_disable_clocks;
331 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
332 regs = devm_ioremap_resource(&pdev->dev, res);
335 goto err_disable_clocks;
338 spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,
339 &rk_spdif_regmap_config);
340 if (IS_ERR(spdif->regmap)) {
342 "Failed to initialise managed register map\n");
343 ret = PTR_ERR(spdif->regmap);
344 goto err_disable_clocks;
347 spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
348 spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
349 spdif->playback_dma_data.maxburst = 4;
351 spdif->dev = &pdev->dev;
352 dev_set_drvdata(&pdev->dev, spdif);
354 pm_runtime_set_active(&pdev->dev);
355 pm_runtime_enable(&pdev->dev);
356 pm_request_idle(&pdev->dev);
358 ret = devm_snd_soc_register_component(&pdev->dev,
362 dev_err(&pdev->dev, "Could not register DAI\n");
366 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
368 dev_err(&pdev->dev, "Could not register PCM\n");
375 pm_runtime_disable(&pdev->dev);
377 clk_disable_unprepare(spdif->mclk);
379 clk_disable_unprepare(spdif->hclk);
384 static int rk_spdif_remove(struct platform_device *pdev)
386 struct rk_spdif_dev *spdif = dev_get_drvdata(&pdev->dev);
388 pm_runtime_disable(&pdev->dev);
389 if (!pm_runtime_status_suspended(&pdev->dev))
390 rk_spdif_runtime_suspend(&pdev->dev);
392 clk_disable_unprepare(spdif->mclk);
393 clk_disable_unprepare(spdif->hclk);
398 static const struct dev_pm_ops rk_spdif_pm_ops = {
399 SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume,
403 static struct platform_driver rk_spdif_driver = {
404 .probe = rk_spdif_probe,
405 .remove = rk_spdif_remove,
407 .name = "rockchip-spdif",
408 .of_match_table = of_match_ptr(rk_spdif_match),
409 .pm = &rk_spdif_pm_ops,
412 module_platform_driver(rk_spdif_driver);
414 MODULE_ALIAS("platform:rockchip-spdif");
415 MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
416 MODULE_AUTHOR("Sjoerd Simons <sjoerd.simons@collabora.co.uk>");
417 MODULE_LICENSE("GPL v2");