1 // SPDX-License-Identifier: GPL-2.0-only
2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
4 // Copyright (c) 2018 Rockchip Electronics Co. Ltd.
5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
6 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
17 #include <linux/spinlock.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm_params.h>
21 #include "rockchip_i2s_tdm.h"
23 #define DRV_NAME "rockchip-i2s-tdm"
25 #define DEFAULT_MCLK_FS 256
26 #define CH_GRP_MAX 4 /* The max channel 8 / 2 */
27 #define MULTIPLEX_CH_MAX 10
28 #define CLK_PPM_MIN -1000
29 #define CLK_PPM_MAX 1000
42 struct rk_i2s_soc_data {
47 const struct txrx_config *configs;
48 int (*init)(struct device *dev, u32 addr);
51 struct rk_i2s_tdm_dev {
56 /* The mclk_tx_src is parent of mclk_tx */
57 struct clk *mclk_tx_src;
58 /* The mclk_rx_src is parent of mclk_rx */
59 struct clk *mclk_rx_src;
61 * The mclk_root0 and mclk_root1 are root parent and supplies for
65 * mclk_root0 is VPLL0, used for FS=48000Hz
66 * mclk_root1 is VPLL1, used for FS=44100Hz
68 struct clk *mclk_root0;
69 struct clk *mclk_root1;
70 struct regmap *regmap;
72 struct snd_dmaengine_dai_dma_data capture_dma_data;
73 struct snd_dmaengine_dai_dma_data playback_dma_data;
74 struct reset_control *tx_reset;
75 struct reset_control *rx_reset;
76 const struct rk_i2s_soc_data *soc_data;
81 unsigned int mclk_rx_freq;
82 unsigned int mclk_tx_freq;
83 unsigned int mclk_root0_freq;
84 unsigned int mclk_root1_freq;
85 unsigned int mclk_root0_initial_freq;
86 unsigned int mclk_root1_initial_freq;
87 unsigned int frame_width;
88 unsigned int clk_trcm;
89 unsigned int i2s_sdis[CH_GRP_MAX];
90 unsigned int i2s_sdos[CH_GRP_MAX];
93 spinlock_t lock; /* xfer lock */
96 struct snd_soc_dai_driver *dai;
99 static int to_ch_num(unsigned int val)
113 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
115 clk_disable_unprepare(i2s_tdm->mclk_tx);
116 clk_disable_unprepare(i2s_tdm->mclk_rx);
117 if (i2s_tdm->mclk_calibrate) {
118 clk_disable_unprepare(i2s_tdm->mclk_tx_src);
119 clk_disable_unprepare(i2s_tdm->mclk_rx_src);
120 clk_disable_unprepare(i2s_tdm->mclk_root0);
121 clk_disable_unprepare(i2s_tdm->mclk_root1);
126 * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
128 * @i2s_tdm: rk_i2s_tdm_dev struct
130 * This function attempts to enable all mclk clocks, but cleans up after
131 * itself on failure. Guarantees to balance its calls.
133 * Returns success (0) or negative errno.
135 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
139 ret = clk_prepare_enable(i2s_tdm->mclk_tx);
142 ret = clk_prepare_enable(i2s_tdm->mclk_rx);
145 if (i2s_tdm->mclk_calibrate) {
146 ret = clk_prepare_enable(i2s_tdm->mclk_tx_src);
149 ret = clk_prepare_enable(i2s_tdm->mclk_rx_src);
151 goto err_mclk_rx_src;
152 ret = clk_prepare_enable(i2s_tdm->mclk_root0);
155 ret = clk_prepare_enable(i2s_tdm->mclk_root1);
163 clk_disable_unprepare(i2s_tdm->mclk_root0);
165 clk_disable_unprepare(i2s_tdm->mclk_rx_src);
167 clk_disable_unprepare(i2s_tdm->mclk_tx_src);
169 clk_disable_unprepare(i2s_tdm->mclk_tx);
174 static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev)
176 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
178 regcache_cache_only(i2s_tdm->regmap, true);
179 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
181 clk_disable_unprepare(i2s_tdm->hclk);
186 static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev)
188 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
191 ret = clk_prepare_enable(i2s_tdm->hclk);
195 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
199 regcache_cache_only(i2s_tdm->regmap, false);
200 regcache_mark_dirty(i2s_tdm->regmap);
202 ret = regcache_sync(i2s_tdm->regmap);
209 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
211 clk_disable_unprepare(i2s_tdm->hclk);
216 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
218 return snd_soc_dai_get_drvdata(dai);
222 * Makes sure that both tx and rx are reset at the same time to sync lrck
225 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
227 /* This is technically race-y.
229 * In an ideal world, we could atomically assert both resets at the
230 * same time, through an atomic bulk reset API. This API however does
231 * not exist, so what the downstream vendor code used to do was
232 * implement half a reset controller here and require the CRU to be
233 * passed to the driver as a device tree node. Violating abstractions
234 * like that is bad, especially when it influences something like the
235 * bindings which are supposed to describe the hardware, not whatever
236 * workarounds the driver needs, so it was dropped.
238 * In practice, asserting the resets one by one appears to work just
239 * fine for playback. During duplex (playback + capture) operation,
240 * this might become an issue, but that should be solved by the
241 * implementation of the aforementioned API, not by shoving a reset
242 * controller into an audio driver.
245 reset_control_assert(i2s_tdm->tx_reset);
246 reset_control_assert(i2s_tdm->rx_reset);
248 reset_control_deassert(i2s_tdm->tx_reset);
249 reset_control_deassert(i2s_tdm->rx_reset);
253 static void rockchip_snd_reset(struct reset_control *rc)
255 reset_control_assert(rc);
257 reset_control_deassert(rc);
261 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm,
264 unsigned int xfer_mask = 0;
265 unsigned int xfer_val = 0;
268 bool tx = clr & I2S_CLR_TXC;
269 bool rx = clr & I2S_CLR_RXC;
275 xfer_mask = I2S_XFER_TXS_START;
276 xfer_val = I2S_XFER_TXS_STOP;
279 xfer_mask |= I2S_XFER_RXS_START;
280 xfer_val |= I2S_XFER_RXS_STOP;
283 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val);
285 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
287 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
288 /* Wait on the clear operation to finish */
291 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
294 dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n",
295 tx ? "tx" : "", rx ? "rx" : "");
297 rockchip_snd_xfer_sync_reset(i2s_tdm);
299 rockchip_snd_reset(i2s_tdm->tx_reset);
301 rockchip_snd_reset(i2s_tdm->rx_reset);
307 static inline void rockchip_enable_tde(struct regmap *regmap)
309 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
310 I2S_DMACR_TDE_ENABLE);
313 static inline void rockchip_disable_tde(struct regmap *regmap)
315 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
316 I2S_DMACR_TDE_DISABLE);
319 static inline void rockchip_enable_rde(struct regmap *regmap)
321 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
322 I2S_DMACR_RDE_ENABLE);
325 static inline void rockchip_disable_rde(struct regmap *regmap)
327 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
328 I2S_DMACR_RDE_DISABLE);
331 /* only used when clk_trcm > 0 */
332 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
333 struct snd_soc_dai *dai, int on)
335 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
338 spin_lock_irqsave(&i2s_tdm->lock, flags);
340 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
341 rockchip_enable_tde(i2s_tdm->regmap);
343 rockchip_enable_rde(i2s_tdm->regmap);
345 if (++i2s_tdm->refcount == 1) {
346 rockchip_snd_xfer_sync_reset(i2s_tdm);
347 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
354 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
355 rockchip_disable_tde(i2s_tdm->regmap);
357 rockchip_disable_rde(i2s_tdm->regmap);
359 if (--i2s_tdm->refcount == 0) {
360 rockchip_snd_xfer_clear(i2s_tdm,
361 I2S_CLR_TXC | I2S_CLR_RXC);
364 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
367 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
370 rockchip_enable_tde(i2s_tdm->regmap);
372 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
376 rockchip_disable_tde(i2s_tdm->regmap);
378 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC);
382 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
385 rockchip_enable_rde(i2s_tdm->regmap);
387 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
391 rockchip_disable_rde(i2s_tdm->regmap);
393 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC);
397 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
400 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
401 unsigned int mask, val, tdm_val, txcr_val, rxcr_val;
403 bool is_tdm = i2s_tdm->tdm_mode;
405 ret = pm_runtime_resume_and_get(cpu_dai->dev);
406 if (ret < 0 && ret != -EACCES)
409 mask = I2S_CKR_MSS_MASK;
410 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
411 case SND_SOC_DAIFMT_BP_FP:
412 val = I2S_CKR_MSS_MASTER;
413 i2s_tdm->is_master_mode = true;
415 case SND_SOC_DAIFMT_BC_FC:
416 val = I2S_CKR_MSS_SLAVE;
417 i2s_tdm->is_master_mode = false;
424 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
426 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
427 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
428 case SND_SOC_DAIFMT_NB_NF:
429 val = I2S_CKR_CKP_NORMAL |
433 case SND_SOC_DAIFMT_NB_IF:
434 val = I2S_CKR_CKP_NORMAL |
435 I2S_CKR_TLP_INVERTED |
436 I2S_CKR_RLP_INVERTED;
438 case SND_SOC_DAIFMT_IB_NF:
439 val = I2S_CKR_CKP_INVERTED |
443 case SND_SOC_DAIFMT_IB_IF:
444 val = I2S_CKR_CKP_INVERTED |
445 I2S_CKR_TLP_INVERTED |
446 I2S_CKR_RLP_INVERTED;
453 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
455 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
456 case SND_SOC_DAIFMT_RIGHT_J:
457 txcr_val = I2S_TXCR_IBM_RSJM;
458 rxcr_val = I2S_RXCR_IBM_RSJM;
460 case SND_SOC_DAIFMT_LEFT_J:
461 txcr_val = I2S_TXCR_IBM_LSJM;
462 rxcr_val = I2S_RXCR_IBM_LSJM;
464 case SND_SOC_DAIFMT_I2S:
465 txcr_val = I2S_TXCR_IBM_NORMAL;
466 rxcr_val = I2S_RXCR_IBM_NORMAL;
468 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
469 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
470 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
472 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
473 txcr_val = I2S_TXCR_TFS_PCM;
474 rxcr_val = I2S_RXCR_TFS_PCM;
481 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
482 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val);
484 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
485 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val);
488 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
489 case SND_SOC_DAIFMT_RIGHT_J:
490 val = I2S_TXCR_TFS_TDM_I2S;
491 tdm_val = TDM_SHIFT_CTRL(2);
493 case SND_SOC_DAIFMT_LEFT_J:
494 val = I2S_TXCR_TFS_TDM_I2S;
495 tdm_val = TDM_SHIFT_CTRL(1);
497 case SND_SOC_DAIFMT_I2S:
498 val = I2S_TXCR_TFS_TDM_I2S;
499 tdm_val = TDM_SHIFT_CTRL(0);
501 case SND_SOC_DAIFMT_DSP_A:
502 val = I2S_TXCR_TFS_TDM_PCM;
503 tdm_val = TDM_SHIFT_CTRL(0);
505 case SND_SOC_DAIFMT_DSP_B:
506 val = I2S_TXCR_TFS_TDM_PCM;
507 tdm_val = TDM_SHIFT_CTRL(2);
514 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
515 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
517 mask = I2S_TXCR_TFS_MASK;
518 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
519 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
521 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
523 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
525 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
530 pm_runtime_put(cpu_dai->dev);
535 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
536 struct rk_i2s_tdm_dev *i2s_tdm)
540 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
541 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
542 rockchip_disable_tde(i2s_tdm->regmap);
544 rockchip_disable_rde(i2s_tdm->regmap);
546 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC);
549 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
550 struct rk_i2s_tdm_dev *i2s_tdm)
554 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
555 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
556 rockchip_enable_tde(i2s_tdm->regmap);
558 rockchip_enable_rde(i2s_tdm->regmap);
560 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
567 static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
568 struct clk *clk, unsigned long rate,
571 unsigned long rate_target;
574 if (ppm == i2s_tdm->clk_ppm)
582 delta *= (int)div64_u64((u64)rate * (u64)abs(ppm) + 500000,
585 rate_target = rate + delta;
590 ret = clk_set_rate(clk, rate_target);
594 i2s_tdm->clk_ppm = ppm;
599 static int rockchip_i2s_tdm_calibrate_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
600 struct snd_pcm_substream *substream,
601 unsigned int lrck_freq)
603 struct clk *mclk_root;
604 struct clk *mclk_parent;
605 unsigned int mclk_root_freq;
606 unsigned int mclk_root_initial_freq;
607 unsigned int mclk_parent_freq;
608 unsigned int div, delta;
612 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
613 mclk_parent = i2s_tdm->mclk_tx_src;
615 mclk_parent = i2s_tdm->mclk_rx_src;
626 mclk_root = i2s_tdm->mclk_root0;
627 mclk_root_freq = i2s_tdm->mclk_root0_freq;
628 mclk_root_initial_freq = i2s_tdm->mclk_root0_initial_freq;
629 mclk_parent_freq = DEFAULT_MCLK_FS * 192000;
636 mclk_root = i2s_tdm->mclk_root1;
637 mclk_root_freq = i2s_tdm->mclk_root1_freq;
638 mclk_root_initial_freq = i2s_tdm->mclk_root1_initial_freq;
639 mclk_parent_freq = DEFAULT_MCLK_FS * 176400;
642 dev_err(i2s_tdm->dev, "Invalid LRCK frequency: %u Hz\n",
647 ret = clk_set_parent(mclk_parent, mclk_root);
651 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, mclk_root,
656 delta = abs(mclk_root_freq % mclk_parent_freq - mclk_parent_freq);
657 ppm = div64_u64((uint64_t)delta * 1000000, (uint64_t)mclk_root_freq);
660 div = DIV_ROUND_CLOSEST(mclk_root_initial_freq, mclk_parent_freq);
664 mclk_root_freq = mclk_parent_freq * round_up(div, 2);
666 ret = clk_set_rate(mclk_root, mclk_root_freq);
670 i2s_tdm->mclk_root0_freq = clk_get_rate(i2s_tdm->mclk_root0);
671 i2s_tdm->mclk_root1_freq = clk_get_rate(i2s_tdm->mclk_root1);
674 return clk_set_rate(mclk_parent, mclk_parent_freq);
677 static int rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
678 struct snd_pcm_substream *substream,
681 unsigned int mclk_freq;
684 if (i2s_tdm->clk_trcm) {
685 if (i2s_tdm->mclk_tx_freq != i2s_tdm->mclk_rx_freq) {
686 dev_err(i2s_tdm->dev,
687 "clk_trcm, tx: %d and rx: %d should be the same\n",
688 i2s_tdm->mclk_tx_freq,
689 i2s_tdm->mclk_rx_freq);
693 ret = clk_set_rate(i2s_tdm->mclk_tx, i2s_tdm->mclk_tx_freq);
697 ret = clk_set_rate(i2s_tdm->mclk_rx, i2s_tdm->mclk_rx_freq);
701 /* mclk_rx is also ok. */
702 *mclk = i2s_tdm->mclk_tx;
704 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
705 *mclk = i2s_tdm->mclk_tx;
706 mclk_freq = i2s_tdm->mclk_tx_freq;
708 *mclk = i2s_tdm->mclk_rx;
709 mclk_freq = i2s_tdm->mclk_rx_freq;
712 ret = clk_set_rate(*mclk, mclk_freq);
720 static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture)
722 if (substream_capture) {
725 return I2S_IO_6CH_OUT_4CH_IN;
727 return I2S_IO_4CH_OUT_6CH_IN;
729 return I2S_IO_2CH_OUT_8CH_IN;
731 return I2S_IO_8CH_OUT_2CH_IN;
736 return I2S_IO_4CH_OUT_6CH_IN;
738 return I2S_IO_6CH_OUT_4CH_IN;
740 return I2S_IO_8CH_OUT_2CH_IN;
742 return I2S_IO_2CH_OUT_8CH_IN;
747 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
748 struct snd_soc_dai *dai)
750 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
751 int usable_chs = MULTIPLEX_CH_MAX;
752 unsigned int val = 0;
754 if (!i2s_tdm->io_multiplex)
757 if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
758 dev_err(i2s_tdm->dev,
759 "io multiplex not supported for this device\n");
763 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
764 struct snd_pcm_str *playback_str =
765 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
767 if (playback_str->substream_opened) {
768 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
769 val &= I2S_TXCR_CSR_MASK;
770 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
773 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
774 val &= I2S_RXCR_CSR_MASK;
776 if (to_ch_num(val) > usable_chs) {
777 dev_err(i2s_tdm->dev,
778 "Capture channels (%d) > usable channels (%d)\n",
779 to_ch_num(val), usable_chs);
783 rockchip_i2s_ch_to_io(val, true);
785 struct snd_pcm_str *capture_str =
786 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
788 if (capture_str->substream_opened) {
789 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
790 val &= I2S_RXCR_CSR_MASK;
791 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
794 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
795 val &= I2S_TXCR_CSR_MASK;
797 if (to_ch_num(val) > usable_chs) {
798 dev_err(i2s_tdm->dev,
799 "Playback channels (%d) > usable channels (%d)\n",
800 to_ch_num(val), usable_chs);
805 val <<= i2s_tdm->soc_data->grf_shift;
806 val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
807 regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
812 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
813 struct snd_soc_dai *dai,
814 unsigned int div_bclk,
815 unsigned int div_lrck,
818 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
821 if (!i2s_tdm->clk_trcm)
824 spin_lock_irqsave(&i2s_tdm->lock, flags);
825 if (i2s_tdm->refcount)
826 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
828 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
829 I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
830 I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
831 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
832 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
833 I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
835 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
836 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
837 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
840 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
841 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
844 if (i2s_tdm->refcount)
845 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
846 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
851 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
852 struct snd_pcm_hw_params *params,
853 struct snd_soc_dai *dai)
855 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
858 unsigned int val = 0;
859 unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
861 if (i2s_tdm->is_master_mode) {
862 if (i2s_tdm->mclk_calibrate)
863 rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
864 params_rate(params));
866 ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
870 mclk_rate = clk_get_rate(mclk);
871 bclk_rate = i2s_tdm->frame_width * params_rate(params);
875 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
876 div_lrck = bclk_rate / params_rate(params);
879 switch (params_format(params)) {
880 case SNDRV_PCM_FORMAT_S8:
881 val |= I2S_TXCR_VDW(8);
883 case SNDRV_PCM_FORMAT_S16_LE:
884 val |= I2S_TXCR_VDW(16);
886 case SNDRV_PCM_FORMAT_S20_3LE:
887 val |= I2S_TXCR_VDW(20);
889 case SNDRV_PCM_FORMAT_S24_LE:
890 val |= I2S_TXCR_VDW(24);
892 case SNDRV_PCM_FORMAT_S32_LE:
893 val |= I2S_TXCR_VDW(32);
899 switch (params_channels(params)) {
916 if (i2s_tdm->clk_trcm) {
917 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
918 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
919 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
921 I2S_CLKDIV_TXM(div_bclk));
922 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
924 I2S_CKR_TSD(div_lrck));
925 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
926 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
929 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
931 I2S_CLKDIV_RXM(div_bclk));
932 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
934 I2S_CKR_RSD(div_lrck));
935 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
936 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
940 return rockchip_i2s_io_multiplex(substream, dai);
943 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
944 int cmd, struct snd_soc_dai *dai)
946 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
949 case SNDRV_PCM_TRIGGER_START:
950 case SNDRV_PCM_TRIGGER_RESUME:
951 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
952 if (i2s_tdm->clk_trcm)
953 rockchip_snd_txrxctrl(substream, dai, 1);
954 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
955 rockchip_snd_rxctrl(i2s_tdm, 1);
957 rockchip_snd_txctrl(i2s_tdm, 1);
959 case SNDRV_PCM_TRIGGER_SUSPEND:
960 case SNDRV_PCM_TRIGGER_STOP:
961 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
962 if (i2s_tdm->clk_trcm)
963 rockchip_snd_txrxctrl(substream, dai, 0);
964 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
965 rockchip_snd_rxctrl(i2s_tdm, 0);
967 rockchip_snd_txctrl(i2s_tdm, 0);
976 static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream,
977 unsigned int freq, int dir)
979 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
981 /* Put set mclk rate into rockchip_i2s_tdm_set_mclk() */
982 if (i2s_tdm->clk_trcm) {
983 i2s_tdm->mclk_tx_freq = freq;
984 i2s_tdm->mclk_rx_freq = freq;
986 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
987 i2s_tdm->mclk_tx_freq = freq;
989 i2s_tdm->mclk_rx_freq = freq;
992 dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n",
993 stream ? "rx" : "tx", freq);
998 static int rockchip_i2s_tdm_clk_compensation_info(struct snd_kcontrol *kcontrol,
999 struct snd_ctl_elem_info *uinfo)
1001 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1003 uinfo->value.integer.min = CLK_PPM_MIN;
1004 uinfo->value.integer.max = CLK_PPM_MAX;
1005 uinfo->value.integer.step = 1;
1010 static int rockchip_i2s_tdm_clk_compensation_get(struct snd_kcontrol *kcontrol,
1011 struct snd_ctl_elem_value *ucontrol)
1013 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1014 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1016 ucontrol->value.integer.value[0] = i2s_tdm->clk_ppm;
1021 static int rockchip_i2s_tdm_clk_compensation_put(struct snd_kcontrol *kcontrol,
1022 struct snd_ctl_elem_value *ucontrol)
1024 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1025 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1026 int ret = 0, ppm = 0;
1028 unsigned long old_rate;
1030 if (ucontrol->value.integer.value[0] < CLK_PPM_MIN ||
1031 ucontrol->value.integer.value[0] > CLK_PPM_MAX)
1034 ppm = ucontrol->value.integer.value[0];
1036 old_rate = clk_get_rate(i2s_tdm->mclk_root0);
1037 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root0,
1038 i2s_tdm->mclk_root0_freq, ppm);
1041 if (old_rate != clk_get_rate(i2s_tdm->mclk_root0))
1044 if (clk_is_match(i2s_tdm->mclk_root0, i2s_tdm->mclk_root1))
1047 old_rate = clk_get_rate(i2s_tdm->mclk_root1);
1048 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root1,
1049 i2s_tdm->mclk_root1_freq, ppm);
1052 if (old_rate != clk_get_rate(i2s_tdm->mclk_root1))
1058 static struct snd_kcontrol_new rockchip_i2s_tdm_compensation_control = {
1059 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1060 .name = "PCM Clock Compensation in PPM",
1061 .info = rockchip_i2s_tdm_clk_compensation_info,
1062 .get = rockchip_i2s_tdm_clk_compensation_get,
1063 .put = rockchip_i2s_tdm_clk_compensation_put,
1066 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
1068 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1070 if (i2s_tdm->has_capture)
1071 snd_soc_dai_dma_data_set_capture(dai, &i2s_tdm->capture_dma_data);
1072 if (i2s_tdm->has_playback)
1073 snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data);
1075 if (i2s_tdm->mclk_calibrate)
1076 snd_soc_add_dai_controls(dai, &rockchip_i2s_tdm_compensation_control, 1);
1081 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
1082 unsigned int tx_mask, unsigned int rx_mask,
1083 int slots, int slot_width)
1085 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1086 unsigned int mask, val;
1088 i2s_tdm->tdm_mode = true;
1089 i2s_tdm->frame_width = slots * slot_width;
1090 mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
1091 val = TDM_SLOT_BIT_WIDTH(slot_width) |
1092 TDM_FRAME_WIDTH(slots * slot_width);
1093 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
1095 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
1101 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai,
1104 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1106 if (ratio < 32 || ratio > 512 || ratio % 2 == 1)
1109 i2s_tdm->frame_width = ratio;
1114 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
1115 .probe = rockchip_i2s_tdm_dai_probe,
1116 .hw_params = rockchip_i2s_tdm_hw_params,
1117 .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio,
1118 .set_sysclk = rockchip_i2s_tdm_set_sysclk,
1119 .set_fmt = rockchip_i2s_tdm_set_fmt,
1120 .set_tdm_slot = rockchip_dai_tdm_slot,
1121 .trigger = rockchip_i2s_tdm_trigger,
1124 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
1126 .legacy_dai_naming = 1,
1129 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
1149 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
1173 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
1188 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
1190 if (reg == I2S_RXDR)
1195 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
1206 static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
1210 .max_register = I2S_CLKDIV,
1211 .reg_defaults = rockchip_i2s_tdm_reg_defaults,
1212 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
1213 .writeable_reg = rockchip_i2s_tdm_wr_reg,
1214 .readable_reg = rockchip_i2s_tdm_rd_reg,
1215 .volatile_reg = rockchip_i2s_tdm_volatile_reg,
1216 .precious_reg = rockchip_i2s_tdm_precious_reg,
1217 .cache_type = REGCACHE_FLAT,
1220 static int common_soc_init(struct device *dev, u32 addr)
1222 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1223 const struct txrx_config *configs = i2s_tdm->soc_data->configs;
1224 u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
1227 if (trcm == TRCM_TXRX)
1230 if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
1231 dev_err(i2s_tdm->dev,
1232 "no grf present but non-txrx TRCM specified\n");
1236 for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
1237 if (addr != configs[i].addr)
1239 reg = configs[i].reg;
1240 if (trcm == TRCM_TX)
1241 val = configs[i].txonly;
1243 val = configs[i].rxonly;
1246 regmap_write(i2s_tdm->grf, reg, val);
1252 static const struct txrx_config px30_txrx_config[] = {
1253 { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
1256 static const struct txrx_config rk1808_txrx_config[] = {
1257 { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
1260 static const struct txrx_config rk3308_txrx_config[] = {
1261 { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
1262 { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
1265 static const struct txrx_config rk3568_txrx_config[] = {
1266 { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
1267 { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
1268 { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
1269 { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
1270 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
1271 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
1274 static const struct txrx_config rv1126_txrx_config[] = {
1275 { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
1278 static const struct rk_i2s_soc_data px30_i2s_soc_data = {
1279 .softrst_offset = 0x0300,
1280 .configs = px30_txrx_config,
1281 .config_count = ARRAY_SIZE(px30_txrx_config),
1282 .init = common_soc_init,
1285 static const struct rk_i2s_soc_data rk1808_i2s_soc_data = {
1286 .softrst_offset = 0x0300,
1287 .configs = rk1808_txrx_config,
1288 .config_count = ARRAY_SIZE(rk1808_txrx_config),
1289 .init = common_soc_init,
1292 static const struct rk_i2s_soc_data rk3308_i2s_soc_data = {
1293 .softrst_offset = 0x0400,
1294 .grf_reg_offset = 0x0308,
1296 .configs = rk3308_txrx_config,
1297 .config_count = ARRAY_SIZE(rk3308_txrx_config),
1298 .init = common_soc_init,
1301 static const struct rk_i2s_soc_data rk3568_i2s_soc_data = {
1302 .softrst_offset = 0x0400,
1303 .configs = rk3568_txrx_config,
1304 .config_count = ARRAY_SIZE(rk3568_txrx_config),
1305 .init = common_soc_init,
1308 static const struct rk_i2s_soc_data rv1126_i2s_soc_data = {
1309 .softrst_offset = 0x0300,
1310 .configs = rv1126_txrx_config,
1311 .config_count = ARRAY_SIZE(rv1126_txrx_config),
1312 .init = common_soc_init,
1315 static const struct of_device_id rockchip_i2s_tdm_match[] = {
1316 { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
1317 { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
1318 { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
1319 { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1320 { .compatible = "rockchip,rk3588-i2s-tdm" },
1321 { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1325 static const struct snd_soc_dai_driver i2s_tdm_dai = {
1326 .ops = &rockchip_i2s_tdm_dai_ops,
1329 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm)
1331 struct snd_soc_dai_driver *dai;
1332 struct property *dma_names;
1333 const char *dma_name;
1334 u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
1335 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
1336 SNDRV_PCM_FMTBIT_S32_LE);
1337 struct device_node *node = i2s_tdm->dev->of_node;
1339 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1340 if (!strcmp(dma_name, "tx"))
1341 i2s_tdm->has_playback = true;
1342 if (!strcmp(dma_name, "rx"))
1343 i2s_tdm->has_capture = true;
1346 dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai,
1347 sizeof(*dai), GFP_KERNEL);
1351 if (i2s_tdm->has_playback) {
1352 dai->playback.stream_name = "Playback";
1353 dai->playback.channels_min = 2;
1354 dai->playback.channels_max = 8;
1355 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
1356 dai->playback.formats = formats;
1359 if (i2s_tdm->has_capture) {
1360 dai->capture.stream_name = "Capture";
1361 dai->capture.channels_min = 2;
1362 dai->capture.channels_max = 8;
1363 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
1364 dai->capture.formats = formats;
1367 if (i2s_tdm->clk_trcm != TRCM_TXRX)
1368 dai->symmetric_rate = 1;
1375 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
1379 unsigned int *i2s_data;
1383 i2s_data = i2s_tdm->i2s_sdis;
1385 i2s_data = i2s_tdm->i2s_sdos;
1387 for (i = 0; i < num; i++) {
1388 if (i2s_data[i] > CH_GRP_MAX - 1) {
1389 dev_err(i2s_tdm->dev,
1390 "%s path i2s_data[%d]: %d is too high, max is: %d\n",
1391 is_rx_path ? "RX" : "TX",
1392 i, i2s_data[i], CH_GRP_MAX);
1396 for (j = 0; j < num; j++) {
1400 if (i2s_data[i] == i2s_data[j]) {
1401 dev_err(i2s_tdm->dev,
1402 "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
1403 is_rx_path ? "RX" : "TX",
1414 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1419 for (idx = 0; idx < num; idx++) {
1420 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1421 I2S_TXCR_PATH_MASK(idx),
1422 I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
1426 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1431 for (idx = 0; idx < num; idx++) {
1432 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1433 I2S_RXCR_PATH_MASK(idx),
1434 I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
1438 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1439 int num, bool is_rx_path)
1442 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
1444 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
1447 static int rockchip_i2s_tdm_get_calibrate_mclks(struct rk_i2s_tdm_dev *i2s_tdm)
1451 i2s_tdm->mclk_tx_src = devm_clk_get(i2s_tdm->dev, "mclk_tx_src");
1452 if (!IS_ERR(i2s_tdm->mclk_tx_src))
1455 i2s_tdm->mclk_rx_src = devm_clk_get(i2s_tdm->dev, "mclk_rx_src");
1456 if (!IS_ERR(i2s_tdm->mclk_rx_src))
1459 i2s_tdm->mclk_root0 = devm_clk_get(i2s_tdm->dev, "mclk_root0");
1460 if (!IS_ERR(i2s_tdm->mclk_root0))
1463 i2s_tdm->mclk_root1 = devm_clk_get(i2s_tdm->dev, "mclk_root1");
1464 if (!IS_ERR(i2s_tdm->mclk_root1))
1467 if (num_mclks < 4 && num_mclks != 0)
1471 i2s_tdm->mclk_calibrate = 1;
1476 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1477 struct device_node *np,
1480 char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
1481 char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
1482 char *i2s_path_prop;
1483 unsigned int *i2s_data;
1487 i2s_path_prop = i2s_rx_path_prop;
1488 i2s_data = i2s_tdm->i2s_sdis;
1490 i2s_path_prop = i2s_tx_path_prop;
1491 i2s_data = i2s_tdm->i2s_sdos;
1494 num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
1496 if (num != -ENOENT) {
1497 dev_err(i2s_tdm->dev,
1498 "Failed to read '%s' num: %d\n",
1499 i2s_path_prop, num);
1503 } else if (num != CH_GRP_MAX) {
1504 dev_err(i2s_tdm->dev,
1505 "The num: %d should be: %d\n", num, CH_GRP_MAX);
1509 ret = of_property_read_u32_array(np, i2s_path_prop,
1512 dev_err(i2s_tdm->dev,
1513 "Failed to read '%s': %d\n",
1514 i2s_path_prop, ret);
1518 ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
1520 dev_err(i2s_tdm->dev,
1521 "Failed to check i2s data bus: %d\n", ret);
1525 rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
1530 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1531 struct device_node *np)
1533 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
1536 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1537 struct device_node *np)
1539 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1542 static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1544 struct device_node *node = pdev->dev.of_node;
1545 struct rk_i2s_tdm_dev *i2s_tdm;
1546 struct resource *res;
1550 i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
1554 i2s_tdm->dev = &pdev->dev;
1556 spin_lock_init(&i2s_tdm->lock);
1557 i2s_tdm->soc_data = device_get_match_data(&pdev->dev);
1558 i2s_tdm->frame_width = 64;
1560 i2s_tdm->clk_trcm = TRCM_TXRX;
1561 if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only"))
1562 i2s_tdm->clk_trcm = TRCM_TX;
1563 if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) {
1564 if (i2s_tdm->clk_trcm) {
1565 dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n");
1568 i2s_tdm->clk_trcm = TRCM_RX;
1571 ret = rockchip_i2s_tdm_init_dai(i2s_tdm);
1575 i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1576 i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1578 if (IS_ERR(i2s_tdm->tx_reset)) {
1579 ret = PTR_ERR(i2s_tdm->tx_reset);
1580 return dev_err_probe(i2s_tdm->dev, ret,
1581 "Error in tx-m reset control\n");
1584 i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1586 if (IS_ERR(i2s_tdm->rx_reset)) {
1587 ret = PTR_ERR(i2s_tdm->rx_reset);
1588 return dev_err_probe(i2s_tdm->dev, ret,
1589 "Error in rx-m reset control\n");
1592 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
1593 if (IS_ERR(i2s_tdm->hclk)) {
1594 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk),
1595 "Failed to get clock hclk\n");
1598 i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
1599 if (IS_ERR(i2s_tdm->mclk_tx)) {
1600 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx),
1601 "Failed to get clock mclk_tx\n");
1604 i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
1605 if (IS_ERR(i2s_tdm->mclk_rx)) {
1606 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx),
1607 "Failed to get clock mclk_rx\n");
1610 i2s_tdm->io_multiplex =
1611 of_property_read_bool(node, "rockchip,io-multiplex");
1613 ret = rockchip_i2s_tdm_get_calibrate_mclks(i2s_tdm);
1615 return dev_err_probe(i2s_tdm->dev, ret,
1616 "mclk-calibrate clocks missing");
1618 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1620 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs),
1621 "Failed to get resource IORESOURCE_MEM\n");
1624 i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1625 &rockchip_i2s_tdm_regmap_config);
1626 if (IS_ERR(i2s_tdm->regmap)) {
1627 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap),
1628 "Failed to initialise regmap\n");
1631 if (i2s_tdm->has_playback) {
1632 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1633 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1634 i2s_tdm->playback_dma_data.maxburst = 8;
1637 if (i2s_tdm->has_capture) {
1638 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1639 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1640 i2s_tdm->capture_dma_data.maxburst = 8;
1643 ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1645 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
1649 ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
1651 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
1655 dev_set_drvdata(&pdev->dev, i2s_tdm);
1657 ret = clk_prepare_enable(i2s_tdm->hclk);
1659 return dev_err_probe(i2s_tdm->dev, ret,
1660 "Failed to enable clock hclk\n");
1663 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
1665 ret = dev_err_probe(i2s_tdm->dev, ret,
1666 "Failed to enable one or more mclks\n");
1667 goto err_disable_hclk;
1670 if (i2s_tdm->mclk_calibrate) {
1671 i2s_tdm->mclk_root0_initial_freq = clk_get_rate(i2s_tdm->mclk_root0);
1672 i2s_tdm->mclk_root1_initial_freq = clk_get_rate(i2s_tdm->mclk_root1);
1673 i2s_tdm->mclk_root0_freq = i2s_tdm->mclk_root0_initial_freq;
1674 i2s_tdm->mclk_root1_freq = i2s_tdm->mclk_root1_initial_freq;
1677 pm_runtime_enable(&pdev->dev);
1679 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1681 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
1683 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK,
1684 i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT);
1686 if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
1687 i2s_tdm->soc_data->init(&pdev->dev, res->start);
1689 ret = devm_snd_soc_register_component(&pdev->dev,
1690 &rockchip_i2s_tdm_component,
1694 dev_err(&pdev->dev, "Could not register DAI\n");
1698 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1700 dev_err(&pdev->dev, "Could not register PCM\n");
1707 if (!pm_runtime_status_suspended(&pdev->dev))
1708 i2s_tdm_runtime_suspend(&pdev->dev);
1709 pm_runtime_disable(&pdev->dev);
1712 clk_disable_unprepare(i2s_tdm->hclk);
1717 static void rockchip_i2s_tdm_remove(struct platform_device *pdev)
1719 if (!pm_runtime_status_suspended(&pdev->dev))
1720 i2s_tdm_runtime_suspend(&pdev->dev);
1722 pm_runtime_disable(&pdev->dev);
1725 static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev)
1727 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1729 regcache_mark_dirty(i2s_tdm->regmap);
1734 static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev)
1736 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1739 ret = pm_runtime_resume_and_get(dev);
1742 ret = regcache_sync(i2s_tdm->regmap);
1743 pm_runtime_put(dev);
1748 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
1749 SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume,
1751 SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend,
1752 rockchip_i2s_tdm_resume)
1755 static struct platform_driver rockchip_i2s_tdm_driver = {
1756 .probe = rockchip_i2s_tdm_probe,
1757 .remove_new = rockchip_i2s_tdm_remove,
1760 .of_match_table = rockchip_i2s_tdm_match,
1761 .pm = &rockchip_i2s_tdm_pm_ops,
1764 module_platform_driver(rockchip_i2s_tdm_driver);
1766 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
1767 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1768 MODULE_LICENSE("GPL v2");
1769 MODULE_ALIAS("platform:" DRV_NAME);
1770 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);