1 // SPDX-License-Identifier: GPL-2.0-only
2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
4 // Copyright (c) 2018 Rockchip Electronics Co. Ltd.
5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
6 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_device.h>
15 #include <linux/of_gpio.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/spinlock.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm_params.h>
23 #include "rockchip_i2s_tdm.h"
25 #define DRV_NAME "rockchip-i2s-tdm"
27 #define DEFAULT_MCLK_FS 256
28 #define CH_GRP_MAX 4 /* The max channel 8 / 2 */
29 #define MULTIPLEX_CH_MAX 10
30 #define CLK_PPM_MIN -1000
31 #define CLK_PPM_MAX 1000
44 struct rk_i2s_soc_data {
49 const struct txrx_config *configs;
50 int (*init)(struct device *dev, u32 addr);
53 struct rk_i2s_tdm_dev {
58 /* The mclk_tx_src is parent of mclk_tx */
59 struct clk *mclk_tx_src;
60 /* The mclk_rx_src is parent of mclk_rx */
61 struct clk *mclk_rx_src;
63 * The mclk_root0 and mclk_root1 are root parent and supplies for
67 * mclk_root0 is VPLL0, used for FS=48000Hz
68 * mclk_root1 is VPLL1, used for FS=44100Hz
70 struct clk *mclk_root0;
71 struct clk *mclk_root1;
72 struct regmap *regmap;
74 struct snd_dmaengine_dai_dma_data capture_dma_data;
75 struct snd_dmaengine_dai_dma_data playback_dma_data;
76 struct reset_control *tx_reset;
77 struct reset_control *rx_reset;
78 struct rk_i2s_soc_data *soc_data;
83 unsigned int mclk_rx_freq;
84 unsigned int mclk_tx_freq;
85 unsigned int mclk_root0_freq;
86 unsigned int mclk_root1_freq;
87 unsigned int mclk_root0_initial_freq;
88 unsigned int mclk_root1_initial_freq;
89 unsigned int frame_width;
90 unsigned int clk_trcm;
91 unsigned int i2s_sdis[CH_GRP_MAX];
92 unsigned int i2s_sdos[CH_GRP_MAX];
95 spinlock_t lock; /* xfer lock */
98 struct snd_soc_dai_driver *dai;
101 static int to_ch_num(unsigned int val)
115 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
117 clk_disable_unprepare(i2s_tdm->mclk_tx);
118 clk_disable_unprepare(i2s_tdm->mclk_rx);
119 if (i2s_tdm->mclk_calibrate) {
120 clk_disable_unprepare(i2s_tdm->mclk_tx_src);
121 clk_disable_unprepare(i2s_tdm->mclk_rx_src);
122 clk_disable_unprepare(i2s_tdm->mclk_root0);
123 clk_disable_unprepare(i2s_tdm->mclk_root1);
128 * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
130 * @i2s_tdm: rk_i2s_tdm_dev struct
132 * This function attempts to enable all mclk clocks, but cleans up after
133 * itself on failure. Guarantees to balance its calls.
135 * Returns success (0) or negative errno.
137 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
141 ret = clk_prepare_enable(i2s_tdm->mclk_tx);
144 ret = clk_prepare_enable(i2s_tdm->mclk_rx);
147 if (i2s_tdm->mclk_calibrate) {
148 ret = clk_prepare_enable(i2s_tdm->mclk_tx_src);
151 ret = clk_prepare_enable(i2s_tdm->mclk_rx_src);
153 goto err_mclk_rx_src;
154 ret = clk_prepare_enable(i2s_tdm->mclk_root0);
157 ret = clk_prepare_enable(i2s_tdm->mclk_root1);
165 clk_disable_unprepare(i2s_tdm->mclk_root0);
167 clk_disable_unprepare(i2s_tdm->mclk_rx_src);
169 clk_disable_unprepare(i2s_tdm->mclk_tx_src);
171 clk_disable_unprepare(i2s_tdm->mclk_tx);
176 static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev)
178 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
180 regcache_cache_only(i2s_tdm->regmap, true);
181 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
183 clk_disable_unprepare(i2s_tdm->hclk);
188 static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev)
190 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
193 ret = clk_prepare_enable(i2s_tdm->hclk);
197 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
201 regcache_cache_only(i2s_tdm->regmap, false);
202 regcache_mark_dirty(i2s_tdm->regmap);
204 ret = regcache_sync(i2s_tdm->regmap);
211 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
213 clk_disable_unprepare(i2s_tdm->hclk);
218 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
220 return snd_soc_dai_get_drvdata(dai);
224 * Makes sure that both tx and rx are reset at the same time to sync lrck
227 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
229 /* This is technically race-y.
231 * In an ideal world, we could atomically assert both resets at the
232 * same time, through an atomic bulk reset API. This API however does
233 * not exist, so what the downstream vendor code used to do was
234 * implement half a reset controller here and require the CRU to be
235 * passed to the driver as a device tree node. Violating abstractions
236 * like that is bad, especially when it influences something like the
237 * bindings which are supposed to describe the hardware, not whatever
238 * workarounds the driver needs, so it was dropped.
240 * In practice, asserting the resets one by one appears to work just
241 * fine for playback. During duplex (playback + capture) operation,
242 * this might become an issue, but that should be solved by the
243 * implementation of the aforementioned API, not by shoving a reset
244 * controller into an audio driver.
247 reset_control_assert(i2s_tdm->tx_reset);
248 reset_control_assert(i2s_tdm->rx_reset);
250 reset_control_deassert(i2s_tdm->tx_reset);
251 reset_control_deassert(i2s_tdm->rx_reset);
255 static void rockchip_snd_reset(struct reset_control *rc)
257 reset_control_assert(rc);
259 reset_control_deassert(rc);
263 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm,
266 unsigned int xfer_mask = 0;
267 unsigned int xfer_val = 0;
270 bool tx = clr & I2S_CLR_TXC;
271 bool rx = clr & I2S_CLR_RXC;
277 xfer_mask = I2S_XFER_TXS_START;
278 xfer_val = I2S_XFER_TXS_STOP;
281 xfer_mask |= I2S_XFER_RXS_START;
282 xfer_val |= I2S_XFER_RXS_STOP;
285 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val);
287 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
289 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
290 /* Wait on the clear operation to finish */
293 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
296 dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n",
297 tx ? "tx" : "", rx ? "rx" : "");
299 rockchip_snd_xfer_sync_reset(i2s_tdm);
301 rockchip_snd_reset(i2s_tdm->tx_reset);
303 rockchip_snd_reset(i2s_tdm->rx_reset);
309 static inline void rockchip_enable_tde(struct regmap *regmap)
311 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
312 I2S_DMACR_TDE_ENABLE);
315 static inline void rockchip_disable_tde(struct regmap *regmap)
317 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
318 I2S_DMACR_TDE_DISABLE);
321 static inline void rockchip_enable_rde(struct regmap *regmap)
323 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
324 I2S_DMACR_RDE_ENABLE);
327 static inline void rockchip_disable_rde(struct regmap *regmap)
329 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
330 I2S_DMACR_RDE_DISABLE);
333 /* only used when clk_trcm > 0 */
334 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
335 struct snd_soc_dai *dai, int on)
337 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
340 spin_lock_irqsave(&i2s_tdm->lock, flags);
342 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
343 rockchip_enable_tde(i2s_tdm->regmap);
345 rockchip_enable_rde(i2s_tdm->regmap);
347 if (++i2s_tdm->refcount == 1) {
348 rockchip_snd_xfer_sync_reset(i2s_tdm);
349 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
356 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
357 rockchip_disable_tde(i2s_tdm->regmap);
359 rockchip_disable_rde(i2s_tdm->regmap);
361 if (--i2s_tdm->refcount == 0) {
362 rockchip_snd_xfer_clear(i2s_tdm,
363 I2S_CLR_TXC | I2S_CLR_RXC);
366 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
369 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
372 rockchip_enable_tde(i2s_tdm->regmap);
374 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
378 rockchip_disable_tde(i2s_tdm->regmap);
380 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC);
384 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
387 rockchip_enable_rde(i2s_tdm->regmap);
389 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
393 rockchip_disable_rde(i2s_tdm->regmap);
395 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC);
399 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
402 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
403 unsigned int mask, val, tdm_val, txcr_val, rxcr_val;
405 bool is_tdm = i2s_tdm->tdm_mode;
407 ret = pm_runtime_get_sync(cpu_dai->dev);
408 if (ret < 0 && ret != -EACCES) {
409 pm_runtime_put_noidle(cpu_dai->dev);
413 mask = I2S_CKR_MSS_MASK;
414 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
415 case SND_SOC_DAIFMT_CBC_CFC:
416 val = I2S_CKR_MSS_MASTER;
417 i2s_tdm->is_master_mode = true;
419 case SND_SOC_DAIFMT_CBP_CFP:
420 val = I2S_CKR_MSS_SLAVE;
421 i2s_tdm->is_master_mode = false;
428 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
430 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
431 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
432 case SND_SOC_DAIFMT_NB_NF:
433 val = I2S_CKR_CKP_NORMAL |
437 case SND_SOC_DAIFMT_NB_IF:
438 val = I2S_CKR_CKP_NORMAL |
439 I2S_CKR_TLP_INVERTED |
440 I2S_CKR_RLP_INVERTED;
442 case SND_SOC_DAIFMT_IB_NF:
443 val = I2S_CKR_CKP_INVERTED |
447 case SND_SOC_DAIFMT_IB_IF:
448 val = I2S_CKR_CKP_INVERTED |
449 I2S_CKR_TLP_INVERTED |
450 I2S_CKR_RLP_INVERTED;
457 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
459 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
460 case SND_SOC_DAIFMT_RIGHT_J:
461 txcr_val = I2S_TXCR_IBM_RSJM;
462 rxcr_val = I2S_RXCR_IBM_RSJM;
464 case SND_SOC_DAIFMT_LEFT_J:
465 txcr_val = I2S_TXCR_IBM_LSJM;
466 rxcr_val = I2S_RXCR_IBM_LSJM;
468 case SND_SOC_DAIFMT_I2S:
469 txcr_val = I2S_TXCR_IBM_NORMAL;
470 rxcr_val = I2S_RXCR_IBM_NORMAL;
472 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
473 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
474 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
476 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
477 txcr_val = I2S_TXCR_TFS_PCM;
478 rxcr_val = I2S_RXCR_TFS_PCM;
485 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
486 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val);
488 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
489 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val);
492 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
493 case SND_SOC_DAIFMT_RIGHT_J:
494 val = I2S_TXCR_TFS_TDM_I2S;
495 tdm_val = TDM_SHIFT_CTRL(2);
497 case SND_SOC_DAIFMT_LEFT_J:
498 val = I2S_TXCR_TFS_TDM_I2S;
499 tdm_val = TDM_SHIFT_CTRL(1);
501 case SND_SOC_DAIFMT_I2S:
502 val = I2S_TXCR_TFS_TDM_I2S;
503 tdm_val = TDM_SHIFT_CTRL(0);
505 case SND_SOC_DAIFMT_DSP_A:
506 val = I2S_TXCR_TFS_TDM_PCM;
507 tdm_val = TDM_SHIFT_CTRL(0);
509 case SND_SOC_DAIFMT_DSP_B:
510 val = I2S_TXCR_TFS_TDM_PCM;
511 tdm_val = TDM_SHIFT_CTRL(2);
518 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
519 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
521 mask = I2S_TXCR_TFS_MASK;
522 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
523 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
525 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
527 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
529 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
534 pm_runtime_put(cpu_dai->dev);
539 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
540 struct rk_i2s_tdm_dev *i2s_tdm)
544 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
545 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
546 rockchip_disable_tde(i2s_tdm->regmap);
548 rockchip_disable_rde(i2s_tdm->regmap);
550 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC);
553 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
554 struct rk_i2s_tdm_dev *i2s_tdm)
558 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
559 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
560 rockchip_enable_tde(i2s_tdm->regmap);
562 rockchip_enable_rde(i2s_tdm->regmap);
564 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
571 static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
572 struct clk *clk, unsigned long rate,
575 unsigned long rate_target;
578 if (ppm == i2s_tdm->clk_ppm)
586 delta *= (int)div64_u64((u64)rate * (u64)abs(ppm) + 500000,
589 rate_target = rate + delta;
594 ret = clk_set_rate(clk, rate_target);
598 i2s_tdm->clk_ppm = ppm;
603 static int rockchip_i2s_tdm_calibrate_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
604 struct snd_pcm_substream *substream,
605 unsigned int lrck_freq)
607 struct clk *mclk_root;
608 struct clk *mclk_parent;
609 unsigned int mclk_root_freq;
610 unsigned int mclk_root_initial_freq;
611 unsigned int mclk_parent_freq;
612 unsigned int div, delta;
616 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
617 mclk_parent = i2s_tdm->mclk_tx_src;
619 mclk_parent = i2s_tdm->mclk_rx_src;
630 mclk_root = i2s_tdm->mclk_root0;
631 mclk_root_freq = i2s_tdm->mclk_root0_freq;
632 mclk_root_initial_freq = i2s_tdm->mclk_root0_initial_freq;
633 mclk_parent_freq = DEFAULT_MCLK_FS * 192000;
640 mclk_root = i2s_tdm->mclk_root1;
641 mclk_root_freq = i2s_tdm->mclk_root1_freq;
642 mclk_root_initial_freq = i2s_tdm->mclk_root1_initial_freq;
643 mclk_parent_freq = DEFAULT_MCLK_FS * 176400;
646 dev_err(i2s_tdm->dev, "Invalid LRCK frequency: %u Hz\n",
651 ret = clk_set_parent(mclk_parent, mclk_root);
655 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, mclk_root,
660 delta = abs(mclk_root_freq % mclk_parent_freq - mclk_parent_freq);
661 ppm = div64_u64((uint64_t)delta * 1000000, (uint64_t)mclk_root_freq);
664 div = DIV_ROUND_CLOSEST(mclk_root_initial_freq, mclk_parent_freq);
668 mclk_root_freq = mclk_parent_freq * round_up(div, 2);
670 ret = clk_set_rate(mclk_root, mclk_root_freq);
674 i2s_tdm->mclk_root0_freq = clk_get_rate(i2s_tdm->mclk_root0);
675 i2s_tdm->mclk_root1_freq = clk_get_rate(i2s_tdm->mclk_root1);
678 return clk_set_rate(mclk_parent, mclk_parent_freq);
681 static int rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
682 struct snd_pcm_substream *substream,
685 unsigned int mclk_freq;
688 if (i2s_tdm->clk_trcm) {
689 if (i2s_tdm->mclk_tx_freq != i2s_tdm->mclk_rx_freq) {
690 dev_err(i2s_tdm->dev,
691 "clk_trcm, tx: %d and rx: %d should be the same\n",
692 i2s_tdm->mclk_tx_freq,
693 i2s_tdm->mclk_rx_freq);
697 ret = clk_set_rate(i2s_tdm->mclk_tx, i2s_tdm->mclk_tx_freq);
701 ret = clk_set_rate(i2s_tdm->mclk_rx, i2s_tdm->mclk_rx_freq);
705 /* mclk_rx is also ok. */
706 *mclk = i2s_tdm->mclk_tx;
708 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
709 *mclk = i2s_tdm->mclk_tx;
710 mclk_freq = i2s_tdm->mclk_tx_freq;
712 *mclk = i2s_tdm->mclk_rx;
713 mclk_freq = i2s_tdm->mclk_rx_freq;
716 ret = clk_set_rate(*mclk, mclk_freq);
724 static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture)
726 if (substream_capture) {
729 return I2S_IO_6CH_OUT_4CH_IN;
731 return I2S_IO_4CH_OUT_6CH_IN;
733 return I2S_IO_2CH_OUT_8CH_IN;
735 return I2S_IO_8CH_OUT_2CH_IN;
740 return I2S_IO_4CH_OUT_6CH_IN;
742 return I2S_IO_6CH_OUT_4CH_IN;
744 return I2S_IO_8CH_OUT_2CH_IN;
746 return I2S_IO_2CH_OUT_8CH_IN;
751 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
752 struct snd_soc_dai *dai)
754 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
755 int usable_chs = MULTIPLEX_CH_MAX;
756 unsigned int val = 0;
758 if (!i2s_tdm->io_multiplex)
761 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
762 struct snd_pcm_str *playback_str =
763 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
765 if (playback_str->substream_opened) {
766 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
767 val &= I2S_TXCR_CSR_MASK;
768 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
771 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
772 val &= I2S_RXCR_CSR_MASK;
774 if (to_ch_num(val) > usable_chs) {
775 dev_err(i2s_tdm->dev,
776 "Capture channels (%d) > usable channels (%d)\n",
777 to_ch_num(val), usable_chs);
781 rockchip_i2s_ch_to_io(val, true);
783 struct snd_pcm_str *capture_str =
784 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
786 if (capture_str->substream_opened) {
787 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
788 val &= I2S_RXCR_CSR_MASK;
789 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
792 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
793 val &= I2S_TXCR_CSR_MASK;
795 if (to_ch_num(val) > usable_chs) {
796 dev_err(i2s_tdm->dev,
797 "Playback channels (%d) > usable channels (%d)\n",
798 to_ch_num(val), usable_chs);
803 val <<= i2s_tdm->soc_data->grf_shift;
804 val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
805 regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
810 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
811 struct snd_soc_dai *dai,
812 unsigned int div_bclk,
813 unsigned int div_lrck,
816 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
819 if (!i2s_tdm->clk_trcm)
822 spin_lock_irqsave(&i2s_tdm->lock, flags);
823 if (i2s_tdm->refcount)
824 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
826 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
827 I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
828 I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
829 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
830 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
831 I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
833 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
834 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
835 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
838 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
839 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
842 if (i2s_tdm->refcount)
843 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
844 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
849 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
850 struct snd_pcm_hw_params *params,
851 struct snd_soc_dai *dai)
853 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
856 unsigned int val = 0;
857 unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
859 if (i2s_tdm->is_master_mode) {
860 if (i2s_tdm->mclk_calibrate)
861 rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
862 params_rate(params));
864 ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
868 mclk_rate = clk_get_rate(mclk);
869 bclk_rate = i2s_tdm->frame_width * params_rate(params);
873 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
874 div_lrck = bclk_rate / params_rate(params);
877 switch (params_format(params)) {
878 case SNDRV_PCM_FORMAT_S8:
879 val |= I2S_TXCR_VDW(8);
881 case SNDRV_PCM_FORMAT_S16_LE:
882 val |= I2S_TXCR_VDW(16);
884 case SNDRV_PCM_FORMAT_S20_3LE:
885 val |= I2S_TXCR_VDW(20);
887 case SNDRV_PCM_FORMAT_S24_LE:
888 val |= I2S_TXCR_VDW(24);
890 case SNDRV_PCM_FORMAT_S32_LE:
891 val |= I2S_TXCR_VDW(32);
897 switch (params_channels(params)) {
914 if (i2s_tdm->clk_trcm) {
915 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
916 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
917 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
919 I2S_CLKDIV_TXM(div_bclk));
920 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
922 I2S_CKR_TSD(div_lrck));
923 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
924 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
927 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
929 I2S_CLKDIV_RXM(div_bclk));
930 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
932 I2S_CKR_RSD(div_lrck));
933 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
934 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
938 return rockchip_i2s_io_multiplex(substream, dai);
941 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
942 int cmd, struct snd_soc_dai *dai)
944 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
947 case SNDRV_PCM_TRIGGER_START:
948 case SNDRV_PCM_TRIGGER_RESUME:
949 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
950 if (i2s_tdm->clk_trcm)
951 rockchip_snd_txrxctrl(substream, dai, 1);
952 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
953 rockchip_snd_rxctrl(i2s_tdm, 1);
955 rockchip_snd_txctrl(i2s_tdm, 1);
957 case SNDRV_PCM_TRIGGER_SUSPEND:
958 case SNDRV_PCM_TRIGGER_STOP:
959 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
960 if (i2s_tdm->clk_trcm)
961 rockchip_snd_txrxctrl(substream, dai, 0);
962 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
963 rockchip_snd_rxctrl(i2s_tdm, 0);
965 rockchip_snd_txctrl(i2s_tdm, 0);
974 static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream,
975 unsigned int freq, int dir)
977 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
979 /* Put set mclk rate into rockchip_i2s_tdm_set_mclk() */
980 if (i2s_tdm->clk_trcm) {
981 i2s_tdm->mclk_tx_freq = freq;
982 i2s_tdm->mclk_rx_freq = freq;
984 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
985 i2s_tdm->mclk_tx_freq = freq;
987 i2s_tdm->mclk_rx_freq = freq;
990 dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n",
991 stream ? "rx" : "tx", freq);
996 static int rockchip_i2s_tdm_clk_compensation_info(struct snd_kcontrol *kcontrol,
997 struct snd_ctl_elem_info *uinfo)
999 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1001 uinfo->value.integer.min = CLK_PPM_MIN;
1002 uinfo->value.integer.max = CLK_PPM_MAX;
1003 uinfo->value.integer.step = 1;
1008 static int rockchip_i2s_tdm_clk_compensation_get(struct snd_kcontrol *kcontrol,
1009 struct snd_ctl_elem_value *ucontrol)
1011 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1012 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1014 ucontrol->value.integer.value[0] = i2s_tdm->clk_ppm;
1019 static int rockchip_i2s_tdm_clk_compensation_put(struct snd_kcontrol *kcontrol,
1020 struct snd_ctl_elem_value *ucontrol)
1022 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1023 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1024 int ret = 0, ppm = 0;
1026 unsigned long old_rate;
1028 if (ucontrol->value.integer.value[0] < CLK_PPM_MIN ||
1029 ucontrol->value.integer.value[0] > CLK_PPM_MAX)
1032 ppm = ucontrol->value.integer.value[0];
1034 old_rate = clk_get_rate(i2s_tdm->mclk_root0);
1035 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root0,
1036 i2s_tdm->mclk_root0_freq, ppm);
1039 if (old_rate != clk_get_rate(i2s_tdm->mclk_root0))
1042 if (clk_is_match(i2s_tdm->mclk_root0, i2s_tdm->mclk_root1))
1045 old_rate = clk_get_rate(i2s_tdm->mclk_root1);
1046 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root1,
1047 i2s_tdm->mclk_root1_freq, ppm);
1050 if (old_rate != clk_get_rate(i2s_tdm->mclk_root1))
1056 static struct snd_kcontrol_new rockchip_i2s_tdm_compensation_control = {
1057 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1058 .name = "PCM Clock Compensation in PPM",
1059 .info = rockchip_i2s_tdm_clk_compensation_info,
1060 .get = rockchip_i2s_tdm_clk_compensation_get,
1061 .put = rockchip_i2s_tdm_clk_compensation_put,
1064 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
1066 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1068 if (i2s_tdm->has_capture)
1069 dai->capture_dma_data = &i2s_tdm->capture_dma_data;
1070 if (i2s_tdm->has_playback)
1071 dai->playback_dma_data = &i2s_tdm->playback_dma_data;
1073 if (i2s_tdm->mclk_calibrate)
1074 snd_soc_add_dai_controls(dai, &rockchip_i2s_tdm_compensation_control, 1);
1079 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
1080 unsigned int tx_mask, unsigned int rx_mask,
1081 int slots, int slot_width)
1083 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1084 unsigned int mask, val;
1086 i2s_tdm->tdm_mode = true;
1087 i2s_tdm->frame_width = slots * slot_width;
1088 mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
1089 val = TDM_SLOT_BIT_WIDTH(slot_width) |
1090 TDM_FRAME_WIDTH(slots * slot_width);
1091 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
1093 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
1099 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai,
1102 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1104 if (ratio < 32 || ratio > 512 || ratio % 2 == 1)
1107 i2s_tdm->frame_width = ratio;
1112 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
1113 .hw_params = rockchip_i2s_tdm_hw_params,
1114 .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio,
1115 .set_sysclk = rockchip_i2s_tdm_set_sysclk,
1116 .set_fmt = rockchip_i2s_tdm_set_fmt,
1117 .set_tdm_slot = rockchip_dai_tdm_slot,
1118 .trigger = rockchip_i2s_tdm_trigger,
1121 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
1125 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
1145 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
1169 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
1184 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
1186 if (reg == I2S_RXDR)
1191 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
1202 static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
1206 .max_register = I2S_CLKDIV,
1207 .reg_defaults = rockchip_i2s_tdm_reg_defaults,
1208 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
1209 .writeable_reg = rockchip_i2s_tdm_wr_reg,
1210 .readable_reg = rockchip_i2s_tdm_rd_reg,
1211 .volatile_reg = rockchip_i2s_tdm_volatile_reg,
1212 .precious_reg = rockchip_i2s_tdm_precious_reg,
1213 .cache_type = REGCACHE_FLAT,
1216 static int common_soc_init(struct device *dev, u32 addr)
1218 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1219 const struct txrx_config *configs = i2s_tdm->soc_data->configs;
1220 u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
1223 if (trcm == TRCM_TXRX)
1226 for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
1227 if (addr != configs[i].addr)
1229 reg = configs[i].reg;
1230 if (trcm == TRCM_TX)
1231 val = configs[i].txonly;
1233 val = configs[i].rxonly;
1236 regmap_write(i2s_tdm->grf, reg, val);
1242 static const struct txrx_config px30_txrx_config[] = {
1243 { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
1246 static const struct txrx_config rk1808_txrx_config[] = {
1247 { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
1250 static const struct txrx_config rk3308_txrx_config[] = {
1251 { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
1252 { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
1255 static const struct txrx_config rk3568_txrx_config[] = {
1256 { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
1257 { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
1258 { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
1259 { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
1260 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
1261 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
1264 static const struct txrx_config rv1126_txrx_config[] = {
1265 { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
1268 static struct rk_i2s_soc_data px30_i2s_soc_data = {
1269 .softrst_offset = 0x0300,
1270 .configs = px30_txrx_config,
1271 .config_count = ARRAY_SIZE(px30_txrx_config),
1272 .init = common_soc_init,
1275 static struct rk_i2s_soc_data rk1808_i2s_soc_data = {
1276 .softrst_offset = 0x0300,
1277 .configs = rk1808_txrx_config,
1278 .config_count = ARRAY_SIZE(rk1808_txrx_config),
1279 .init = common_soc_init,
1282 static struct rk_i2s_soc_data rk3308_i2s_soc_data = {
1283 .softrst_offset = 0x0400,
1284 .grf_reg_offset = 0x0308,
1286 .configs = rk3308_txrx_config,
1287 .config_count = ARRAY_SIZE(rk3308_txrx_config),
1288 .init = common_soc_init,
1291 static struct rk_i2s_soc_data rk3568_i2s_soc_data = {
1292 .softrst_offset = 0x0400,
1293 .configs = rk3568_txrx_config,
1294 .config_count = ARRAY_SIZE(rk3568_txrx_config),
1295 .init = common_soc_init,
1298 static struct rk_i2s_soc_data rv1126_i2s_soc_data = {
1299 .softrst_offset = 0x0300,
1300 .configs = rv1126_txrx_config,
1301 .config_count = ARRAY_SIZE(rv1126_txrx_config),
1302 .init = common_soc_init,
1305 static const struct of_device_id rockchip_i2s_tdm_match[] = {
1306 { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
1307 { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
1308 { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
1309 { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1310 { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1314 static const struct snd_soc_dai_driver i2s_tdm_dai = {
1315 .probe = rockchip_i2s_tdm_dai_probe,
1316 .ops = &rockchip_i2s_tdm_dai_ops,
1319 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm)
1321 struct snd_soc_dai_driver *dai;
1322 struct property *dma_names;
1323 const char *dma_name;
1324 u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
1325 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
1326 SNDRV_PCM_FMTBIT_S32_LE);
1327 struct device_node *node = i2s_tdm->dev->of_node;
1329 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1330 if (!strcmp(dma_name, "tx"))
1331 i2s_tdm->has_playback = true;
1332 if (!strcmp(dma_name, "rx"))
1333 i2s_tdm->has_capture = true;
1336 dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai,
1337 sizeof(*dai), GFP_KERNEL);
1341 if (i2s_tdm->has_playback) {
1342 dai->playback.stream_name = "Playback";
1343 dai->playback.channels_min = 2;
1344 dai->playback.channels_max = 8;
1345 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
1346 dai->playback.formats = formats;
1349 if (i2s_tdm->has_capture) {
1350 dai->capture.stream_name = "Capture";
1351 dai->capture.channels_min = 2;
1352 dai->capture.channels_max = 8;
1353 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
1354 dai->capture.formats = formats;
1357 if (i2s_tdm->clk_trcm != TRCM_TXRX)
1358 dai->symmetric_rate = 1;
1365 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
1369 unsigned int *i2s_data;
1373 i2s_data = i2s_tdm->i2s_sdis;
1375 i2s_data = i2s_tdm->i2s_sdos;
1377 for (i = 0; i < num; i++) {
1378 if (i2s_data[i] > CH_GRP_MAX - 1) {
1379 dev_err(i2s_tdm->dev,
1380 "%s path i2s_data[%d]: %d is too high, max is: %d\n",
1381 is_rx_path ? "RX" : "TX",
1382 i, i2s_data[i], CH_GRP_MAX);
1386 for (j = 0; j < num; j++) {
1390 if (i2s_data[i] == i2s_data[j]) {
1391 dev_err(i2s_tdm->dev,
1392 "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
1393 is_rx_path ? "RX" : "TX",
1404 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1409 for (idx = 0; idx < num; idx++) {
1410 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1411 I2S_TXCR_PATH_MASK(idx),
1412 I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
1416 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1421 for (idx = 0; idx < num; idx++) {
1422 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1423 I2S_RXCR_PATH_MASK(idx),
1424 I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
1428 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1429 int num, bool is_rx_path)
1432 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
1434 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
1437 static int rockchip_i2s_tdm_get_calibrate_mclks(struct rk_i2s_tdm_dev *i2s_tdm)
1441 i2s_tdm->mclk_tx_src = devm_clk_get(i2s_tdm->dev, "mclk_tx_src");
1442 if (!IS_ERR(i2s_tdm->mclk_tx_src))
1445 i2s_tdm->mclk_rx_src = devm_clk_get(i2s_tdm->dev, "mclk_rx_src");
1446 if (!IS_ERR(i2s_tdm->mclk_rx_src))
1449 i2s_tdm->mclk_root0 = devm_clk_get(i2s_tdm->dev, "mclk_root0");
1450 if (!IS_ERR(i2s_tdm->mclk_root0))
1453 i2s_tdm->mclk_root1 = devm_clk_get(i2s_tdm->dev, "mclk_root1");
1454 if (!IS_ERR(i2s_tdm->mclk_root1))
1457 if (num_mclks < 4 && num_mclks != 0)
1461 i2s_tdm->mclk_calibrate = 1;
1466 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1467 struct device_node *np,
1470 char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
1471 char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
1472 char *i2s_path_prop;
1473 unsigned int *i2s_data;
1477 i2s_path_prop = i2s_rx_path_prop;
1478 i2s_data = i2s_tdm->i2s_sdis;
1480 i2s_path_prop = i2s_tx_path_prop;
1481 i2s_data = i2s_tdm->i2s_sdos;
1484 num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
1486 if (num != -ENOENT) {
1487 dev_err(i2s_tdm->dev,
1488 "Failed to read '%s' num: %d\n",
1489 i2s_path_prop, num);
1493 } else if (num != CH_GRP_MAX) {
1494 dev_err(i2s_tdm->dev,
1495 "The num: %d should be: %d\n", num, CH_GRP_MAX);
1499 ret = of_property_read_u32_array(np, i2s_path_prop,
1502 dev_err(i2s_tdm->dev,
1503 "Failed to read '%s': %d\n",
1504 i2s_path_prop, ret);
1508 ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
1510 dev_err(i2s_tdm->dev,
1511 "Failed to check i2s data bus: %d\n", ret);
1515 rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
1520 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1521 struct device_node *np)
1523 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
1526 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1527 struct device_node *np)
1529 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1532 static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1534 struct device_node *node = pdev->dev.of_node;
1535 const struct of_device_id *of_id;
1536 struct rk_i2s_tdm_dev *i2s_tdm;
1537 struct resource *res;
1541 i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
1545 i2s_tdm->dev = &pdev->dev;
1547 of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
1548 if (!of_id || !of_id->data)
1551 spin_lock_init(&i2s_tdm->lock);
1552 i2s_tdm->soc_data = (struct rk_i2s_soc_data *)of_id->data;
1554 i2s_tdm->frame_width = 64;
1556 i2s_tdm->clk_trcm = TRCM_TXRX;
1557 if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only"))
1558 i2s_tdm->clk_trcm = TRCM_TX;
1559 if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) {
1560 if (i2s_tdm->clk_trcm) {
1561 dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n");
1564 i2s_tdm->clk_trcm = TRCM_RX;
1567 ret = rockchip_i2s_tdm_init_dai(i2s_tdm);
1571 i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1572 if (IS_ERR(i2s_tdm->grf))
1573 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->grf),
1574 "Error in rockchip,grf\n");
1576 i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1578 if (IS_ERR(i2s_tdm->tx_reset)) {
1579 ret = PTR_ERR(i2s_tdm->tx_reset);
1580 return dev_err_probe(i2s_tdm->dev, ret,
1581 "Error in tx-m reset control\n");
1584 i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1586 if (IS_ERR(i2s_tdm->rx_reset)) {
1587 ret = PTR_ERR(i2s_tdm->rx_reset);
1588 return dev_err_probe(i2s_tdm->dev, ret,
1589 "Error in rx-m reset control\n");
1592 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
1593 if (IS_ERR(i2s_tdm->hclk)) {
1594 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk),
1595 "Failed to get clock hclk\n");
1598 i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
1599 if (IS_ERR(i2s_tdm->mclk_tx)) {
1600 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx),
1601 "Failed to get clock mclk_tx\n");
1604 i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
1605 if (IS_ERR(i2s_tdm->mclk_rx)) {
1606 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx),
1607 "Failed to get clock mclk_rx\n");
1610 i2s_tdm->io_multiplex =
1611 of_property_read_bool(node, "rockchip,io-multiplex");
1613 ret = rockchip_i2s_tdm_get_calibrate_mclks(i2s_tdm);
1615 return dev_err_probe(i2s_tdm->dev, ret,
1616 "mclk-calibrate clocks missing");
1618 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1620 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs),
1621 "Failed to get resource IORESOURCE_MEM\n");
1624 i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1625 &rockchip_i2s_tdm_regmap_config);
1626 if (IS_ERR(i2s_tdm->regmap)) {
1627 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap),
1628 "Failed to initialise regmap\n");
1631 if (i2s_tdm->has_playback) {
1632 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1633 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1634 i2s_tdm->playback_dma_data.maxburst = 8;
1637 if (i2s_tdm->has_capture) {
1638 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1639 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1640 i2s_tdm->capture_dma_data.maxburst = 8;
1643 ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1645 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
1649 ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
1651 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
1655 dev_set_drvdata(&pdev->dev, i2s_tdm);
1657 ret = clk_prepare_enable(i2s_tdm->hclk);
1659 return dev_err_probe(i2s_tdm->dev, ret,
1660 "Failed to enable clock hclk\n");
1663 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
1665 ret = dev_err_probe(i2s_tdm->dev, ret,
1666 "Failed to enable one or more mclks\n");
1667 goto err_disable_hclk;
1670 if (i2s_tdm->mclk_calibrate) {
1671 i2s_tdm->mclk_root0_initial_freq = clk_get_rate(i2s_tdm->mclk_root0);
1672 i2s_tdm->mclk_root1_initial_freq = clk_get_rate(i2s_tdm->mclk_root1);
1673 i2s_tdm->mclk_root0_freq = i2s_tdm->mclk_root0_initial_freq;
1674 i2s_tdm->mclk_root1_freq = i2s_tdm->mclk_root1_initial_freq;
1677 pm_runtime_enable(&pdev->dev);
1679 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1681 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
1683 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK,
1684 i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT);
1686 if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
1687 i2s_tdm->soc_data->init(&pdev->dev, res->start);
1689 ret = devm_snd_soc_register_component(&pdev->dev,
1690 &rockchip_i2s_tdm_component,
1694 dev_err(&pdev->dev, "Could not register DAI\n");
1698 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1700 dev_err(&pdev->dev, "Could not register PCM\n");
1707 if (!pm_runtime_status_suspended(&pdev->dev))
1708 i2s_tdm_runtime_suspend(&pdev->dev);
1709 pm_runtime_disable(&pdev->dev);
1712 clk_disable_unprepare(i2s_tdm->hclk);
1717 static int rockchip_i2s_tdm_remove(struct platform_device *pdev)
1719 if (!pm_runtime_status_suspended(&pdev->dev))
1720 i2s_tdm_runtime_suspend(&pdev->dev);
1722 pm_runtime_disable(&pdev->dev);
1727 static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev)
1729 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1731 regcache_mark_dirty(i2s_tdm->regmap);
1736 static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev)
1738 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1741 ret = pm_runtime_resume_and_get(dev);
1744 ret = regcache_sync(i2s_tdm->regmap);
1745 pm_runtime_put(dev);
1750 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
1751 SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume,
1753 SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend,
1754 rockchip_i2s_tdm_resume)
1757 static struct platform_driver rockchip_i2s_tdm_driver = {
1758 .probe = rockchip_i2s_tdm_probe,
1759 .remove = rockchip_i2s_tdm_remove,
1762 .of_match_table = of_match_ptr(rockchip_i2s_tdm_match),
1763 .pm = &rockchip_i2s_tdm_pm_ops,
1766 module_platform_driver(rockchip_i2s_tdm_driver);
1768 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
1769 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1770 MODULE_LICENSE("GPL v2");
1771 MODULE_ALIAS("platform:" DRV_NAME);
1772 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);