sound/soc/rockchip/rockchip_i2s_tdm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
   3
   4 // Copyright (c) 2018 Rockchip Electronics Co. Ltd.
   5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
   6 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
   7
   8 #include <linux/clk.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/delay.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_gpio.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19 #include <linux/spinlock.h>
  20 #include <sound/dmaengine_pcm.h>
  21 #include <sound/pcm_params.h>
  22
  23 #include "rockchip_i2s_tdm.h"
  24
  25 #define DRV_NAME "rockchip-i2s-tdm"
  26
  27 #define DEFAULT_MCLK_FS                         256
  28 #define CH_GRP_MAX                              4  /* The max channel 8 / 2 */
  29 #define MULTIPLEX_CH_MAX                        10
  30
  31 #define TRCM_TXRX 0
  32 #define TRCM_TX 1
  33 #define TRCM_RX 2
  34
  35 struct txrx_config {
  36         u32 addr;
  37         u32 reg;
  38         u32 txonly;
  39         u32 rxonly;
  40 };
  41
  42 struct rk_i2s_soc_data {
  43         u32 softrst_offset;
  44         u32 grf_reg_offset;
  45         u32 grf_shift;
  46         int config_count;
  47         const struct txrx_config *configs;
  48         int (*init)(struct device *dev, u32 addr);
  49 };
  50
  51 struct rk_i2s_tdm_dev {
  52         struct device *dev;
  53         struct clk *hclk;
  54         struct clk *mclk_tx;
  55         struct clk *mclk_rx;
  56         struct regmap *regmap;
  57         struct regmap *grf;
  58         struct snd_dmaengine_dai_dma_data capture_dma_data;
  59         struct snd_dmaengine_dai_dma_data playback_dma_data;
  60         struct reset_control *tx_reset;
  61         struct reset_control *rx_reset;
  62         struct rk_i2s_soc_data *soc_data;
  63         bool is_master_mode;
  64         bool io_multiplex;
  65         bool tdm_mode;
  66         unsigned int frame_width;
  67         unsigned int clk_trcm;
  68         unsigned int i2s_sdis[CH_GRP_MAX];
  69         unsigned int i2s_sdos[CH_GRP_MAX];
  70         int refcount;
  71         spinlock_t lock; /* xfer lock */
  72         bool has_playback;
  73         bool has_capture;
  74         struct snd_soc_dai_driver *dai;
  75 };
  76
  77 static int to_ch_num(unsigned int val)
  78 {
  79         switch (val) {
  80         case I2S_CHN_4:
  81                 return 4;
  82         case I2S_CHN_6:
  83                 return 6;
  84         case I2S_CHN_8:
  85                 return 8;
  86         default:
  87                 return 2;
  88         }
  89 }
  90
  91 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
  92 {
  93         clk_disable_unprepare(i2s_tdm->mclk_tx);
  94         clk_disable_unprepare(i2s_tdm->mclk_rx);
  95 }
  96
  97 /**
  98  * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
  99  *                               failure.
 100  * @i2s_tdm: rk_i2s_tdm_dev struct
 101  *
 102  * This function attempts to enable all mclk clocks, but cleans up after
 103  * itself on failure. Guarantees to balance its calls.
 104  *
 105  * Returns success (0) or negative errno.
 106  */
 107 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
 108 {
 109         int ret = 0;
 110
 111         ret = clk_prepare_enable(i2s_tdm->mclk_tx);
 112         if (ret)
 113                 goto err_mclk_tx;
 114         ret = clk_prepare_enable(i2s_tdm->mclk_rx);
 115         if (ret)
 116                 goto err_mclk_rx;
 117
 118         return 0;
 119
 120 err_mclk_rx:
 121         clk_disable_unprepare(i2s_tdm->mclk_tx);
 122 err_mclk_tx:
 123         return ret;
 124 }
 125
 126 static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev)
 127 {
 128         struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
 129
 130         regcache_cache_only(i2s_tdm->regmap, true);
 131         i2s_tdm_disable_unprepare_mclk(i2s_tdm);
 132
 133         clk_disable_unprepare(i2s_tdm->hclk);
 134
 135         return 0;
 136 }
 137
 138 static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev)
 139 {
 140         struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
 141         int ret;
 142
 143         ret = clk_prepare_enable(i2s_tdm->hclk);
 144         if (ret)
 145                 goto err_hclk;
 146
 147         ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
 148         if (ret)
 149                 goto err_mclk;
 150
 151         regcache_cache_only(i2s_tdm->regmap, false);
 152         regcache_mark_dirty(i2s_tdm->regmap);
 153
 154         ret = regcache_sync(i2s_tdm->regmap);
 155         if (ret)
 156                 goto err_regcache;
 157
 158         return 0;
 159
 160 err_regcache:
 161         i2s_tdm_disable_unprepare_mclk(i2s_tdm);
 162 err_mclk:
 163         clk_disable_unprepare(i2s_tdm->hclk);
 164 err_hclk:
 165         return ret;
 166 }
 167
 168 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
 169 {
 170         return snd_soc_dai_get_drvdata(dai);
 171 }
 172
 173 /*
 174  * Makes sure that both tx and rx are reset at the same time to sync lrck
 175  * when clk_trcm > 0.
 176  */
 177 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
 178 {
 179         /* This is technically race-y.
 180          *
 181          * In an ideal world, we could atomically assert both resets at the
 182          * same time, through an atomic bulk reset API. This API however does
 183          * not exist, so what the downstream vendor code used to do was
 184          * implement half a reset controller here and require the CRU to be
 185          * passed to the driver as a device tree node. Violating abstractions
 186          * like that is bad, especially when it influences something like the
 187          * bindings which are supposed to describe the hardware, not whatever
 188          * workarounds the driver needs, so it was dropped.
 189          *
 190          * In practice, asserting the resets one by one appears to work just
 191          * fine for playback. During duplex (playback + capture) operation,
 192          * this might become an issue, but that should be solved by the
 193          * implementation of the aforementioned API, not by shoving a reset
 194          * controller into an audio driver.
 195          */
 196
 197         reset_control_assert(i2s_tdm->tx_reset);
 198         reset_control_assert(i2s_tdm->rx_reset);
 199         udelay(10);
 200         reset_control_deassert(i2s_tdm->tx_reset);
 201         reset_control_deassert(i2s_tdm->rx_reset);
 202         udelay(10);
 203 }
 204
 205 static void rockchip_snd_reset(struct reset_control *rc)
 206 {
 207         reset_control_assert(rc);
 208         udelay(10);
 209         reset_control_deassert(rc);
 210         udelay(10);
 211 }
 212
 213 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm,
 214                                     unsigned int clr)
 215 {
 216         unsigned int xfer_mask = 0;
 217         unsigned int xfer_val = 0;
 218         unsigned int val;
 219         int retry = 10;
 220         bool tx = clr & I2S_CLR_TXC;
 221         bool rx = clr & I2S_CLR_RXC;
 222
 223         if (!(rx || tx))
 224                 return;
 225
 226         if (tx) {
 227                 xfer_mask = I2S_XFER_TXS_START;
 228                 xfer_val = I2S_XFER_TXS_STOP;
 229         }
 230         if (rx) {
 231                 xfer_mask |= I2S_XFER_RXS_START;
 232                 xfer_val |= I2S_XFER_RXS_STOP;
 233         }
 234
 235         regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val);
 236         udelay(150);
 237         regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
 238
 239         regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
 240         /* Wait on the clear operation to finish */
 241         while (val) {
 242                 udelay(15);
 243                 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
 244                 retry--;
 245                 if (!retry) {
 246                         dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n",
 247                                  tx ? "tx" : "", rx ? "rx" : "");
 248                         if (rx && tx)
 249                                 rockchip_snd_xfer_sync_reset(i2s_tdm);
 250                         else if (tx)
 251                                 rockchip_snd_reset(i2s_tdm->tx_reset);
 252                         else if (rx)
 253                                 rockchip_snd_reset(i2s_tdm->rx_reset);
 254                         break;
 255                 }
 256         }
 257 }
 258
 259 static inline void rockchip_enable_tde(struct regmap *regmap)
 260 {
 261         regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
 262                            I2S_DMACR_TDE_ENABLE);
 263 }
 264
 265 static inline void rockchip_disable_tde(struct regmap *regmap)
 266 {
 267         regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
 268                            I2S_DMACR_TDE_DISABLE);
 269 }
 270
 271 static inline void rockchip_enable_rde(struct regmap *regmap)
 272 {
 273         regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
 274                            I2S_DMACR_RDE_ENABLE);
 275 }
 276
 277 static inline void rockchip_disable_rde(struct regmap *regmap)
 278 {
 279         regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
 280                            I2S_DMACR_RDE_DISABLE);
 281 }
 282
 283 /* only used when clk_trcm > 0 */
 284 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
 285                                   struct snd_soc_dai *dai, int on)
 286 {
 287         struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
 288         unsigned long flags;
 289
 290         spin_lock_irqsave(&i2s_tdm->lock, flags);
 291         if (on) {
 292                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 293                         rockchip_enable_tde(i2s_tdm->regmap);
 294                 else
 295                         rockchip_enable_rde(i2s_tdm->regmap);
 296
 297                 if (++i2s_tdm->refcount == 1) {
 298                         rockchip_snd_xfer_sync_reset(i2s_tdm);
 299                         regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
 300                                            I2S_XFER_TXS_START |
 301                                            I2S_XFER_RXS_START,
 302                                            I2S_XFER_TXS_START |
 303                                            I2S_XFER_RXS_START);
 304                 }
 305         } else {
 306                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 307                         rockchip_disable_tde(i2s_tdm->regmap);
 308                 else
 309                         rockchip_disable_rde(i2s_tdm->regmap);
 310
 311                 if (--i2s_tdm->refcount == 0) {
 312                         rockchip_snd_xfer_clear(i2s_tdm,
 313                                                 I2S_CLR_TXC | I2S_CLR_RXC);
 314                 }
 315         }
 316         spin_unlock_irqrestore(&i2s_tdm->lock, flags);
 317 }
 318
 319 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
 320 {
 321         if (on) {
 322                 rockchip_enable_tde(i2s_tdm->regmap);
 323
 324                 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
 325                                    I2S_XFER_TXS_START,
 326                                    I2S_XFER_TXS_START);
 327         } else {
 328                 rockchip_disable_tde(i2s_tdm->regmap);
 329
 330                 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC);
 331         }
 332 }
 333
 334 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
 335 {
 336         if (on) {
 337                 rockchip_enable_rde(i2s_tdm->regmap);
 338
 339                 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
 340                                    I2S_XFER_RXS_START,
 341                                    I2S_XFER_RXS_START);
 342         } else {
 343                 rockchip_disable_rde(i2s_tdm->regmap);
 344
 345                 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC);
 346         }
 347 }
 348
 349 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
 350                                     unsigned int fmt)
 351 {
 352         struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
 353         unsigned int mask, val, tdm_val, txcr_val, rxcr_val;
 354         int ret;
 355         bool is_tdm = i2s_tdm->tdm_mode;
 356
 357         ret = pm_runtime_resume_and_get(cpu_dai->dev);
 358         if (ret < 0 && ret != -EACCES)
 359                 return ret;
 360
 361         mask = I2S_CKR_MSS_MASK;
 362         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 363         case SND_SOC_DAIFMT_BP_FP:
 364                 val = I2S_CKR_MSS_MASTER;
 365                 i2s_tdm->is_master_mode = true;
 366                 break;
 367         case SND_SOC_DAIFMT_BC_FC:
 368                 val = I2S_CKR_MSS_SLAVE;
 369                 i2s_tdm->is_master_mode = false;
 370                 break;
 371         default:
 372                 ret = -EINVAL;
 373                 goto err_pm_put;
 374         }
 375
 376         regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
 377
 378         mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
 379         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 380         case SND_SOC_DAIFMT_NB_NF:
 381                 val = I2S_CKR_CKP_NORMAL |
 382                       I2S_CKR_TLP_NORMAL |
 383                       I2S_CKR_RLP_NORMAL;
 384                 break;
 385         case SND_SOC_DAIFMT_NB_IF:
 386                 val = I2S_CKR_CKP_NORMAL |
 387                       I2S_CKR_TLP_INVERTED |
 388                       I2S_CKR_RLP_INVERTED;
 389                 break;
 390         case SND_SOC_DAIFMT_IB_NF:
 391                 val = I2S_CKR_CKP_INVERTED |
 392                       I2S_CKR_TLP_NORMAL |
 393                       I2S_CKR_RLP_NORMAL;
 394                 break;
 395         case SND_SOC_DAIFMT_IB_IF:
 396                 val = I2S_CKR_CKP_INVERTED |
 397                       I2S_CKR_TLP_INVERTED |
 398                       I2S_CKR_RLP_INVERTED;
 399                 break;
 400         default:
 401                 ret = -EINVAL;
 402                 goto err_pm_put;
 403         }
 404
 405         regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
 406
 407         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 408         case SND_SOC_DAIFMT_RIGHT_J:
 409                 txcr_val = I2S_TXCR_IBM_RSJM;
 410                 rxcr_val = I2S_RXCR_IBM_RSJM;
 411                 break;
 412         case SND_SOC_DAIFMT_LEFT_J:
 413                 txcr_val = I2S_TXCR_IBM_LSJM;
 414                 rxcr_val = I2S_RXCR_IBM_LSJM;
 415                 break;
 416         case SND_SOC_DAIFMT_I2S:
 417                 txcr_val = I2S_TXCR_IBM_NORMAL;
 418                 rxcr_val = I2S_RXCR_IBM_NORMAL;
 419                 break;
 420         case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
 421                 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
 422                 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
 423                 break;
 424         case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
 425                 txcr_val = I2S_TXCR_TFS_PCM;
 426                 rxcr_val = I2S_RXCR_TFS_PCM;
 427                 break;
 428         default:
 429                 ret = -EINVAL;
 430                 goto err_pm_put;
 431         }
 432
 433         mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
 434         regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val);
 435
 436         mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
 437         regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val);
 438
 439         if (is_tdm) {
 440                 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 441                 case SND_SOC_DAIFMT_RIGHT_J:
 442                         val = I2S_TXCR_TFS_TDM_I2S;
 443                         tdm_val = TDM_SHIFT_CTRL(2);
 444                         break;
 445                 case SND_SOC_DAIFMT_LEFT_J:
 446                         val = I2S_TXCR_TFS_TDM_I2S;
 447                         tdm_val = TDM_SHIFT_CTRL(1);
 448                         break;
 449                 case SND_SOC_DAIFMT_I2S:
 450                         val = I2S_TXCR_TFS_TDM_I2S;
 451                         tdm_val = TDM_SHIFT_CTRL(0);
 452                         break;
 453                 case SND_SOC_DAIFMT_DSP_A:
 454                         val = I2S_TXCR_TFS_TDM_PCM;
 455                         tdm_val = TDM_SHIFT_CTRL(0);
 456                         break;
 457                 case SND_SOC_DAIFMT_DSP_B:
 458                         val = I2S_TXCR_TFS_TDM_PCM;
 459                         tdm_val = TDM_SHIFT_CTRL(2);
 460                         break;
 461                 default:
 462                         ret = -EINVAL;
 463                         goto err_pm_put;
 464                 }
 465
 466                 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
 467                 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
 468
 469                 mask = I2S_TXCR_TFS_MASK;
 470                 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
 471                 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
 472
 473                 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
 474                        TDM_SHIFT_CTRL_MSK;
 475                 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
 476                                    mask, tdm_val);
 477                 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
 478                                    mask, tdm_val);
 479         }
 480
 481 err_pm_put:
 482         pm_runtime_put(cpu_dai->dev);
 483
 484         return ret;
 485 }
 486
 487 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
 488                                         struct rk_i2s_tdm_dev *i2s_tdm)
 489 {
 490         int stream;
 491
 492         stream = SNDRV_PCM_STREAM_LAST - substream->stream;
 493         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 494                 rockchip_disable_tde(i2s_tdm->regmap);
 495         else
 496                 rockchip_disable_rde(i2s_tdm->regmap);
 497
 498         rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC);
 499 }
 500
 501 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
 502                                          struct rk_i2s_tdm_dev *i2s_tdm)
 503 {
 504         int stream;
 505
 506         stream = SNDRV_PCM_STREAM_LAST - substream->stream;
 507         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 508                 rockchip_enable_tde(i2s_tdm->regmap);
 509         else
 510                 rockchip_enable_rde(i2s_tdm->regmap);
 511
 512         regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
 513                            I2S_XFER_TXS_START |
 514                            I2S_XFER_RXS_START,
 515                            I2S_XFER_TXS_START |
 516                            I2S_XFER_RXS_START);
 517 }
 518
 519 static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture)
 520 {
 521         if (substream_capture) {
 522                 switch (ch) {
 523                 case I2S_CHN_4:
 524                         return I2S_IO_6CH_OUT_4CH_IN;
 525                 case I2S_CHN_6:
 526                         return I2S_IO_4CH_OUT_6CH_IN;
 527                 case I2S_CHN_8:
 528                         return I2S_IO_2CH_OUT_8CH_IN;
 529                 default:
 530                         return I2S_IO_8CH_OUT_2CH_IN;
 531                 }
 532         } else {
 533                 switch (ch) {
 534                 case I2S_CHN_4:
 535                         return I2S_IO_4CH_OUT_6CH_IN;
 536                 case I2S_CHN_6:
 537                         return I2S_IO_6CH_OUT_4CH_IN;
 538                 case I2S_CHN_8:
 539                         return I2S_IO_8CH_OUT_2CH_IN;
 540                 default:
 541                         return I2S_IO_2CH_OUT_8CH_IN;
 542                 }
 543         }
 544 }
 545
 546 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
 547                                      struct snd_soc_dai *dai)
 548 {
 549         struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
 550         int usable_chs = MULTIPLEX_CH_MAX;
 551         unsigned int val = 0;
 552
 553         if (!i2s_tdm->io_multiplex)
 554                 return 0;
 555
 556         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 557                 struct snd_pcm_str *playback_str =
 558                         &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
 559
 560                 if (playback_str->substream_opened) {
 561                         regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
 562                         val &= I2S_TXCR_CSR_MASK;
 563                         usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
 564                 }
 565
 566                 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
 567                 val &= I2S_RXCR_CSR_MASK;
 568
 569                 if (to_ch_num(val) > usable_chs) {
 570                         dev_err(i2s_tdm->dev,
 571                                 "Capture channels (%d) > usable channels (%d)\n",
 572                                 to_ch_num(val), usable_chs);
 573                         return -EINVAL;
 574                 }
 575
 576                 rockchip_i2s_ch_to_io(val, true);
 577         } else {
 578                 struct snd_pcm_str *capture_str =
 579                         &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
 580
 581                 if (capture_str->substream_opened) {
 582                         regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
 583                         val &= I2S_RXCR_CSR_MASK;
 584                         usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
 585                 }
 586
 587                 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
 588                 val &= I2S_TXCR_CSR_MASK;
 589
 590                 if (to_ch_num(val) > usable_chs) {
 591                         dev_err(i2s_tdm->dev,
 592                                 "Playback channels (%d) > usable channels (%d)\n",
 593                                 to_ch_num(val), usable_chs);
 594                         return -EINVAL;
 595                 }
 596         }
 597
 598         val <<= i2s_tdm->soc_data->grf_shift;
 599         val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
 600         regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
 601
 602         return 0;
 603 }
 604
 605 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
 606                                   struct snd_soc_dai *dai,
 607                                   unsigned int div_bclk,
 608                                   unsigned int div_lrck,
 609                                   unsigned int fmt)
 610 {
 611         struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
 612         unsigned long flags;
 613
 614         if (!i2s_tdm->clk_trcm)
 615                 return 0;
 616
 617         spin_lock_irqsave(&i2s_tdm->lock, flags);
 618         if (i2s_tdm->refcount)
 619                 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
 620
 621         regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
 622                            I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
 623                            I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
 624         regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
 625                            I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
 626                            I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
 627
 628         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 629                 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
 630                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 631                                    fmt);
 632         else
 633                 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
 634                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 635                                    fmt);
 636
 637         if (i2s_tdm->refcount)
 638                 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
 639         spin_unlock_irqrestore(&i2s_tdm->lock, flags);
 640
 641         return 0;
 642 }
 643
 644 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
 645                                       struct snd_pcm_hw_params *params,
 646                                       struct snd_soc_dai *dai)
 647 {
 648         struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
 649         unsigned int val = 0;
 650         unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
 651         int err;
 652
 653         if (i2s_tdm->is_master_mode) {
 654                 struct clk *mclk = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
 655                         i2s_tdm->mclk_tx : i2s_tdm->mclk_rx;
 656
 657                 err = clk_set_rate(mclk, DEFAULT_MCLK_FS * params_rate(params));
 658                 if (err)
 659                         return err;
 660
 661                 mclk_rate = clk_get_rate(mclk);
 662                 bclk_rate = i2s_tdm->frame_width * params_rate(params);
 663                 if (!bclk_rate)
 664                         return -EINVAL;
 665
 666                 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
 667                 div_lrck = bclk_rate / params_rate(params);
 668         }
 669
 670         switch (params_format(params)) {
 671         case SNDRV_PCM_FORMAT_S8:
 672                 val |= I2S_TXCR_VDW(8);
 673                 break;
 674         case SNDRV_PCM_FORMAT_S16_LE:
 675                 val |= I2S_TXCR_VDW(16);
 676                 break;
 677         case SNDRV_PCM_FORMAT_S20_3LE:
 678                 val |= I2S_TXCR_VDW(20);
 679                 break;
 680         case SNDRV_PCM_FORMAT_S24_LE:
 681                 val |= I2S_TXCR_VDW(24);
 682                 break;
 683         case SNDRV_PCM_FORMAT_S32_LE:
 684                 val |= I2S_TXCR_VDW(32);
 685                 break;
 686         default:
 687                 return -EINVAL;
 688         }
 689
 690         switch (params_channels(params)) {
 691         case 8:
 692                 val |= I2S_CHN_8;
 693                 break;
 694         case 6:
 695                 val |= I2S_CHN_6;
 696                 break;
 697         case 4:
 698                 val |= I2S_CHN_4;
 699                 break;
 700         case 2:
 701                 val |= I2S_CHN_2;
 702                 break;
 703         default:
 704                 return -EINVAL;
 705         }
 706
 707         if (i2s_tdm->clk_trcm) {
 708                 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
 709         } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 710                 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
 711                                    I2S_CLKDIV_TXM_MASK,
 712                                    I2S_CLKDIV_TXM(div_bclk));
 713                 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
 714                                    I2S_CKR_TSD_MASK,
 715                                    I2S_CKR_TSD(div_lrck));
 716                 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
 717                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 718                                    val);
 719         } else {
 720                 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
 721                                    I2S_CLKDIV_RXM_MASK,
 722                                    I2S_CLKDIV_RXM(div_bclk));
 723                 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
 724                                    I2S_CKR_RSD_MASK,
 725                                    I2S_CKR_RSD(div_lrck));
 726                 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
 727                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 728                                    val);
 729         }
 730
 731         return rockchip_i2s_io_multiplex(substream, dai);
 732 }
 733
 734 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
 735                                     int cmd, struct snd_soc_dai *dai)
 736 {
 737         struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
 738
 739         switch (cmd) {
 740         case SNDRV_PCM_TRIGGER_START:
 741         case SNDRV_PCM_TRIGGER_RESUME:
 742         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 743                 if (i2s_tdm->clk_trcm)
 744                         rockchip_snd_txrxctrl(substream, dai, 1);
 745                 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 746                         rockchip_snd_rxctrl(i2s_tdm, 1);
 747                 else
 748                         rockchip_snd_txctrl(i2s_tdm, 1);
 749                 break;
 750         case SNDRV_PCM_TRIGGER_SUSPEND:
 751         case SNDRV_PCM_TRIGGER_STOP:
 752         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 753                 if (i2s_tdm->clk_trcm)
 754                         rockchip_snd_txrxctrl(substream, dai, 0);
 755                 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 756                         rockchip_snd_rxctrl(i2s_tdm, 0);
 757                 else
 758                         rockchip_snd_txctrl(i2s_tdm, 0);
 759                 break;
 760         default:
 761                 return -EINVAL;
 762         }
 763
 764         return 0;
 765 }
 766
 767 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
 768 {
 769         struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
 770
 771         if (i2s_tdm->has_capture)
 772                 dai->capture_dma_data = &i2s_tdm->capture_dma_data;
 773         if (i2s_tdm->has_playback)
 774                 dai->playback_dma_data = &i2s_tdm->playback_dma_data;
 775
 776         return 0;
 777 }
 778
 779 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
 780                                  unsigned int tx_mask, unsigned int rx_mask,
 781                                  int slots, int slot_width)
 782 {
 783         struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
 784         unsigned int mask, val;
 785
 786         i2s_tdm->tdm_mode = true;
 787         i2s_tdm->frame_width = slots * slot_width;
 788         mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
 789         val = TDM_SLOT_BIT_WIDTH(slot_width) |
 790               TDM_FRAME_WIDTH(slots * slot_width);
 791         regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
 792                            mask, val);
 793         regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
 794                            mask, val);
 795
 796         return 0;
 797 }
 798
 799 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai,
 800                                            unsigned int ratio)
 801 {
 802         struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
 803
 804         if (ratio < 32 || ratio > 512 || ratio % 2 == 1)
 805                 return -EINVAL;
 806
 807         i2s_tdm->frame_width = ratio;
 808
 809         return 0;
 810 }
 811
 812 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
 813         .hw_params = rockchip_i2s_tdm_hw_params,
 814         .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio,
 815         .set_fmt = rockchip_i2s_tdm_set_fmt,
 816         .set_tdm_slot = rockchip_dai_tdm_slot,
 817         .trigger = rockchip_i2s_tdm_trigger,
 818 };
 819
 820 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
 821         .name = DRV_NAME,
 822         .legacy_dai_naming = 1,
 823 };
 824
 825 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
 826 {
 827         switch (reg) {
 828         case I2S_TXCR:
 829         case I2S_RXCR:
 830         case I2S_CKR:
 831         case I2S_DMACR:
 832         case I2S_INTCR:
 833         case I2S_XFER:
 834         case I2S_CLR:
 835         case I2S_TXDR:
 836         case I2S_TDM_TXCR:
 837         case I2S_TDM_RXCR:
 838         case I2S_CLKDIV:
 839                 return true;
 840         default:
 841                 return false;
 842         }
 843 }
 844
 845 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
 846 {
 847         switch (reg) {
 848         case I2S_TXCR:
 849         case I2S_RXCR:
 850         case I2S_CKR:
 851         case I2S_DMACR:
 852         case I2S_INTCR:
 853         case I2S_XFER:
 854         case I2S_CLR:
 855         case I2S_TXDR:
 856         case I2S_RXDR:
 857         case I2S_TXFIFOLR:
 858         case I2S_INTSR:
 859         case I2S_RXFIFOLR:
 860         case I2S_TDM_TXCR:
 861         case I2S_TDM_RXCR:
 862         case I2S_CLKDIV:
 863                 return true;
 864         default:
 865                 return false;
 866         }
 867 }
 868
 869 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
 870 {
 871         switch (reg) {
 872         case I2S_TXFIFOLR:
 873         case I2S_INTSR:
 874         case I2S_CLR:
 875         case I2S_TXDR:
 876         case I2S_RXDR:
 877         case I2S_RXFIFOLR:
 878                 return true;
 879         default:
 880                 return false;
 881         }
 882 }
 883
 884 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
 885 {
 886         if (reg == I2S_RXDR)
 887                 return true;
 888         return false;
 889 }
 890
 891 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
 892         {0x00, 0x7200000f},
 893         {0x04, 0x01c8000f},
 894         {0x08, 0x00001f1f},
 895         {0x10, 0x001f0000},
 896         {0x14, 0x01f00000},
 897         {0x30, 0x00003eff},
 898         {0x34, 0x00003eff},
 899         {0x38, 0x00000707},
 900 };
 901
 902 static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
 903         .reg_bits = 32,
 904         .reg_stride = 4,
 905         .val_bits = 32,
 906         .max_register = I2S_CLKDIV,
 907         .reg_defaults = rockchip_i2s_tdm_reg_defaults,
 908         .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
 909         .writeable_reg = rockchip_i2s_tdm_wr_reg,
 910         .readable_reg = rockchip_i2s_tdm_rd_reg,
 911         .volatile_reg = rockchip_i2s_tdm_volatile_reg,
 912         .precious_reg = rockchip_i2s_tdm_precious_reg,
 913         .cache_type = REGCACHE_FLAT,
 914 };
 915
 916 static int common_soc_init(struct device *dev, u32 addr)
 917 {
 918         struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
 919         const struct txrx_config *configs = i2s_tdm->soc_data->configs;
 920         u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
 921         int i;
 922
 923         if (trcm == TRCM_TXRX)
 924                 return 0;
 925
 926         for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
 927                 if (addr != configs[i].addr)
 928                         continue;
 929                 reg = configs[i].reg;
 930                 if (trcm == TRCM_TX)
 931                         val = configs[i].txonly;
 932                 else
 933                         val = configs[i].rxonly;
 934
 935                 if (reg)
 936                         regmap_write(i2s_tdm->grf, reg, val);
 937         }
 938
 939         return 0;
 940 }
 941
 942 static const struct txrx_config px30_txrx_config[] = {
 943         { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
 944 };
 945
 946 static const struct txrx_config rk1808_txrx_config[] = {
 947         { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
 948 };
 949
 950 static const struct txrx_config rk3308_txrx_config[] = {
 951         { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
 952         { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
 953 };
 954
 955 static const struct txrx_config rk3568_txrx_config[] = {
 956         { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
 957         { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
 958         { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
 959         { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
 960         { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
 961         { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
 962 };
 963
 964 static const struct txrx_config rv1126_txrx_config[] = {
 965         { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
 966 };
 967
 968 static struct rk_i2s_soc_data px30_i2s_soc_data = {
 969         .softrst_offset = 0x0300,
 970         .configs = px30_txrx_config,
 971         .config_count = ARRAY_SIZE(px30_txrx_config),
 972         .init = common_soc_init,
 973 };
 974
 975 static struct rk_i2s_soc_data rk1808_i2s_soc_data = {
 976         .softrst_offset = 0x0300,
 977         .configs = rk1808_txrx_config,
 978         .config_count = ARRAY_SIZE(rk1808_txrx_config),
 979         .init = common_soc_init,
 980 };
 981
 982 static struct rk_i2s_soc_data rk3308_i2s_soc_data = {
 983         .softrst_offset = 0x0400,
 984         .grf_reg_offset = 0x0308,
 985         .grf_shift = 5,
 986         .configs = rk3308_txrx_config,
 987         .config_count = ARRAY_SIZE(rk3308_txrx_config),
 988         .init = common_soc_init,
 989 };
 990
 991 static struct rk_i2s_soc_data rk3568_i2s_soc_data = {
 992         .softrst_offset = 0x0400,
 993         .configs = rk3568_txrx_config,
 994         .config_count = ARRAY_SIZE(rk3568_txrx_config),
 995         .init = common_soc_init,
 996 };
 997
 998 static struct rk_i2s_soc_data rv1126_i2s_soc_data = {
 999         .softrst_offset = 0x0300,
1000         .configs = rv1126_txrx_config,
1001         .config_count = ARRAY_SIZE(rv1126_txrx_config),
1002         .init = common_soc_init,
1003 };
1004
1005 static const struct of_device_id rockchip_i2s_tdm_match[] = {
1006         { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
1007         { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
1008         { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
1009         { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1010         { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1011         {},
1012 };
1013
1014 static const struct snd_soc_dai_driver i2s_tdm_dai = {
1015         .probe = rockchip_i2s_tdm_dai_probe,
1016         .ops = &rockchip_i2s_tdm_dai_ops,
1017 };
1018
1019 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm)
1020 {
1021         struct snd_soc_dai_driver *dai;
1022         struct property *dma_names;
1023         const char *dma_name;
1024         u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
1025                        SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
1026                        SNDRV_PCM_FMTBIT_S32_LE);
1027         struct device_node *node = i2s_tdm->dev->of_node;
1028
1029         of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1030                 if (!strcmp(dma_name, "tx"))
1031                         i2s_tdm->has_playback = true;
1032                 if (!strcmp(dma_name, "rx"))
1033                         i2s_tdm->has_capture = true;
1034         }
1035
1036         dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai,
1037                            sizeof(*dai), GFP_KERNEL);
1038         if (!dai)
1039                 return -ENOMEM;
1040
1041         if (i2s_tdm->has_playback) {
1042                 dai->playback.stream_name  = "Playback";
1043                 dai->playback.channels_min = 2;
1044                 dai->playback.channels_max = 8;
1045                 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
1046                 dai->playback.formats = formats;
1047         }
1048
1049         if (i2s_tdm->has_capture) {
1050                 dai->capture.stream_name  = "Capture";
1051                 dai->capture.channels_min = 2;
1052                 dai->capture.channels_max = 8;
1053                 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
1054                 dai->capture.formats = formats;
1055         }
1056
1057         if (i2s_tdm->clk_trcm != TRCM_TXRX)
1058                 dai->symmetric_rate = 1;
1059
1060         i2s_tdm->dai = dai;
1061
1062         return 0;
1063 }
1064
1065 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
1066                                        int num,
1067                                        bool is_rx_path)
1068 {
1069         unsigned int *i2s_data;
1070         int i, j;
1071
1072         if (is_rx_path)
1073                 i2s_data = i2s_tdm->i2s_sdis;
1074         else
1075                 i2s_data = i2s_tdm->i2s_sdos;
1076
1077         for (i = 0; i < num; i++) {
1078                 if (i2s_data[i] > CH_GRP_MAX - 1) {
1079                         dev_err(i2s_tdm->dev,
1080                                 "%s path i2s_data[%d]: %d is too high, max is: %d\n",
1081                                 is_rx_path ? "RX" : "TX",
1082                                 i, i2s_data[i], CH_GRP_MAX);
1083                         return -EINVAL;
1084                 }
1085
1086                 for (j = 0; j < num; j++) {
1087                         if (i == j)
1088                                 continue;
1089
1090                         if (i2s_data[i] == i2s_data[j]) {
1091                                 dev_err(i2s_tdm->dev,
1092                                         "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
1093                                         is_rx_path ? "RX" : "TX",
1094                                         i, i2s_data[i],
1095                                         j, i2s_data[j]);
1096                                 return -EINVAL;
1097                         }
1098                 }
1099         }
1100
1101         return 0;
1102 }
1103
1104 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1105                                             int num)
1106 {
1107         int idx;
1108
1109         for (idx = 0; idx < num; idx++) {
1110                 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1111                                    I2S_TXCR_PATH_MASK(idx),
1112                                    I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
1113         }
1114 }
1115
1116 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1117                                             int num)
1118 {
1119         int idx;
1120
1121         for (idx = 0; idx < num; idx++) {
1122                 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1123                                    I2S_RXCR_PATH_MASK(idx),
1124                                    I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
1125         }
1126 }
1127
1128 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1129                                          int num, bool is_rx_path)
1130 {
1131         if (is_rx_path)
1132                 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
1133         else
1134                 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
1135 }
1136
1137 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1138                                          struct device_node *np,
1139                                          bool is_rx_path)
1140 {
1141         char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
1142         char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
1143         char *i2s_path_prop;
1144         unsigned int *i2s_data;
1145         int num, ret = 0;
1146
1147         if (is_rx_path) {
1148                 i2s_path_prop = i2s_rx_path_prop;
1149                 i2s_data = i2s_tdm->i2s_sdis;
1150         } else {
1151                 i2s_path_prop = i2s_tx_path_prop;
1152                 i2s_data = i2s_tdm->i2s_sdos;
1153         }
1154
1155         num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
1156         if (num < 0) {
1157                 if (num != -ENOENT) {
1158                         dev_err(i2s_tdm->dev,
1159                                 "Failed to read '%s' num: %d\n",
1160                                 i2s_path_prop, num);
1161                         ret = num;
1162                 }
1163                 return ret;
1164         } else if (num != CH_GRP_MAX) {
1165                 dev_err(i2s_tdm->dev,
1166                         "The num: %d should be: %d\n", num, CH_GRP_MAX);
1167                 return -EINVAL;
1168         }
1169
1170         ret = of_property_read_u32_array(np, i2s_path_prop,
1171                                          i2s_data, num);
1172         if (ret < 0) {
1173                 dev_err(i2s_tdm->dev,
1174                         "Failed to read '%s': %d\n",
1175                         i2s_path_prop, ret);
1176                 return ret;
1177         }
1178
1179         ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
1180         if (ret < 0) {
1181                 dev_err(i2s_tdm->dev,
1182                         "Failed to check i2s data bus: %d\n", ret);
1183                 return ret;
1184         }
1185
1186         rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
1187
1188         return 0;
1189 }
1190
1191 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1192                                             struct device_node *np)
1193 {
1194         return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
1195 }
1196
1197 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1198                                             struct device_node *np)
1199 {
1200         return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1201 }
1202
1203 static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1204 {
1205         struct device_node *node = pdev->dev.of_node;
1206         const struct of_device_id *of_id;
1207         struct rk_i2s_tdm_dev *i2s_tdm;
1208         struct resource *res;
1209         void __iomem *regs;
1210         int ret;
1211
1212         i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
1213         if (!i2s_tdm)
1214                 return -ENOMEM;
1215
1216         i2s_tdm->dev = &pdev->dev;
1217
1218         of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
1219         if (!of_id || !of_id->data)
1220                 return -EINVAL;
1221
1222         spin_lock_init(&i2s_tdm->lock);
1223         i2s_tdm->soc_data = (struct rk_i2s_soc_data *)of_id->data;
1224
1225         i2s_tdm->frame_width = 64;
1226
1227         i2s_tdm->clk_trcm = TRCM_TXRX;
1228         if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only"))
1229                 i2s_tdm->clk_trcm = TRCM_TX;
1230         if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) {
1231                 if (i2s_tdm->clk_trcm) {
1232                         dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n");
1233                         return -EINVAL;
1234                 }
1235                 i2s_tdm->clk_trcm = TRCM_RX;
1236         }
1237
1238         ret = rockchip_i2s_tdm_init_dai(i2s_tdm);
1239         if (ret)
1240                 return ret;
1241
1242         i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1243         if (IS_ERR(i2s_tdm->grf))
1244                 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->grf),
1245                                      "Error in rockchip,grf\n");
1246
1247         i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1248                                                                       "tx-m");
1249         if (IS_ERR(i2s_tdm->tx_reset)) {
1250                 ret = PTR_ERR(i2s_tdm->tx_reset);
1251                 return dev_err_probe(i2s_tdm->dev, ret,
1252                                      "Error in tx-m reset control\n");
1253         }
1254
1255         i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1256                                                                       "rx-m");
1257         if (IS_ERR(i2s_tdm->rx_reset)) {
1258                 ret = PTR_ERR(i2s_tdm->rx_reset);
1259                 return dev_err_probe(i2s_tdm->dev, ret,
1260                                      "Error in rx-m reset control\n");
1261         }
1262
1263         i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
1264         if (IS_ERR(i2s_tdm->hclk)) {
1265                 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk),
1266                                      "Failed to get clock hclk\n");
1267         }
1268
1269         i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
1270         if (IS_ERR(i2s_tdm->mclk_tx)) {
1271                 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx),
1272                                      "Failed to get clock mclk_tx\n");
1273         }
1274
1275         i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
1276         if (IS_ERR(i2s_tdm->mclk_rx)) {
1277                 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx),
1278                                      "Failed to get clock mclk_rx\n");
1279         }
1280
1281         i2s_tdm->io_multiplex =
1282                 of_property_read_bool(node, "rockchip,io-multiplex");
1283
1284         regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1285         if (IS_ERR(regs)) {
1286                 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs),
1287                                      "Failed to get resource IORESOURCE_MEM\n");
1288         }
1289
1290         i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1291                                                 &rockchip_i2s_tdm_regmap_config);
1292         if (IS_ERR(i2s_tdm->regmap)) {
1293                 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap),
1294                                      "Failed to initialise regmap\n");
1295         }
1296
1297         if (i2s_tdm->has_playback) {
1298                 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1299                 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1300                 i2s_tdm->playback_dma_data.maxburst = 8;
1301         }
1302
1303         if (i2s_tdm->has_capture) {
1304                 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1305                 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1306                 i2s_tdm->capture_dma_data.maxburst = 8;
1307         }
1308
1309         ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1310         if (ret < 0) {
1311                 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
1312                 return ret;
1313         }
1314
1315         ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
1316         if (ret < 0) {
1317                 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
1318                 return ret;
1319         }
1320
1321         dev_set_drvdata(&pdev->dev, i2s_tdm);
1322
1323         ret = clk_prepare_enable(i2s_tdm->hclk);
1324         if (ret) {
1325                 return dev_err_probe(i2s_tdm->dev, ret,
1326                                      "Failed to enable clock hclk\n");
1327         }
1328
1329         ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
1330         if (ret) {
1331                 ret = dev_err_probe(i2s_tdm->dev, ret,
1332                                     "Failed to enable one or more mclks\n");
1333                 goto err_disable_hclk;
1334         }
1335
1336         pm_runtime_enable(&pdev->dev);
1337
1338         regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1339                            I2S_DMACR_TDL(16));
1340         regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
1341                            I2S_DMACR_RDL(16));
1342         regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK,
1343                            i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT);
1344
1345         if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
1346                 i2s_tdm->soc_data->init(&pdev->dev, res->start);
1347
1348         ret = devm_snd_soc_register_component(&pdev->dev,
1349                                               &rockchip_i2s_tdm_component,
1350                                               i2s_tdm->dai, 1);
1351
1352         if (ret) {
1353                 dev_err(&pdev->dev, "Could not register DAI\n");
1354                 goto err_suspend;
1355         }
1356
1357         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1358         if (ret) {
1359                 dev_err(&pdev->dev, "Could not register PCM\n");
1360                 goto err_suspend;
1361         }
1362
1363         return 0;
1364
1365 err_suspend:
1366         if (!pm_runtime_status_suspended(&pdev->dev))
1367                 i2s_tdm_runtime_suspend(&pdev->dev);
1368         pm_runtime_disable(&pdev->dev);
1369
1370 err_disable_hclk:
1371         clk_disable_unprepare(i2s_tdm->hclk);
1372
1373         return ret;
1374 }
1375
1376 static int rockchip_i2s_tdm_remove(struct platform_device *pdev)
1377 {
1378         if (!pm_runtime_status_suspended(&pdev->dev))
1379                 i2s_tdm_runtime_suspend(&pdev->dev);
1380
1381         pm_runtime_disable(&pdev->dev);
1382
1383         return 0;
1384 }
1385
1386 static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev)
1387 {
1388         struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1389
1390         regcache_mark_dirty(i2s_tdm->regmap);
1391
1392         return 0;
1393 }
1394
1395 static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev)
1396 {
1397         struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1398         int ret;
1399
1400         ret = pm_runtime_resume_and_get(dev);
1401         if (ret < 0)
1402                 return ret;
1403         ret = regcache_sync(i2s_tdm->regmap);
1404         pm_runtime_put(dev);
1405
1406         return ret;
1407 }
1408
1409 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
1410         SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume,
1411                            NULL)
1412         SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend,
1413                                 rockchip_i2s_tdm_resume)
1414 };
1415
1416 static struct platform_driver rockchip_i2s_tdm_driver = {
1417         .probe = rockchip_i2s_tdm_probe,
1418         .remove = rockchip_i2s_tdm_remove,
1419         .driver = {
1420                 .name = DRV_NAME,
1421                 .of_match_table = of_match_ptr(rockchip_i2s_tdm_match),
1422                 .pm = &rockchip_i2s_tdm_pm_ops,
1423         },
1424 };
1425 module_platform_driver(rockchip_i2s_tdm_driver);
1426
1427 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
1428 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1429 MODULE_LICENSE("GPL v2");
1430 MODULE_ALIAS("platform:" DRV_NAME);
1431 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);