sound/soc/rockchip/rockchip_i2s.c

   1 /* sound/soc/rockchip/rockchip_i2s.c
   2  *
   3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
   4  *
   5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
   6  * Author: Jianqun <jay.xu@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/delay.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/of_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/dmaengine_pcm.h>
  23
  24 #include "rockchip_i2s.h"
  25 #include "rockchip_pcm.h"
  26
  27 #define DRV_NAME "rockchip-i2s"
  28
  29 struct rk_i2s_pins {
  30         u32 reg_offset;
  31         u32 shift;
  32 };
  33
  34 struct rk_i2s_dev {
  35         struct device *dev;
  36
  37         struct clk *hclk;
  38         struct clk *mclk;
  39
  40         struct snd_dmaengine_dai_dma_data capture_dma_data;
  41         struct snd_dmaengine_dai_dma_data playback_dma_data;
  42
  43         struct regmap *regmap;
  44         struct regmap *grf;
  45
  46 /*
  47  * Used to indicate the tx/rx status.
  48  * I2S controller hopes to start the tx and rx together,
  49  * also to stop them when they are both try to stop.
  50 */
  51         bool tx_start;
  52         bool rx_start;
  53         bool is_master_mode;
  54         const struct rk_i2s_pins *pins;
  55 };
  56
  57 static int i2s_runtime_suspend(struct device *dev)
  58 {
  59         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  60
  61         regcache_cache_only(i2s->regmap, true);
  62         clk_disable_unprepare(i2s->mclk);
  63
  64         return 0;
  65 }
  66
  67 static int i2s_runtime_resume(struct device *dev)
  68 {
  69         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  70         int ret;
  71
  72         ret = clk_prepare_enable(i2s->mclk);
  73         if (ret) {
  74                 dev_err(i2s->dev, "clock enable failed %d\n", ret);
  75                 return ret;
  76         }
  77
  78         regcache_cache_only(i2s->regmap, false);
  79         regcache_mark_dirty(i2s->regmap);
  80
  81         ret = regcache_sync(i2s->regmap);
  82         if (ret)
  83                 clk_disable_unprepare(i2s->mclk);
  84
  85         return ret;
  86 }
  87
  88 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
  89 {
  90         return snd_soc_dai_get_drvdata(dai);
  91 }
  92
  93 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
  94 {
  95         unsigned int val = 0;
  96         int retry = 10;
  97
  98         if (on) {
  99                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 100                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
 101
 102                 regmap_update_bits(i2s->regmap, I2S_XFER,
 103                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 104                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 105
 106                 i2s->tx_start = true;
 107         } else {
 108                 i2s->tx_start = false;
 109
 110                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 111                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
 112
 113                 if (!i2s->rx_start) {
 114                         regmap_update_bits(i2s->regmap, I2S_XFER,
 115                                            I2S_XFER_TXS_START |
 116                                            I2S_XFER_RXS_START,
 117                                            I2S_XFER_TXS_STOP |
 118                                            I2S_XFER_RXS_STOP);
 119
 120                         udelay(150);
 121                         regmap_update_bits(i2s->regmap, I2S_CLR,
 122                                            I2S_CLR_TXC | I2S_CLR_RXC,
 123                                            I2S_CLR_TXC | I2S_CLR_RXC);
 124
 125                         regmap_read(i2s->regmap, I2S_CLR, &val);
 126
 127                         /* Should wait for clear operation to finish */
 128                         while (val) {
 129                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 130                                 retry--;
 131                                 if (!retry) {
 132                                         dev_warn(i2s->dev, "fail to clear\n");
 133                                         break;
 134                                 }
 135                         }
 136                 }
 137         }
 138 }
 139
 140 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 141 {
 142         unsigned int val = 0;
 143         int retry = 10;
 144
 145         if (on) {
 146                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 147                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
 148
 149                 regmap_update_bits(i2s->regmap, I2S_XFER,
 150                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 151                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 152
 153                 i2s->rx_start = true;
 154         } else {
 155                 i2s->rx_start = false;
 156
 157                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 158                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
 159
 160                 if (!i2s->tx_start) {
 161                         regmap_update_bits(i2s->regmap, I2S_XFER,
 162                                            I2S_XFER_TXS_START |
 163                                            I2S_XFER_RXS_START,
 164                                            I2S_XFER_TXS_STOP |
 165                                            I2S_XFER_RXS_STOP);
 166
 167                         udelay(150);
 168                         regmap_update_bits(i2s->regmap, I2S_CLR,
 169                                            I2S_CLR_TXC | I2S_CLR_RXC,
 170                                            I2S_CLR_TXC | I2S_CLR_RXC);
 171
 172                         regmap_read(i2s->regmap, I2S_CLR, &val);
 173
 174                         /* Should wait for clear operation to finish */
 175                         while (val) {
 176                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 177                                 retry--;
 178                                 if (!retry) {
 179                                         dev_warn(i2s->dev, "fail to clear\n");
 180                                         break;
 181                                 }
 182                         }
 183                 }
 184         }
 185 }
 186
 187 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 188                                 unsigned int fmt)
 189 {
 190         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 191         unsigned int mask = 0, val = 0;
 192         int ret = 0;
 193
 194         pm_runtime_get_sync(cpu_dai->dev);
 195         mask = I2S_CKR_MSS_MASK;
 196         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 197         case SND_SOC_DAIFMT_CBS_CFS:
 198                 /* Set source clock in Master mode */
 199                 val = I2S_CKR_MSS_MASTER;
 200                 i2s->is_master_mode = true;
 201                 break;
 202         case SND_SOC_DAIFMT_CBM_CFM:
 203                 val = I2S_CKR_MSS_SLAVE;
 204                 i2s->is_master_mode = false;
 205                 break;
 206         default:
 207                 ret = -EINVAL;
 208                 goto err_pm_put;
 209         }
 210
 211         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 212
 213         mask = I2S_CKR_CKP_MASK;
 214         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 215         case SND_SOC_DAIFMT_NB_NF:
 216                 val = I2S_CKR_CKP_NEG;
 217                 break;
 218         case SND_SOC_DAIFMT_IB_NF:
 219                 val = I2S_CKR_CKP_POS;
 220                 break;
 221         default:
 222                 ret = -EINVAL;
 223                 goto err_pm_put;
 224         }
 225
 226         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 227
 228         mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
 229         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 230         case SND_SOC_DAIFMT_RIGHT_J:
 231                 val = I2S_TXCR_IBM_RSJM;
 232                 break;
 233         case SND_SOC_DAIFMT_LEFT_J:
 234                 val = I2S_TXCR_IBM_LSJM;
 235                 break;
 236         case SND_SOC_DAIFMT_I2S:
 237                 val = I2S_TXCR_IBM_NORMAL;
 238                 break;
 239         case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
 240                 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
 241                 break;
 242         case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
 243                 val = I2S_TXCR_TFS_PCM;
 244                 break;
 245         default:
 246                 ret = -EINVAL;
 247                 goto err_pm_put;
 248         }
 249
 250         regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
 251
 252         mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
 253         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 254         case SND_SOC_DAIFMT_RIGHT_J:
 255                 val = I2S_RXCR_IBM_RSJM;
 256                 break;
 257         case SND_SOC_DAIFMT_LEFT_J:
 258                 val = I2S_RXCR_IBM_LSJM;
 259                 break;
 260         case SND_SOC_DAIFMT_I2S:
 261                 val = I2S_RXCR_IBM_NORMAL;
 262                 break;
 263         case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
 264                 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
 265                 break;
 266         case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
 267                 val = I2S_RXCR_TFS_PCM;
 268                 break;
 269         default:
 270                 ret = -EINVAL;
 271                 goto err_pm_put;
 272         }
 273
 274         regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
 275
 276 err_pm_put:
 277         pm_runtime_put(cpu_dai->dev);
 278
 279         return ret;
 280 }
 281
 282 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 283                                   struct snd_pcm_hw_params *params,
 284                                   struct snd_soc_dai *dai)
 285 {
 286         struct rk_i2s_dev *i2s = to_info(dai);
 287         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 288         unsigned int val = 0;
 289         unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
 290
 291         if (i2s->is_master_mode) {
 292                 mclk_rate = clk_get_rate(i2s->mclk);
 293                 bclk_rate = 2 * 32 * params_rate(params);
 294                 if (bclk_rate && mclk_rate % bclk_rate)
 295                         return -EINVAL;
 296
 297                 div_bclk = mclk_rate / bclk_rate;
 298                 div_lrck = bclk_rate / params_rate(params);
 299                 regmap_update_bits(i2s->regmap, I2S_CKR,
 300                                    I2S_CKR_MDIV_MASK,
 301                                    I2S_CKR_MDIV(div_bclk));
 302
 303                 regmap_update_bits(i2s->regmap, I2S_CKR,
 304                                    I2S_CKR_TSD_MASK |
 305                                    I2S_CKR_RSD_MASK,
 306                                    I2S_CKR_TSD(div_lrck) |
 307                                    I2S_CKR_RSD(div_lrck));
 308         }
 309
 310         switch (params_format(params)) {
 311         case SNDRV_PCM_FORMAT_S8:
 312                 val |= I2S_TXCR_VDW(8);
 313                 break;
 314         case SNDRV_PCM_FORMAT_S16_LE:
 315                 val |= I2S_TXCR_VDW(16);
 316                 break;
 317         case SNDRV_PCM_FORMAT_S20_3LE:
 318                 val |= I2S_TXCR_VDW(20);
 319                 break;
 320         case SNDRV_PCM_FORMAT_S24_LE:
 321                 val |= I2S_TXCR_VDW(24);
 322                 break;
 323         case SNDRV_PCM_FORMAT_S32_LE:
 324                 val |= I2S_TXCR_VDW(32);
 325                 break;
 326         default:
 327                 return -EINVAL;
 328         }
 329
 330         switch (params_channels(params)) {
 331         case 8:
 332                 val |= I2S_CHN_8;
 333                 break;
 334         case 6:
 335                 val |= I2S_CHN_6;
 336                 break;
 337         case 4:
 338                 val |= I2S_CHN_4;
 339                 break;
 340         case 2:
 341                 val |= I2S_CHN_2;
 342                 break;
 343         default:
 344                 dev_err(i2s->dev, "invalid channel: %d\n",
 345                         params_channels(params));
 346                 return -EINVAL;
 347         }
 348
 349         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 350                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 351                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 352                                    val);
 353         else
 354                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 355                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 356                                    val);
 357
 358         if (!IS_ERR(i2s->grf) && i2s->pins) {
 359                 regmap_read(i2s->regmap, I2S_TXCR, &val);
 360                 val &= I2S_TXCR_CSR_MASK;
 361
 362                 switch (val) {
 363                 case I2S_CHN_4:
 364                         val = I2S_IO_4CH_OUT_6CH_IN;
 365                         break;
 366                 case I2S_CHN_6:
 367                         val = I2S_IO_6CH_OUT_4CH_IN;
 368                         break;
 369                 case I2S_CHN_8:
 370                         val = I2S_IO_8CH_OUT_2CH_IN;
 371                         break;
 372                 default:
 373                         val = I2S_IO_2CH_OUT_8CH_IN;
 374                         break;
 375                 }
 376
 377                 val <<= i2s->pins->shift;
 378                 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
 379                 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
 380         }
 381
 382         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
 383                            I2S_DMACR_TDL(16));
 384         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
 385                            I2S_DMACR_RDL(16));
 386
 387         val = I2S_CKR_TRCM_TXRX;
 388         if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
 389                 val = I2S_CKR_TRCM_TXONLY;
 390
 391         regmap_update_bits(i2s->regmap, I2S_CKR,
 392                            I2S_CKR_TRCM_MASK,
 393                            val);
 394         return 0;
 395 }
 396
 397 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
 398                                 int cmd, struct snd_soc_dai *dai)
 399 {
 400         struct rk_i2s_dev *i2s = to_info(dai);
 401         int ret = 0;
 402
 403         switch (cmd) {
 404         case SNDRV_PCM_TRIGGER_START:
 405         case SNDRV_PCM_TRIGGER_RESUME:
 406         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 407                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 408                         rockchip_snd_rxctrl(i2s, 1);
 409                 else
 410                         rockchip_snd_txctrl(i2s, 1);
 411                 break;
 412         case SNDRV_PCM_TRIGGER_SUSPEND:
 413         case SNDRV_PCM_TRIGGER_STOP:
 414         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 415                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 416                         rockchip_snd_rxctrl(i2s, 0);
 417                 else
 418                         rockchip_snd_txctrl(i2s, 0);
 419                 break;
 420         default:
 421                 ret = -EINVAL;
 422                 break;
 423         }
 424
 425         return ret;
 426 }
 427
 428 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
 429                                    unsigned int freq, int dir)
 430 {
 431         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 432         int ret;
 433
 434         ret = clk_set_rate(i2s->mclk, freq);
 435         if (ret)
 436                 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
 437
 438         return ret;
 439 }
 440
 441 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
 442 {
 443         struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
 444
 445         dai->capture_dma_data = &i2s->capture_dma_data;
 446         dai->playback_dma_data = &i2s->playback_dma_data;
 447
 448         return 0;
 449 }
 450
 451 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
 452         .hw_params = rockchip_i2s_hw_params,
 453         .set_sysclk = rockchip_i2s_set_sysclk,
 454         .set_fmt = rockchip_i2s_set_fmt,
 455         .trigger = rockchip_i2s_trigger,
 456 };
 457
 458 static struct snd_soc_dai_driver rockchip_i2s_dai = {
 459         .probe = rockchip_i2s_dai_probe,
 460         .playback = {
 461                 .stream_name = "Playback",
 462                 .channels_min = 2,
 463                 .channels_max = 8,
 464                 .rates = SNDRV_PCM_RATE_8000_192000,
 465                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 466                             SNDRV_PCM_FMTBIT_S16_LE |
 467                             SNDRV_PCM_FMTBIT_S20_3LE |
 468                             SNDRV_PCM_FMTBIT_S24_LE |
 469                             SNDRV_PCM_FMTBIT_S32_LE),
 470         },
 471         .capture = {
 472                 .stream_name = "Capture",
 473                 .channels_min = 2,
 474                 .channels_max = 2,
 475                 .rates = SNDRV_PCM_RATE_8000_192000,
 476                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 477                             SNDRV_PCM_FMTBIT_S16_LE |
 478                             SNDRV_PCM_FMTBIT_S20_3LE |
 479                             SNDRV_PCM_FMTBIT_S24_LE |
 480                             SNDRV_PCM_FMTBIT_S32_LE),
 481         },
 482         .ops = &rockchip_i2s_dai_ops,
 483         .symmetric_rates = 1,
 484 };
 485
 486 static const struct snd_soc_component_driver rockchip_i2s_component = {
 487         .name = DRV_NAME,
 488 };
 489
 490 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
 491 {
 492         switch (reg) {
 493         case I2S_TXCR:
 494         case I2S_RXCR:
 495         case I2S_CKR:
 496         case I2S_DMACR:
 497         case I2S_INTCR:
 498         case I2S_XFER:
 499         case I2S_CLR:
 500         case I2S_TXDR:
 501                 return true;
 502         default:
 503                 return false;
 504         }
 505 }
 506
 507 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
 508 {
 509         switch (reg) {
 510         case I2S_TXCR:
 511         case I2S_RXCR:
 512         case I2S_CKR:
 513         case I2S_DMACR:
 514         case I2S_INTCR:
 515         case I2S_XFER:
 516         case I2S_CLR:
 517         case I2S_TXDR:
 518         case I2S_RXDR:
 519         case I2S_FIFOLR:
 520         case I2S_INTSR:
 521                 return true;
 522         default:
 523                 return false;
 524         }
 525 }
 526
 527 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
 528 {
 529         switch (reg) {
 530         case I2S_INTSR:
 531         case I2S_CLR:
 532         case I2S_FIFOLR:
 533         case I2S_TXDR:
 534         case I2S_RXDR:
 535                 return true;
 536         default:
 537                 return false;
 538         }
 539 }
 540
 541 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
 542 {
 543         switch (reg) {
 544         case I2S_RXDR:
 545                 return true;
 546         default:
 547                 return false;
 548         }
 549 }
 550
 551 static const struct reg_default rockchip_i2s_reg_defaults[] = {
 552         {0x00, 0x0000000f},
 553         {0x04, 0x0000000f},
 554         {0x08, 0x00071f1f},
 555         {0x10, 0x001f0000},
 556         {0x14, 0x01f00000},
 557 };
 558
 559 static const struct regmap_config rockchip_i2s_regmap_config = {
 560         .reg_bits = 32,
 561         .reg_stride = 4,
 562         .val_bits = 32,
 563         .max_register = I2S_RXDR,
 564         .reg_defaults = rockchip_i2s_reg_defaults,
 565         .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
 566         .writeable_reg = rockchip_i2s_wr_reg,
 567         .readable_reg = rockchip_i2s_rd_reg,
 568         .volatile_reg = rockchip_i2s_volatile_reg,
 569         .precious_reg = rockchip_i2s_precious_reg,
 570         .cache_type = REGCACHE_FLAT,
 571 };
 572
 573 static const struct rk_i2s_pins rk3399_i2s_pins = {
 574         .reg_offset = 0xe220,
 575         .shift = 11,
 576 };
 577
 578 static const struct of_device_id rockchip_i2s_match[] = {
 579         { .compatible = "rockchip,rk3066-i2s", },
 580         { .compatible = "rockchip,rk3188-i2s", },
 581         { .compatible = "rockchip,rk3288-i2s", },
 582         { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
 583         {},
 584 };
 585
 586 static int rockchip_i2s_probe(struct platform_device *pdev)
 587 {
 588         struct device_node *node = pdev->dev.of_node;
 589         const struct of_device_id *of_id;
 590         struct rk_i2s_dev *i2s;
 591         struct snd_soc_dai_driver *soc_dai;
 592         struct resource *res;
 593         void __iomem *regs;
 594         int ret;
 595         int val;
 596
 597         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 598         if (!i2s)
 599                 return -ENOMEM;
 600
 601         i2s->dev = &pdev->dev;
 602
 603         i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
 604         if (!IS_ERR(i2s->grf)) {
 605                 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
 606                 if (!of_id || !of_id->data)
 607                         return -EINVAL;
 608
 609                 i2s->pins = of_id->data;
 610         }
 611
 612         /* try to prepare related clocks */
 613         i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
 614         if (IS_ERR(i2s->hclk)) {
 615                 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
 616                 return PTR_ERR(i2s->hclk);
 617         }
 618         ret = clk_prepare_enable(i2s->hclk);
 619         if (ret) {
 620                 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
 621                 return ret;
 622         }
 623
 624         i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
 625         if (IS_ERR(i2s->mclk)) {
 626                 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
 627                 return PTR_ERR(i2s->mclk);
 628         }
 629
 630         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 631         regs = devm_ioremap_resource(&pdev->dev, res);
 632         if (IS_ERR(regs))
 633                 return PTR_ERR(regs);
 634
 635         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 636                                             &rockchip_i2s_regmap_config);
 637         if (IS_ERR(i2s->regmap)) {
 638                 dev_err(&pdev->dev,
 639                         "Failed to initialise managed register map\n");
 640                 return PTR_ERR(i2s->regmap);
 641         }
 642
 643         i2s->playback_dma_data.addr = res->start + I2S_TXDR;
 644         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 645         i2s->playback_dma_data.maxburst = 4;
 646
 647         i2s->capture_dma_data.addr = res->start + I2S_RXDR;
 648         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 649         i2s->capture_dma_data.maxburst = 4;
 650
 651         dev_set_drvdata(&pdev->dev, i2s);
 652
 653         pm_runtime_enable(&pdev->dev);
 654         if (!pm_runtime_enabled(&pdev->dev)) {
 655                 ret = i2s_runtime_resume(&pdev->dev);
 656                 if (ret)
 657                         goto err_pm_disable;
 658         }
 659
 660         soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai,
 661                                sizeof(*soc_dai), GFP_KERNEL);
 662         if (!soc_dai) {
 663                 ret = -ENOMEM;
 664                 goto err_pm_disable;
 665         }
 666
 667         if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
 668                 if (val >= 2 && val <= 8)
 669                         soc_dai->playback.channels_max = val;
 670         }
 671
 672         if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
 673                 if (val >= 2 && val <= 8)
 674                         soc_dai->capture.channels_max = val;
 675         }
 676
 677         ret = devm_snd_soc_register_component(&pdev->dev,
 678                                               &rockchip_i2s_component,
 679                                               soc_dai, 1);
 680
 681         if (ret) {
 682                 dev_err(&pdev->dev, "Could not register DAI\n");
 683                 goto err_suspend;
 684         }
 685
 686         ret = rockchip_pcm_platform_register(&pdev->dev);
 687         if (ret) {
 688                 dev_err(&pdev->dev, "Could not register PCM\n");
 689                 goto err_suspend;
 690         }
 691
 692         return 0;
 693
 694 err_suspend:
 695         if (!pm_runtime_status_suspended(&pdev->dev))
 696                 i2s_runtime_suspend(&pdev->dev);
 697 err_pm_disable:
 698         pm_runtime_disable(&pdev->dev);
 699
 700         return ret;
 701 }
 702
 703 static int rockchip_i2s_remove(struct platform_device *pdev)
 704 {
 705         struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
 706
 707         pm_runtime_disable(&pdev->dev);
 708         if (!pm_runtime_status_suspended(&pdev->dev))
 709                 i2s_runtime_suspend(&pdev->dev);
 710
 711         clk_disable_unprepare(i2s->hclk);
 712
 713         return 0;
 714 }
 715
 716 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
 717         SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
 718                            NULL)
 719 };
 720
 721 static struct platform_driver rockchip_i2s_driver = {
 722         .probe = rockchip_i2s_probe,
 723         .remove = rockchip_i2s_remove,
 724         .driver = {
 725                 .name = DRV_NAME,
 726                 .of_match_table = of_match_ptr(rockchip_i2s_match),
 727                 .pm = &rockchip_i2s_pm_ops,
 728         },
 729 };
 730 module_platform_driver(rockchip_i2s_driver);
 731
 732 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
 733 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
 734 MODULE_LICENSE("GPL v2");
 735 MODULE_ALIAS("platform:" DRV_NAME);
 736 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);