1 // SPDX-License-Identifier: GPL-2.0-only
2 /* sound/soc/rockchip/rockchip_i2s.c
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun <jay.xu@rock-chips.com>
10 #include <linux/module.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/delay.h>
14 #include <linux/of_gpio.h>
15 #include <linux/clk.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <linux/spinlock.h>
20 #include <sound/pcm_params.h>
21 #include <sound/dmaengine_pcm.h>
23 #include "rockchip_i2s.h"
25 #define DRV_NAME "rockchip-i2s"
38 struct snd_dmaengine_dai_dma_data capture_dma_data;
39 struct snd_dmaengine_dai_dma_data playback_dma_data;
41 struct regmap *regmap;
48 * Used to indicate the tx/rx status.
49 * I2S controller hopes to start the tx and rx together,
50 * also to stop them when they are both try to stop.
55 const struct rk_i2s_pins *pins;
56 unsigned int bclk_ratio;
57 spinlock_t lock; /* tx/rx lock */
58 struct pinctrl *pinctrl;
59 struct pinctrl_state *bclk_on;
60 struct pinctrl_state *bclk_off;
63 static int i2s_pinctrl_select_bclk_on(struct rk_i2s_dev *i2s)
67 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_on))
68 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_on);
71 dev_err(i2s->dev, "bclk enable failed %d\n", ret);
76 static int i2s_pinctrl_select_bclk_off(struct rk_i2s_dev *i2s)
81 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_off))
82 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_off);
85 dev_err(i2s->dev, "bclk disable failed %d\n", ret);
90 static int i2s_runtime_suspend(struct device *dev)
92 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
94 regcache_cache_only(i2s->regmap, true);
95 clk_disable_unprepare(i2s->mclk);
100 static int i2s_runtime_resume(struct device *dev)
102 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
105 ret = clk_prepare_enable(i2s->mclk);
107 dev_err(i2s->dev, "clock enable failed %d\n", ret);
111 regcache_cache_only(i2s->regmap, false);
112 regcache_mark_dirty(i2s->regmap);
114 ret = regcache_sync(i2s->regmap);
116 clk_disable_unprepare(i2s->mclk);
121 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
123 return snd_soc_dai_get_drvdata(dai);
126 static int rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
128 unsigned int val = 0;
131 spin_lock(&i2s->lock);
133 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
134 I2S_DMACR_TDE_ENABLE,
135 I2S_DMACR_TDE_ENABLE);
138 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
139 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
140 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
143 i2s->tx_start = true;
145 i2s->tx_start = false;
147 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
148 I2S_DMACR_TDE_ENABLE,
149 I2S_DMACR_TDE_DISABLE);
153 if (!i2s->rx_start) {
154 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
155 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
156 I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
160 ret = regmap_update_bits(i2s->regmap, I2S_CLR,
161 I2S_CLR_TXC | I2S_CLR_RXC,
162 I2S_CLR_TXC | I2S_CLR_RXC);
165 ret = regmap_read_poll_timeout_atomic(i2s->regmap,
172 dev_warn(i2s->dev, "fail to clear: %d\n", ret);
176 spin_unlock(&i2s->lock);
178 dev_err(i2s->dev, "lrclk update failed\n");
183 static int rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
185 unsigned int val = 0;
188 spin_lock(&i2s->lock);
190 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
191 I2S_DMACR_RDE_ENABLE,
192 I2S_DMACR_RDE_ENABLE);
196 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
197 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
198 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
201 i2s->rx_start = true;
203 i2s->rx_start = false;
205 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
206 I2S_DMACR_RDE_ENABLE,
207 I2S_DMACR_RDE_DISABLE);
211 if (!i2s->tx_start) {
212 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
213 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
214 I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
218 ret = regmap_update_bits(i2s->regmap, I2S_CLR,
219 I2S_CLR_TXC | I2S_CLR_RXC,
220 I2S_CLR_TXC | I2S_CLR_RXC);
223 ret = regmap_read_poll_timeout_atomic(i2s->regmap,
230 dev_warn(i2s->dev, "fail to clear: %d\n", ret);
234 spin_unlock(&i2s->lock);
236 dev_err(i2s->dev, "lrclk update failed\n");
241 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
244 struct rk_i2s_dev *i2s = to_info(cpu_dai);
245 unsigned int mask = 0, val = 0;
248 pm_runtime_get_sync(cpu_dai->dev);
249 mask = I2S_CKR_MSS_MASK;
250 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
251 case SND_SOC_DAIFMT_BP_FP:
252 /* Set source clock in Master mode */
253 val = I2S_CKR_MSS_MASTER;
254 i2s->is_master_mode = true;
256 case SND_SOC_DAIFMT_BC_FC:
257 val = I2S_CKR_MSS_SLAVE;
258 i2s->is_master_mode = false;
265 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
267 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
268 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
269 case SND_SOC_DAIFMT_NB_NF:
270 val = I2S_CKR_CKP_NORMAL |
274 case SND_SOC_DAIFMT_NB_IF:
275 val = I2S_CKR_CKP_NORMAL |
276 I2S_CKR_TLP_INVERTED |
277 I2S_CKR_RLP_INVERTED;
279 case SND_SOC_DAIFMT_IB_NF:
280 val = I2S_CKR_CKP_INVERTED |
284 case SND_SOC_DAIFMT_IB_IF:
285 val = I2S_CKR_CKP_INVERTED |
286 I2S_CKR_TLP_INVERTED |
287 I2S_CKR_RLP_INVERTED;
294 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
296 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
297 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
298 case SND_SOC_DAIFMT_RIGHT_J:
299 val = I2S_TXCR_IBM_RSJM;
301 case SND_SOC_DAIFMT_LEFT_J:
302 val = I2S_TXCR_IBM_LSJM;
304 case SND_SOC_DAIFMT_I2S:
305 val = I2S_TXCR_IBM_NORMAL;
307 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
308 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
310 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
311 val = I2S_TXCR_TFS_PCM;
318 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
320 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
321 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
322 case SND_SOC_DAIFMT_RIGHT_J:
323 val = I2S_RXCR_IBM_RSJM;
325 case SND_SOC_DAIFMT_LEFT_J:
326 val = I2S_RXCR_IBM_LSJM;
328 case SND_SOC_DAIFMT_I2S:
329 val = I2S_RXCR_IBM_NORMAL;
331 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
332 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
334 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
335 val = I2S_RXCR_TFS_PCM;
342 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
345 pm_runtime_put(cpu_dai->dev);
350 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
351 struct snd_pcm_hw_params *params,
352 struct snd_soc_dai *dai)
354 struct rk_i2s_dev *i2s = to_info(dai);
355 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
356 unsigned int val = 0;
357 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
359 if (i2s->is_master_mode) {
360 mclk_rate = clk_get_rate(i2s->mclk);
361 bclk_rate = i2s->bclk_ratio * params_rate(params);
365 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
366 div_lrck = bclk_rate / params_rate(params);
367 regmap_update_bits(i2s->regmap, I2S_CKR,
369 I2S_CKR_MDIV(div_bclk));
371 regmap_update_bits(i2s->regmap, I2S_CKR,
374 I2S_CKR_TSD(div_lrck) |
375 I2S_CKR_RSD(div_lrck));
378 switch (params_format(params)) {
379 case SNDRV_PCM_FORMAT_S8:
380 val |= I2S_TXCR_VDW(8);
382 case SNDRV_PCM_FORMAT_S16_LE:
383 val |= I2S_TXCR_VDW(16);
385 case SNDRV_PCM_FORMAT_S20_3LE:
386 val |= I2S_TXCR_VDW(20);
388 case SNDRV_PCM_FORMAT_S24_LE:
389 val |= I2S_TXCR_VDW(24);
391 case SNDRV_PCM_FORMAT_S32_LE:
392 val |= I2S_TXCR_VDW(32);
398 switch (params_channels(params)) {
412 dev_err(i2s->dev, "invalid channel: %d\n",
413 params_channels(params));
417 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
418 regmap_update_bits(i2s->regmap, I2S_RXCR,
419 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
422 regmap_update_bits(i2s->regmap, I2S_TXCR,
423 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
426 if (!IS_ERR(i2s->grf) && i2s->pins) {
427 regmap_read(i2s->regmap, I2S_TXCR, &val);
428 val &= I2S_TXCR_CSR_MASK;
432 val = I2S_IO_4CH_OUT_6CH_IN;
435 val = I2S_IO_6CH_OUT_4CH_IN;
438 val = I2S_IO_8CH_OUT_2CH_IN;
441 val = I2S_IO_2CH_OUT_8CH_IN;
445 val <<= i2s->pins->shift;
446 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
447 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
450 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
452 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
455 val = I2S_CKR_TRCM_TXRX;
456 if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate)
457 val = I2S_CKR_TRCM_TXONLY;
459 regmap_update_bits(i2s->regmap, I2S_CKR,
465 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
466 int cmd, struct snd_soc_dai *dai)
468 struct rk_i2s_dev *i2s = to_info(dai);
472 case SNDRV_PCM_TRIGGER_START:
473 case SNDRV_PCM_TRIGGER_RESUME:
474 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
475 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
476 ret = rockchip_snd_rxctrl(i2s, 1);
478 ret = rockchip_snd_txctrl(i2s, 1);
481 i2s_pinctrl_select_bclk_on(i2s);
483 case SNDRV_PCM_TRIGGER_SUSPEND:
484 case SNDRV_PCM_TRIGGER_STOP:
485 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
486 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
488 i2s_pinctrl_select_bclk_off(i2s);
489 ret = rockchip_snd_rxctrl(i2s, 0);
492 i2s_pinctrl_select_bclk_off(i2s);
493 ret = rockchip_snd_txctrl(i2s, 0);
504 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
507 struct rk_i2s_dev *i2s = to_info(dai);
509 i2s->bclk_ratio = ratio;
514 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
515 unsigned int freq, int dir)
517 struct rk_i2s_dev *i2s = to_info(cpu_dai);
523 ret = clk_set_rate(i2s->mclk, freq);
525 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
530 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
532 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
534 snd_soc_dai_init_dma_data(dai,
535 i2s->has_playback ? &i2s->playback_dma_data : NULL,
536 i2s->has_capture ? &i2s->capture_dma_data : NULL);
541 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
542 .probe = rockchip_i2s_dai_probe,
543 .hw_params = rockchip_i2s_hw_params,
544 .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
545 .set_sysclk = rockchip_i2s_set_sysclk,
546 .set_fmt = rockchip_i2s_set_fmt,
547 .trigger = rockchip_i2s_trigger,
550 static struct snd_soc_dai_driver rockchip_i2s_dai = {
551 .ops = &rockchip_i2s_dai_ops,
555 static const struct snd_soc_component_driver rockchip_i2s_component = {
557 .legacy_dai_naming = 1,
560 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
577 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
597 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
611 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
621 static const struct reg_default rockchip_i2s_reg_defaults[] = {
629 static const struct regmap_config rockchip_i2s_regmap_config = {
633 .max_register = I2S_RXDR,
634 .reg_defaults = rockchip_i2s_reg_defaults,
635 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
636 .writeable_reg = rockchip_i2s_wr_reg,
637 .readable_reg = rockchip_i2s_rd_reg,
638 .volatile_reg = rockchip_i2s_volatile_reg,
639 .precious_reg = rockchip_i2s_precious_reg,
640 .cache_type = REGCACHE_FLAT,
643 static const struct rk_i2s_pins rk3399_i2s_pins = {
644 .reg_offset = 0xe220,
648 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
649 { .compatible = "rockchip,px30-i2s", },
650 { .compatible = "rockchip,rk1808-i2s", },
651 { .compatible = "rockchip,rk3036-i2s", },
652 { .compatible = "rockchip,rk3066-i2s", },
653 { .compatible = "rockchip,rk3128-i2s", },
654 { .compatible = "rockchip,rk3188-i2s", },
655 { .compatible = "rockchip,rk3228-i2s", },
656 { .compatible = "rockchip,rk3288-i2s", },
657 { .compatible = "rockchip,rk3308-i2s", },
658 { .compatible = "rockchip,rk3328-i2s", },
659 { .compatible = "rockchip,rk3366-i2s", },
660 { .compatible = "rockchip,rk3368-i2s", },
661 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
662 { .compatible = "rockchip,rk3588-i2s", },
663 { .compatible = "rockchip,rv1126-i2s", },
667 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
668 struct snd_soc_dai_driver **dp)
670 struct device_node *node = i2s->dev->of_node;
671 struct snd_soc_dai_driver *dai;
672 struct property *dma_names;
673 const char *dma_name;
676 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
677 if (!strcmp(dma_name, "tx"))
678 i2s->has_playback = true;
679 if (!strcmp(dma_name, "rx"))
680 i2s->has_capture = true;
683 dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
684 sizeof(*dai), GFP_KERNEL);
688 if (i2s->has_playback) {
689 dai->playback.stream_name = "Playback";
690 dai->playback.channels_min = 2;
691 dai->playback.channels_max = 8;
692 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
693 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
694 SNDRV_PCM_FMTBIT_S16_LE |
695 SNDRV_PCM_FMTBIT_S20_3LE |
696 SNDRV_PCM_FMTBIT_S24_LE |
697 SNDRV_PCM_FMTBIT_S32_LE;
699 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
700 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
701 i2s->playback_dma_data.maxburst = 8;
703 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
704 if (val >= 2 && val <= 8)
705 dai->playback.channels_max = val;
709 if (i2s->has_capture) {
710 dai->capture.stream_name = "Capture";
711 dai->capture.channels_min = 2;
712 dai->capture.channels_max = 8;
713 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
714 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
715 SNDRV_PCM_FMTBIT_S16_LE |
716 SNDRV_PCM_FMTBIT_S20_3LE |
717 SNDRV_PCM_FMTBIT_S24_LE |
718 SNDRV_PCM_FMTBIT_S32_LE;
720 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
721 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
722 i2s->capture_dma_data.maxburst = 8;
724 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
725 if (val >= 2 && val <= 8)
726 dai->capture.channels_max = val;
736 static int rockchip_i2s_probe(struct platform_device *pdev)
738 struct device_node *node = pdev->dev.of_node;
739 struct rk_i2s_dev *i2s;
740 struct snd_soc_dai_driver *dai;
741 struct resource *res;
745 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
749 spin_lock_init(&i2s->lock);
750 i2s->dev = &pdev->dev;
752 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
753 if (!IS_ERR(i2s->grf)) {
754 i2s->pins = device_get_match_data(&pdev->dev);
760 /* try to prepare related clocks */
761 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
762 if (IS_ERR(i2s->hclk)) {
763 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
764 return PTR_ERR(i2s->hclk);
766 ret = clk_prepare_enable(i2s->hclk);
768 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
772 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
773 if (IS_ERR(i2s->mclk)) {
774 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
775 ret = PTR_ERR(i2s->mclk);
779 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
785 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
786 &rockchip_i2s_regmap_config);
787 if (IS_ERR(i2s->regmap)) {
789 "Failed to initialise managed register map\n");
790 ret = PTR_ERR(i2s->regmap);
794 i2s->bclk_ratio = 64;
795 i2s->pinctrl = devm_pinctrl_get(&pdev->dev);
796 if (!IS_ERR(i2s->pinctrl)) {
797 i2s->bclk_on = pinctrl_lookup_state(i2s->pinctrl, "bclk_on");
798 if (!IS_ERR_OR_NULL(i2s->bclk_on)) {
799 i2s->bclk_off = pinctrl_lookup_state(i2s->pinctrl, "bclk_off");
800 if (IS_ERR_OR_NULL(i2s->bclk_off)) {
801 dev_err(&pdev->dev, "failed to find i2s bclk_off\n");
807 dev_dbg(&pdev->dev, "failed to find i2s pinctrl\n");
810 i2s_pinctrl_select_bclk_off(i2s);
812 dev_set_drvdata(&pdev->dev, i2s);
814 pm_runtime_enable(&pdev->dev);
815 if (!pm_runtime_enabled(&pdev->dev)) {
816 ret = i2s_runtime_resume(&pdev->dev);
821 ret = rockchip_i2s_init_dai(i2s, res, &dai);
825 ret = devm_snd_soc_register_component(&pdev->dev,
826 &rockchip_i2s_component,
830 dev_err(&pdev->dev, "Could not register DAI\n");
834 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
836 dev_err(&pdev->dev, "Could not register PCM\n");
843 if (!pm_runtime_status_suspended(&pdev->dev))
844 i2s_runtime_suspend(&pdev->dev);
846 pm_runtime_disable(&pdev->dev);
848 clk_disable_unprepare(i2s->hclk);
852 static void rockchip_i2s_remove(struct platform_device *pdev)
854 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
856 pm_runtime_disable(&pdev->dev);
857 if (!pm_runtime_status_suspended(&pdev->dev))
858 i2s_runtime_suspend(&pdev->dev);
860 clk_disable_unprepare(i2s->hclk);
863 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
864 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
868 static struct platform_driver rockchip_i2s_driver = {
869 .probe = rockchip_i2s_probe,
870 .remove_new = rockchip_i2s_remove,
873 .of_match_table = of_match_ptr(rockchip_i2s_match),
874 .pm = &rockchip_i2s_pm_ops,
877 module_platform_driver(rockchip_i2s_driver);
879 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
880 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
881 MODULE_LICENSE("GPL v2");
882 MODULE_ALIAS("platform:" DRV_NAME);
883 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);