sound/soc/rockchip/rockchip_i2s.c

   1 /* sound/soc/rockchip/rockchip_i2s.c
   2  *
   3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
   4  *
   5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
   6  * Author: Jianqun <jay.xu@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/delay.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/of_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/dmaengine_pcm.h>
  23
  24 #include "rockchip_i2s.h"
  25
  26 #define DRV_NAME "rockchip-i2s"
  27
  28 struct rk_i2s_pins {
  29         u32 reg_offset;
  30         u32 shift;
  31 };
  32
  33 struct rk_i2s_dev {
  34         struct device *dev;
  35
  36         struct clk *hclk;
  37         struct clk *mclk;
  38
  39         struct snd_dmaengine_dai_dma_data capture_dma_data;
  40         struct snd_dmaengine_dai_dma_data playback_dma_data;
  41
  42         struct regmap *regmap;
  43         struct regmap *grf;
  44
  45 /*
  46  * Used to indicate the tx/rx status.
  47  * I2S controller hopes to start the tx and rx together,
  48  * also to stop them when they are both try to stop.
  49 */
  50         bool tx_start;
  51         bool rx_start;
  52         bool is_master_mode;
  53         const struct rk_i2s_pins *pins;
  54 };
  55
  56 static int i2s_runtime_suspend(struct device *dev)
  57 {
  58         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  59
  60         regcache_cache_only(i2s->regmap, true);
  61         clk_disable_unprepare(i2s->mclk);
  62
  63         return 0;
  64 }
  65
  66 static int i2s_runtime_resume(struct device *dev)
  67 {
  68         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  69         int ret;
  70
  71         ret = clk_prepare_enable(i2s->mclk);
  72         if (ret) {
  73                 dev_err(i2s->dev, "clock enable failed %d\n", ret);
  74                 return ret;
  75         }
  76
  77         regcache_cache_only(i2s->regmap, false);
  78         regcache_mark_dirty(i2s->regmap);
  79
  80         ret = regcache_sync(i2s->regmap);
  81         if (ret)
  82                 clk_disable_unprepare(i2s->mclk);
  83
  84         return ret;
  85 }
  86
  87 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
  88 {
  89         return snd_soc_dai_get_drvdata(dai);
  90 }
  91
  92 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
  93 {
  94         unsigned int val = 0;
  95         int retry = 10;
  96
  97         if (on) {
  98                 regmap_update_bits(i2s->regmap, I2S_DMACR,
  99                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
 100
 101                 regmap_update_bits(i2s->regmap, I2S_XFER,
 102                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 103                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 104
 105                 i2s->tx_start = true;
 106         } else {
 107                 i2s->tx_start = false;
 108
 109                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 110                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
 111
 112                 if (!i2s->rx_start) {
 113                         regmap_update_bits(i2s->regmap, I2S_XFER,
 114                                            I2S_XFER_TXS_START |
 115                                            I2S_XFER_RXS_START,
 116                                            I2S_XFER_TXS_STOP |
 117                                            I2S_XFER_RXS_STOP);
 118
 119                         udelay(150);
 120                         regmap_update_bits(i2s->regmap, I2S_CLR,
 121                                            I2S_CLR_TXC | I2S_CLR_RXC,
 122                                            I2S_CLR_TXC | I2S_CLR_RXC);
 123
 124                         regmap_read(i2s->regmap, I2S_CLR, &val);
 125
 126                         /* Should wait for clear operation to finish */
 127                         while (val) {
 128                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 129                                 retry--;
 130                                 if (!retry) {
 131                                         dev_warn(i2s->dev, "fail to clear\n");
 132                                         break;
 133                                 }
 134                         }
 135                 }
 136         }
 137 }
 138
 139 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 140 {
 141         unsigned int val = 0;
 142         int retry = 10;
 143
 144         if (on) {
 145                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 146                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
 147
 148                 regmap_update_bits(i2s->regmap, I2S_XFER,
 149                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 150                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 151
 152                 i2s->rx_start = true;
 153         } else {
 154                 i2s->rx_start = false;
 155
 156                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 157                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
 158
 159                 if (!i2s->tx_start) {
 160                         regmap_update_bits(i2s->regmap, I2S_XFER,
 161                                            I2S_XFER_TXS_START |
 162                                            I2S_XFER_RXS_START,
 163                                            I2S_XFER_TXS_STOP |
 164                                            I2S_XFER_RXS_STOP);
 165
 166                         udelay(150);
 167                         regmap_update_bits(i2s->regmap, I2S_CLR,
 168                                            I2S_CLR_TXC | I2S_CLR_RXC,
 169                                            I2S_CLR_TXC | I2S_CLR_RXC);
 170
 171                         regmap_read(i2s->regmap, I2S_CLR, &val);
 172
 173                         /* Should wait for clear operation to finish */
 174                         while (val) {
 175                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 176                                 retry--;
 177                                 if (!retry) {
 178                                         dev_warn(i2s->dev, "fail to clear\n");
 179                                         break;
 180                                 }
 181                         }
 182                 }
 183         }
 184 }
 185
 186 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 187                                 unsigned int fmt)
 188 {
 189         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 190         unsigned int mask = 0, val = 0;
 191         int ret = 0;
 192
 193         pm_runtime_get_sync(cpu_dai->dev);
 194         mask = I2S_CKR_MSS_MASK;
 195         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 196         case SND_SOC_DAIFMT_CBS_CFS:
 197                 /* Set source clock in Master mode */
 198                 val = I2S_CKR_MSS_MASTER;
 199                 i2s->is_master_mode = true;
 200                 break;
 201         case SND_SOC_DAIFMT_CBM_CFM:
 202                 val = I2S_CKR_MSS_SLAVE;
 203                 i2s->is_master_mode = false;
 204                 break;
 205         default:
 206                 ret = -EINVAL;
 207                 goto err_pm_put;
 208         }
 209
 210         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 211
 212         mask = I2S_CKR_CKP_MASK;
 213         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 214         case SND_SOC_DAIFMT_NB_NF:
 215                 val = I2S_CKR_CKP_NEG;
 216                 break;
 217         case SND_SOC_DAIFMT_IB_NF:
 218                 val = I2S_CKR_CKP_POS;
 219                 break;
 220         default:
 221                 ret = -EINVAL;
 222                 goto err_pm_put;
 223         }
 224
 225         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 226
 227         mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
 228         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 229         case SND_SOC_DAIFMT_RIGHT_J:
 230                 val = I2S_TXCR_IBM_RSJM;
 231                 break;
 232         case SND_SOC_DAIFMT_LEFT_J:
 233                 val = I2S_TXCR_IBM_LSJM;
 234                 break;
 235         case SND_SOC_DAIFMT_I2S:
 236                 val = I2S_TXCR_IBM_NORMAL;
 237                 break;
 238         case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
 239                 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
 240                 break;
 241         case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
 242                 val = I2S_TXCR_TFS_PCM;
 243                 break;
 244         default:
 245                 ret = -EINVAL;
 246                 goto err_pm_put;
 247         }
 248
 249         regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
 250
 251         mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
 252         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 253         case SND_SOC_DAIFMT_RIGHT_J:
 254                 val = I2S_RXCR_IBM_RSJM;
 255                 break;
 256         case SND_SOC_DAIFMT_LEFT_J:
 257                 val = I2S_RXCR_IBM_LSJM;
 258                 break;
 259         case SND_SOC_DAIFMT_I2S:
 260                 val = I2S_RXCR_IBM_NORMAL;
 261                 break;
 262         case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
 263                 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
 264                 break;
 265         case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
 266                 val = I2S_RXCR_TFS_PCM;
 267                 break;
 268         default:
 269                 ret = -EINVAL;
 270                 goto err_pm_put;
 271         }
 272
 273         regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
 274
 275 err_pm_put:
 276         pm_runtime_put(cpu_dai->dev);
 277
 278         return ret;
 279 }
 280
 281 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 282                                   struct snd_pcm_hw_params *params,
 283                                   struct snd_soc_dai *dai)
 284 {
 285         struct rk_i2s_dev *i2s = to_info(dai);
 286         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 287         unsigned int val = 0;
 288         unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
 289
 290         if (i2s->is_master_mode) {
 291                 mclk_rate = clk_get_rate(i2s->mclk);
 292                 bclk_rate = 2 * 32 * params_rate(params);
 293                 if (bclk_rate && mclk_rate % bclk_rate)
 294                         return -EINVAL;
 295
 296                 div_bclk = mclk_rate / bclk_rate;
 297                 div_lrck = bclk_rate / params_rate(params);
 298                 regmap_update_bits(i2s->regmap, I2S_CKR,
 299                                    I2S_CKR_MDIV_MASK,
 300                                    I2S_CKR_MDIV(div_bclk));
 301
 302                 regmap_update_bits(i2s->regmap, I2S_CKR,
 303                                    I2S_CKR_TSD_MASK |
 304                                    I2S_CKR_RSD_MASK,
 305                                    I2S_CKR_TSD(div_lrck) |
 306                                    I2S_CKR_RSD(div_lrck));
 307         }
 308
 309         switch (params_format(params)) {
 310         case SNDRV_PCM_FORMAT_S8:
 311                 val |= I2S_TXCR_VDW(8);
 312                 break;
 313         case SNDRV_PCM_FORMAT_S16_LE:
 314                 val |= I2S_TXCR_VDW(16);
 315                 break;
 316         case SNDRV_PCM_FORMAT_S20_3LE:
 317                 val |= I2S_TXCR_VDW(20);
 318                 break;
 319         case SNDRV_PCM_FORMAT_S24_LE:
 320                 val |= I2S_TXCR_VDW(24);
 321                 break;
 322         case SNDRV_PCM_FORMAT_S32_LE:
 323                 val |= I2S_TXCR_VDW(32);
 324                 break;
 325         default:
 326                 return -EINVAL;
 327         }
 328
 329         switch (params_channels(params)) {
 330         case 8:
 331                 val |= I2S_CHN_8;
 332                 break;
 333         case 6:
 334                 val |= I2S_CHN_6;
 335                 break;
 336         case 4:
 337                 val |= I2S_CHN_4;
 338                 break;
 339         case 2:
 340                 val |= I2S_CHN_2;
 341                 break;
 342         default:
 343                 dev_err(i2s->dev, "invalid channel: %d\n",
 344                         params_channels(params));
 345                 return -EINVAL;
 346         }
 347
 348         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 349                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 350                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 351                                    val);
 352         else
 353                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 354                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 355                                    val);
 356
 357         if (!IS_ERR(i2s->grf) && i2s->pins) {
 358                 regmap_read(i2s->regmap, I2S_TXCR, &val);
 359                 val &= I2S_TXCR_CSR_MASK;
 360
 361                 switch (val) {
 362                 case I2S_CHN_4:
 363                         val = I2S_IO_4CH_OUT_6CH_IN;
 364                         break;
 365                 case I2S_CHN_6:
 366                         val = I2S_IO_6CH_OUT_4CH_IN;
 367                         break;
 368                 case I2S_CHN_8:
 369                         val = I2S_IO_8CH_OUT_2CH_IN;
 370                         break;
 371                 default:
 372                         val = I2S_IO_2CH_OUT_8CH_IN;
 373                         break;
 374                 }
 375
 376                 val <<= i2s->pins->shift;
 377                 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
 378                 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
 379         }
 380
 381         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
 382                            I2S_DMACR_TDL(16));
 383         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
 384                            I2S_DMACR_RDL(16));
 385
 386         val = I2S_CKR_TRCM_TXRX;
 387         if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
 388                 val = I2S_CKR_TRCM_TXONLY;
 389
 390         regmap_update_bits(i2s->regmap, I2S_CKR,
 391                            I2S_CKR_TRCM_MASK,
 392                            val);
 393         return 0;
 394 }
 395
 396 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
 397                                 int cmd, struct snd_soc_dai *dai)
 398 {
 399         struct rk_i2s_dev *i2s = to_info(dai);
 400         int ret = 0;
 401
 402         switch (cmd) {
 403         case SNDRV_PCM_TRIGGER_START:
 404         case SNDRV_PCM_TRIGGER_RESUME:
 405         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 406                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 407                         rockchip_snd_rxctrl(i2s, 1);
 408                 else
 409                         rockchip_snd_txctrl(i2s, 1);
 410                 break;
 411         case SNDRV_PCM_TRIGGER_SUSPEND:
 412         case SNDRV_PCM_TRIGGER_STOP:
 413         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 414                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 415                         rockchip_snd_rxctrl(i2s, 0);
 416                 else
 417                         rockchip_snd_txctrl(i2s, 0);
 418                 break;
 419         default:
 420                 ret = -EINVAL;
 421                 break;
 422         }
 423
 424         return ret;
 425 }
 426
 427 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
 428                                    unsigned int freq, int dir)
 429 {
 430         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 431         int ret;
 432
 433         ret = clk_set_rate(i2s->mclk, freq);
 434         if (ret)
 435                 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
 436
 437         return ret;
 438 }
 439
 440 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
 441 {
 442         struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
 443
 444         dai->capture_dma_data = &i2s->capture_dma_data;
 445         dai->playback_dma_data = &i2s->playback_dma_data;
 446
 447         return 0;
 448 }
 449
 450 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
 451         .hw_params = rockchip_i2s_hw_params,
 452         .set_sysclk = rockchip_i2s_set_sysclk,
 453         .set_fmt = rockchip_i2s_set_fmt,
 454         .trigger = rockchip_i2s_trigger,
 455 };
 456
 457 static struct snd_soc_dai_driver rockchip_i2s_dai = {
 458         .probe = rockchip_i2s_dai_probe,
 459         .playback = {
 460                 .stream_name = "Playback",
 461                 .channels_min = 2,
 462                 .channels_max = 8,
 463                 .rates = SNDRV_PCM_RATE_8000_192000,
 464                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 465                             SNDRV_PCM_FMTBIT_S16_LE |
 466                             SNDRV_PCM_FMTBIT_S20_3LE |
 467                             SNDRV_PCM_FMTBIT_S24_LE |
 468                             SNDRV_PCM_FMTBIT_S32_LE),
 469         },
 470         .capture = {
 471                 .stream_name = "Capture",
 472                 .channels_min = 2,
 473                 .channels_max = 2,
 474                 .rates = SNDRV_PCM_RATE_8000_192000,
 475                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 476                             SNDRV_PCM_FMTBIT_S16_LE |
 477                             SNDRV_PCM_FMTBIT_S20_3LE |
 478                             SNDRV_PCM_FMTBIT_S24_LE |
 479                             SNDRV_PCM_FMTBIT_S32_LE),
 480         },
 481         .ops = &rockchip_i2s_dai_ops,
 482         .symmetric_rates = 1,
 483 };
 484
 485 static const struct snd_soc_component_driver rockchip_i2s_component = {
 486         .name = DRV_NAME,
 487 };
 488
 489 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
 490 {
 491         switch (reg) {
 492         case I2S_TXCR:
 493         case I2S_RXCR:
 494         case I2S_CKR:
 495         case I2S_DMACR:
 496         case I2S_INTCR:
 497         case I2S_XFER:
 498         case I2S_CLR:
 499         case I2S_TXDR:
 500                 return true;
 501         default:
 502                 return false;
 503         }
 504 }
 505
 506 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
 507 {
 508         switch (reg) {
 509         case I2S_TXCR:
 510         case I2S_RXCR:
 511         case I2S_CKR:
 512         case I2S_DMACR:
 513         case I2S_INTCR:
 514         case I2S_XFER:
 515         case I2S_CLR:
 516         case I2S_TXDR:
 517         case I2S_RXDR:
 518         case I2S_FIFOLR:
 519         case I2S_INTSR:
 520                 return true;
 521         default:
 522                 return false;
 523         }
 524 }
 525
 526 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
 527 {
 528         switch (reg) {
 529         case I2S_INTSR:
 530         case I2S_CLR:
 531         case I2S_FIFOLR:
 532         case I2S_TXDR:
 533         case I2S_RXDR:
 534                 return true;
 535         default:
 536                 return false;
 537         }
 538 }
 539
 540 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
 541 {
 542         switch (reg) {
 543         case I2S_RXDR:
 544                 return true;
 545         default:
 546                 return false;
 547         }
 548 }
 549
 550 static const struct reg_default rockchip_i2s_reg_defaults[] = {
 551         {0x00, 0x0000000f},
 552         {0x04, 0x0000000f},
 553         {0x08, 0x00071f1f},
 554         {0x10, 0x001f0000},
 555         {0x14, 0x01f00000},
 556 };
 557
 558 static const struct regmap_config rockchip_i2s_regmap_config = {
 559         .reg_bits = 32,
 560         .reg_stride = 4,
 561         .val_bits = 32,
 562         .max_register = I2S_RXDR,
 563         .reg_defaults = rockchip_i2s_reg_defaults,
 564         .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
 565         .writeable_reg = rockchip_i2s_wr_reg,
 566         .readable_reg = rockchip_i2s_rd_reg,
 567         .volatile_reg = rockchip_i2s_volatile_reg,
 568         .precious_reg = rockchip_i2s_precious_reg,
 569         .cache_type = REGCACHE_FLAT,
 570 };
 571
 572 static const struct rk_i2s_pins rk3399_i2s_pins = {
 573         .reg_offset = 0xe220,
 574         .shift = 11,
 575 };
 576
 577 static const struct of_device_id rockchip_i2s_match[] = {
 578         { .compatible = "rockchip,rk3066-i2s", },
 579         { .compatible = "rockchip,rk3188-i2s", },
 580         { .compatible = "rockchip,rk3288-i2s", },
 581         { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
 582         {},
 583 };
 584
 585 static int rockchip_i2s_probe(struct platform_device *pdev)
 586 {
 587         struct device_node *node = pdev->dev.of_node;
 588         const struct of_device_id *of_id;
 589         struct rk_i2s_dev *i2s;
 590         struct snd_soc_dai_driver *soc_dai;
 591         struct resource *res;
 592         void __iomem *regs;
 593         int ret;
 594         int val;
 595
 596         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 597         if (!i2s)
 598                 return -ENOMEM;
 599
 600         i2s->dev = &pdev->dev;
 601
 602         i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
 603         if (!IS_ERR(i2s->grf)) {
 604                 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
 605                 if (!of_id || !of_id->data)
 606                         return -EINVAL;
 607
 608                 i2s->pins = of_id->data;
 609         }
 610
 611         /* try to prepare related clocks */
 612         i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
 613         if (IS_ERR(i2s->hclk)) {
 614                 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
 615                 return PTR_ERR(i2s->hclk);
 616         }
 617         ret = clk_prepare_enable(i2s->hclk);
 618         if (ret) {
 619                 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
 620                 return ret;
 621         }
 622
 623         i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
 624         if (IS_ERR(i2s->mclk)) {
 625                 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
 626                 return PTR_ERR(i2s->mclk);
 627         }
 628
 629         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 630         regs = devm_ioremap_resource(&pdev->dev, res);
 631         if (IS_ERR(regs))
 632                 return PTR_ERR(regs);
 633
 634         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 635                                             &rockchip_i2s_regmap_config);
 636         if (IS_ERR(i2s->regmap)) {
 637                 dev_err(&pdev->dev,
 638                         "Failed to initialise managed register map\n");
 639                 return PTR_ERR(i2s->regmap);
 640         }
 641
 642         i2s->playback_dma_data.addr = res->start + I2S_TXDR;
 643         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 644         i2s->playback_dma_data.maxburst = 4;
 645
 646         i2s->capture_dma_data.addr = res->start + I2S_RXDR;
 647         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 648         i2s->capture_dma_data.maxburst = 4;
 649
 650         dev_set_drvdata(&pdev->dev, i2s);
 651
 652         pm_runtime_enable(&pdev->dev);
 653         if (!pm_runtime_enabled(&pdev->dev)) {
 654                 ret = i2s_runtime_resume(&pdev->dev);
 655                 if (ret)
 656                         goto err_pm_disable;
 657         }
 658
 659         soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai,
 660                                sizeof(*soc_dai), GFP_KERNEL);
 661         if (!soc_dai) {
 662                 ret = -ENOMEM;
 663                 goto err_pm_disable;
 664         }
 665
 666         if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
 667                 if (val >= 2 && val <= 8)
 668                         soc_dai->playback.channels_max = val;
 669         }
 670
 671         if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
 672                 if (val >= 2 && val <= 8)
 673                         soc_dai->capture.channels_max = val;
 674         }
 675
 676         ret = devm_snd_soc_register_component(&pdev->dev,
 677                                               &rockchip_i2s_component,
 678                                               soc_dai, 1);
 679
 680         if (ret) {
 681                 dev_err(&pdev->dev, "Could not register DAI\n");
 682                 goto err_suspend;
 683         }
 684
 685         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 686         if (ret) {
 687                 dev_err(&pdev->dev, "Could not register PCM\n");
 688                 goto err_suspend;
 689         }
 690
 691         return 0;
 692
 693 err_suspend:
 694         if (!pm_runtime_status_suspended(&pdev->dev))
 695                 i2s_runtime_suspend(&pdev->dev);
 696 err_pm_disable:
 697         pm_runtime_disable(&pdev->dev);
 698
 699         return ret;
 700 }
 701
 702 static int rockchip_i2s_remove(struct platform_device *pdev)
 703 {
 704         struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
 705
 706         pm_runtime_disable(&pdev->dev);
 707         if (!pm_runtime_status_suspended(&pdev->dev))
 708                 i2s_runtime_suspend(&pdev->dev);
 709
 710         clk_disable_unprepare(i2s->mclk);
 711         clk_disable_unprepare(i2s->hclk);
 712
 713         return 0;
 714 }
 715
 716 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
 717         SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
 718                            NULL)
 719 };
 720
 721 static struct platform_driver rockchip_i2s_driver = {
 722         .probe = rockchip_i2s_probe,
 723         .remove = rockchip_i2s_remove,
 724         .driver = {
 725                 .name = DRV_NAME,
 726                 .of_match_table = of_match_ptr(rockchip_i2s_match),
 727                 .pm = &rockchip_i2s_pm_ops,
 728         },
 729 };
 730 module_platform_driver(rockchip_i2s_driver);
 731
 732 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
 733 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
 734 MODULE_LICENSE("GPL v2");
 735 MODULE_ALIAS("platform:" DRV_NAME);
 736 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);