1 // SPDX-License-Identifier: GPL-2.0-only
2 /* sound/soc/rockchip/rockchip_i2s.c
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun <jay.xu@rock-chips.com>
10 #include <linux/module.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/delay.h>
13 #include <linux/of_gpio.h>
14 #include <linux/of_device.h>
15 #include <linux/clk.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/spinlock.h>
19 #include <sound/pcm_params.h>
20 #include <sound/dmaengine_pcm.h>
22 #include "rockchip_i2s.h"
23 #include "rockchip_pcm.h"
25 #define DRV_NAME "rockchip-i2s"
38 struct snd_dmaengine_dai_dma_data capture_dma_data;
39 struct snd_dmaengine_dai_dma_data playback_dma_data;
41 struct regmap *regmap;
48 * Used to indicate the tx/rx status.
49 * I2S controller hopes to start the tx and rx together,
50 * also to stop them when they are both try to stop.
55 const struct rk_i2s_pins *pins;
56 unsigned int bclk_ratio;
57 spinlock_t lock; /* tx/rx lock */
60 static int i2s_runtime_suspend(struct device *dev)
62 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
64 regcache_cache_only(i2s->regmap, true);
65 clk_disable_unprepare(i2s->mclk);
70 static int i2s_runtime_resume(struct device *dev)
72 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
75 ret = clk_prepare_enable(i2s->mclk);
77 dev_err(i2s->dev, "clock enable failed %d\n", ret);
81 regcache_cache_only(i2s->regmap, false);
82 regcache_mark_dirty(i2s->regmap);
84 ret = regcache_sync(i2s->regmap);
86 clk_disable_unprepare(i2s->mclk);
91 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
93 return snd_soc_dai_get_drvdata(dai);
96 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
101 spin_lock(&i2s->lock);
103 regmap_update_bits(i2s->regmap, I2S_DMACR,
104 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
106 regmap_update_bits(i2s->regmap, I2S_XFER,
107 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
108 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
110 i2s->tx_start = true;
112 i2s->tx_start = false;
114 regmap_update_bits(i2s->regmap, I2S_DMACR,
115 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
117 if (!i2s->rx_start) {
118 regmap_update_bits(i2s->regmap, I2S_XFER,
125 regmap_update_bits(i2s->regmap, I2S_CLR,
126 I2S_CLR_TXC | I2S_CLR_RXC,
127 I2S_CLR_TXC | I2S_CLR_RXC);
129 regmap_read(i2s->regmap, I2S_CLR, &val);
131 /* Should wait for clear operation to finish */
133 regmap_read(i2s->regmap, I2S_CLR, &val);
136 dev_warn(i2s->dev, "fail to clear\n");
142 spin_unlock(&i2s->lock);
145 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
147 unsigned int val = 0;
150 spin_lock(&i2s->lock);
152 regmap_update_bits(i2s->regmap, I2S_DMACR,
153 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
155 regmap_update_bits(i2s->regmap, I2S_XFER,
156 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
157 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
159 i2s->rx_start = true;
161 i2s->rx_start = false;
163 regmap_update_bits(i2s->regmap, I2S_DMACR,
164 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
166 if (!i2s->tx_start) {
167 regmap_update_bits(i2s->regmap, I2S_XFER,
174 regmap_update_bits(i2s->regmap, I2S_CLR,
175 I2S_CLR_TXC | I2S_CLR_RXC,
176 I2S_CLR_TXC | I2S_CLR_RXC);
178 regmap_read(i2s->regmap, I2S_CLR, &val);
180 /* Should wait for clear operation to finish */
182 regmap_read(i2s->regmap, I2S_CLR, &val);
185 dev_warn(i2s->dev, "fail to clear\n");
191 spin_unlock(&i2s->lock);
194 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
197 struct rk_i2s_dev *i2s = to_info(cpu_dai);
198 unsigned int mask = 0, val = 0;
201 pm_runtime_get_sync(cpu_dai->dev);
202 mask = I2S_CKR_MSS_MASK;
203 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
204 case SND_SOC_DAIFMT_CBS_CFS:
205 /* Set source clock in Master mode */
206 val = I2S_CKR_MSS_MASTER;
207 i2s->is_master_mode = true;
209 case SND_SOC_DAIFMT_CBM_CFM:
210 val = I2S_CKR_MSS_SLAVE;
211 i2s->is_master_mode = false;
218 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
220 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
221 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
222 case SND_SOC_DAIFMT_NB_NF:
223 val = I2S_CKR_CKP_NORMAL |
227 case SND_SOC_DAIFMT_NB_IF:
228 val = I2S_CKR_CKP_NORMAL |
229 I2S_CKR_TLP_INVERTED |
230 I2S_CKR_RLP_INVERTED;
232 case SND_SOC_DAIFMT_IB_NF:
233 val = I2S_CKR_CKP_INVERTED |
237 case SND_SOC_DAIFMT_IB_IF:
238 val = I2S_CKR_CKP_INVERTED |
239 I2S_CKR_TLP_INVERTED |
240 I2S_CKR_RLP_INVERTED;
247 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
249 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
250 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
251 case SND_SOC_DAIFMT_RIGHT_J:
252 val = I2S_TXCR_IBM_RSJM;
254 case SND_SOC_DAIFMT_LEFT_J:
255 val = I2S_TXCR_IBM_LSJM;
257 case SND_SOC_DAIFMT_I2S:
258 val = I2S_TXCR_IBM_NORMAL;
260 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
261 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
263 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
264 val = I2S_TXCR_TFS_PCM;
271 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
273 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
274 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
275 case SND_SOC_DAIFMT_RIGHT_J:
276 val = I2S_RXCR_IBM_RSJM;
278 case SND_SOC_DAIFMT_LEFT_J:
279 val = I2S_RXCR_IBM_LSJM;
281 case SND_SOC_DAIFMT_I2S:
282 val = I2S_RXCR_IBM_NORMAL;
284 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
285 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
287 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
288 val = I2S_RXCR_TFS_PCM;
295 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
298 pm_runtime_put(cpu_dai->dev);
303 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
304 struct snd_pcm_hw_params *params,
305 struct snd_soc_dai *dai)
307 struct rk_i2s_dev *i2s = to_info(dai);
308 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
309 unsigned int val = 0;
310 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
312 if (i2s->is_master_mode) {
313 mclk_rate = clk_get_rate(i2s->mclk);
314 bclk_rate = i2s->bclk_ratio * params_rate(params);
318 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
319 div_lrck = bclk_rate / params_rate(params);
320 regmap_update_bits(i2s->regmap, I2S_CKR,
322 I2S_CKR_MDIV(div_bclk));
324 regmap_update_bits(i2s->regmap, I2S_CKR,
327 I2S_CKR_TSD(div_lrck) |
328 I2S_CKR_RSD(div_lrck));
331 switch (params_format(params)) {
332 case SNDRV_PCM_FORMAT_S8:
333 val |= I2S_TXCR_VDW(8);
335 case SNDRV_PCM_FORMAT_S16_LE:
336 val |= I2S_TXCR_VDW(16);
338 case SNDRV_PCM_FORMAT_S20_3LE:
339 val |= I2S_TXCR_VDW(20);
341 case SNDRV_PCM_FORMAT_S24_LE:
342 val |= I2S_TXCR_VDW(24);
344 case SNDRV_PCM_FORMAT_S32_LE:
345 val |= I2S_TXCR_VDW(32);
351 switch (params_channels(params)) {
365 dev_err(i2s->dev, "invalid channel: %d\n",
366 params_channels(params));
370 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
371 regmap_update_bits(i2s->regmap, I2S_RXCR,
372 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
375 regmap_update_bits(i2s->regmap, I2S_TXCR,
376 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
379 if (!IS_ERR(i2s->grf) && i2s->pins) {
380 regmap_read(i2s->regmap, I2S_TXCR, &val);
381 val &= I2S_TXCR_CSR_MASK;
385 val = I2S_IO_4CH_OUT_6CH_IN;
388 val = I2S_IO_6CH_OUT_4CH_IN;
391 val = I2S_IO_8CH_OUT_2CH_IN;
394 val = I2S_IO_2CH_OUT_8CH_IN;
398 val <<= i2s->pins->shift;
399 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
400 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
403 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
405 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
408 val = I2S_CKR_TRCM_TXRX;
409 if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate)
410 val = I2S_CKR_TRCM_TXONLY;
412 regmap_update_bits(i2s->regmap, I2S_CKR,
418 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
419 int cmd, struct snd_soc_dai *dai)
421 struct rk_i2s_dev *i2s = to_info(dai);
425 case SNDRV_PCM_TRIGGER_START:
426 case SNDRV_PCM_TRIGGER_RESUME:
427 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
428 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
429 rockchip_snd_rxctrl(i2s, 1);
431 rockchip_snd_txctrl(i2s, 1);
433 case SNDRV_PCM_TRIGGER_SUSPEND:
434 case SNDRV_PCM_TRIGGER_STOP:
435 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
436 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
437 rockchip_snd_rxctrl(i2s, 0);
439 rockchip_snd_txctrl(i2s, 0);
449 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
452 struct rk_i2s_dev *i2s = to_info(dai);
454 i2s->bclk_ratio = ratio;
459 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
460 unsigned int freq, int dir)
462 struct rk_i2s_dev *i2s = to_info(cpu_dai);
468 ret = clk_set_rate(i2s->mclk, freq);
470 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
475 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
477 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
479 snd_soc_dai_init_dma_data(dai,
480 i2s->has_playback ? &i2s->playback_dma_data : NULL,
481 i2s->has_capture ? &i2s->capture_dma_data : NULL);
486 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
487 .hw_params = rockchip_i2s_hw_params,
488 .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
489 .set_sysclk = rockchip_i2s_set_sysclk,
490 .set_fmt = rockchip_i2s_set_fmt,
491 .trigger = rockchip_i2s_trigger,
494 static struct snd_soc_dai_driver rockchip_i2s_dai = {
495 .probe = rockchip_i2s_dai_probe,
496 .ops = &rockchip_i2s_dai_ops,
500 static const struct snd_soc_component_driver rockchip_i2s_component = {
504 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
521 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
541 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
555 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
565 static const struct reg_default rockchip_i2s_reg_defaults[] = {
573 static const struct regmap_config rockchip_i2s_regmap_config = {
577 .max_register = I2S_RXDR,
578 .reg_defaults = rockchip_i2s_reg_defaults,
579 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
580 .writeable_reg = rockchip_i2s_wr_reg,
581 .readable_reg = rockchip_i2s_rd_reg,
582 .volatile_reg = rockchip_i2s_volatile_reg,
583 .precious_reg = rockchip_i2s_precious_reg,
584 .cache_type = REGCACHE_FLAT,
587 static const struct rk_i2s_pins rk3399_i2s_pins = {
588 .reg_offset = 0xe220,
592 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
593 { .compatible = "rockchip,px30-i2s", },
594 { .compatible = "rockchip,rk1808-i2s", },
595 { .compatible = "rockchip,rk3036-i2s", },
596 { .compatible = "rockchip,rk3066-i2s", },
597 { .compatible = "rockchip,rk3128-i2s", },
598 { .compatible = "rockchip,rk3188-i2s", },
599 { .compatible = "rockchip,rk3228-i2s", },
600 { .compatible = "rockchip,rk3288-i2s", },
601 { .compatible = "rockchip,rk3308-i2s", },
602 { .compatible = "rockchip,rk3328-i2s", },
603 { .compatible = "rockchip,rk3366-i2s", },
604 { .compatible = "rockchip,rk3368-i2s", },
605 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
606 { .compatible = "rockchip,rv1126-i2s", },
610 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
611 struct snd_soc_dai_driver **dp)
613 struct device_node *node = i2s->dev->of_node;
614 struct snd_soc_dai_driver *dai;
615 struct property *dma_names;
616 const char *dma_name;
619 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
620 if (!strcmp(dma_name, "tx"))
621 i2s->has_playback = true;
622 if (!strcmp(dma_name, "rx"))
623 i2s->has_capture = true;
626 dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
627 sizeof(*dai), GFP_KERNEL);
631 if (i2s->has_playback) {
632 dai->playback.stream_name = "Playback";
633 dai->playback.channels_min = 2;
634 dai->playback.channels_max = 8;
635 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
636 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
637 SNDRV_PCM_FMTBIT_S16_LE |
638 SNDRV_PCM_FMTBIT_S20_3LE |
639 SNDRV_PCM_FMTBIT_S24_LE |
640 SNDRV_PCM_FMTBIT_S32_LE;
642 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
643 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
644 i2s->playback_dma_data.maxburst = 8;
646 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
647 if (val >= 2 && val <= 8)
648 dai->playback.channels_max = val;
652 if (i2s->has_capture) {
653 dai->capture.stream_name = "Capture";
654 dai->capture.channels_min = 2;
655 dai->capture.channels_max = 8;
656 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
657 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
658 SNDRV_PCM_FMTBIT_S16_LE |
659 SNDRV_PCM_FMTBIT_S20_3LE |
660 SNDRV_PCM_FMTBIT_S24_LE |
661 SNDRV_PCM_FMTBIT_S32_LE;
663 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
664 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
665 i2s->capture_dma_data.maxburst = 8;
667 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
668 if (val >= 2 && val <= 8)
669 dai->capture.channels_max = val;
679 static int rockchip_i2s_probe(struct platform_device *pdev)
681 struct device_node *node = pdev->dev.of_node;
682 const struct of_device_id *of_id;
683 struct rk_i2s_dev *i2s;
684 struct snd_soc_dai_driver *dai;
685 struct resource *res;
689 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
693 spin_lock_init(&i2s->lock);
694 i2s->dev = &pdev->dev;
696 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
697 if (!IS_ERR(i2s->grf)) {
698 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
699 if (!of_id || !of_id->data)
702 i2s->pins = of_id->data;
705 /* try to prepare related clocks */
706 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
707 if (IS_ERR(i2s->hclk)) {
708 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
709 return PTR_ERR(i2s->hclk);
711 ret = clk_prepare_enable(i2s->hclk);
713 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
717 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
718 if (IS_ERR(i2s->mclk)) {
719 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
720 ret = PTR_ERR(i2s->mclk);
724 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
730 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
731 &rockchip_i2s_regmap_config);
732 if (IS_ERR(i2s->regmap)) {
734 "Failed to initialise managed register map\n");
735 ret = PTR_ERR(i2s->regmap);
739 i2s->bclk_ratio = 64;
741 dev_set_drvdata(&pdev->dev, i2s);
743 pm_runtime_enable(&pdev->dev);
744 if (!pm_runtime_enabled(&pdev->dev)) {
745 ret = i2s_runtime_resume(&pdev->dev);
750 ret = rockchip_i2s_init_dai(i2s, res, &dai);
754 ret = devm_snd_soc_register_component(&pdev->dev,
755 &rockchip_i2s_component,
759 dev_err(&pdev->dev, "Could not register DAI\n");
763 ret = rockchip_pcm_platform_register(&pdev->dev);
765 dev_err(&pdev->dev, "Could not register PCM\n");
772 if (!pm_runtime_status_suspended(&pdev->dev))
773 i2s_runtime_suspend(&pdev->dev);
775 pm_runtime_disable(&pdev->dev);
777 clk_disable_unprepare(i2s->hclk);
781 static int rockchip_i2s_remove(struct platform_device *pdev)
783 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
785 pm_runtime_disable(&pdev->dev);
786 if (!pm_runtime_status_suspended(&pdev->dev))
787 i2s_runtime_suspend(&pdev->dev);
789 clk_disable_unprepare(i2s->hclk);
794 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
795 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
799 static struct platform_driver rockchip_i2s_driver = {
800 .probe = rockchip_i2s_probe,
801 .remove = rockchip_i2s_remove,
804 .of_match_table = of_match_ptr(rockchip_i2s_match),
805 .pm = &rockchip_i2s_pm_ops,
808 module_platform_driver(rockchip_i2s_driver);
810 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
811 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
812 MODULE_LICENSE("GPL v2");
813 MODULE_ALIAS("platform:" DRV_NAME);
814 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);