1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef __AUDIOREACH_H__
4 #define __AUDIOREACH_H__
5 #include <linux/types.h>
6 #include <linux/soc/qcom/apr.h>
12 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000
13 #define MODULE_ID_RD_SHARED_MEM_EP 0x07001001
14 #define MODULE_ID_GAIN 0x07001002
15 #define MODULE_ID_PCM_CNV 0x07001003
16 #define MODULE_ID_PCM_ENC 0x07001004
17 #define MODULE_ID_PCM_DEC 0x07001005
18 #define MODULE_ID_PLACEHOLDER_ENCODER 0x07001008
19 #define MODULE_ID_PLACEHOLDER_DECODER 0x07001009
20 #define MODULE_ID_SAL 0x07001010
21 #define MODULE_ID_MFC 0x07001015
22 #define MODULE_ID_CODEC_DMA_SINK 0x07001023
23 #define MODULE_ID_CODEC_DMA_SOURCE 0x07001024
24 #define MODULE_ID_I2S_SINK 0x0700100A
25 #define MODULE_ID_I2S_SOURCE 0x0700100B
26 #define MODULE_ID_DATA_LOGGING 0x0700101A
27 #define MODULE_ID_AAC_DEC 0x0700101F
28 #define MODULE_ID_FLAC_DEC 0x0700102F
29 #define MODULE_ID_MP3_DECODE 0x0700103B
30 #define MODULE_ID_GAPLESS 0x0700104D
31 #define MODULE_ID_DISPLAY_PORT_SINK 0x07001069
33 #define APM_CMD_GET_SPF_STATE 0x01001021
34 #define APM_CMD_RSP_GET_SPF_STATE 0x02001007
36 #define APM_MODULE_INSTANCE_ID 0x00000001
37 #define PRM_MODULE_INSTANCE_ID 0x00000002
38 #define AMDB_MODULE_INSTANCE_ID 0x00000003
39 #define VCPM_MODULE_INSTANCE_ID 0x00000004
40 #define AR_MODULE_INSTANCE_ID_START 0x00006000
41 #define AR_MODULE_INSTANCE_ID_END 0x00007000
42 #define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000
43 #define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000
44 #define AR_CONT_INSTANCE_ID_START 0x00005000
45 #define AR_CONT_INSTANCE_ID_END 0x00006000
46 #define AR_SG_INSTANCE_ID_START 0x00004000
48 #define APM_CMD_GRAPH_OPEN 0x01001000
49 #define APM_CMD_GRAPH_PREPARE 0x01001001
50 #define APM_CMD_GRAPH_START 0x01001002
51 #define APM_CMD_GRAPH_STOP 0x01001003
52 #define APM_CMD_GRAPH_CLOSE 0x01001004
53 #define APM_CMD_GRAPH_FLUSH 0x01001005
54 #define APM_CMD_SET_CFG 0x01001006
55 #define APM_CMD_GET_CFG 0x01001007
56 #define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C
57 #define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D
58 #define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001
59 #define APM_CMD_RSP_GET_CFG 0x02001000
60 #define APM_CMD_CLOSE_ALL 0x01001013
61 #define APM_CMD_REGISTER_SHARED_CFG 0x0100100A
63 #define APM_MEMORY_MAP_SHMEM8_4K_POOL 3
65 struct apm_cmd_shared_mem_map_regions {
68 uint32_t property_flag;
71 struct apm_shared_map_region_payload {
72 uint32_t shm_addr_lsw;
73 uint32_t shm_addr_msw;
74 uint32_t mem_size_bytes;
77 struct apm_cmd_shared_mem_unmap_regions {
78 uint32_t mem_map_handle;
81 struct apm_cmd_rsp_shared_mem_map_regions {
82 uint32_t mem_map_handle;
86 #define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005
88 #define APM_PARAM_ID_MODULE_LIST 0x08001002
90 struct apm_param_id_modules_list {
91 uint32_t num_modules_list;
94 #define APM_PARAM_ID_MODULE_PROP 0x08001003
96 struct apm_param_id_module_prop {
97 uint32_t num_modules_prop_cfg;
100 struct apm_module_prop_cfg {
101 uint32_t instance_id;
105 #define APM_PARAM_ID_MODULE_CONN 0x08001004
107 struct apm_param_id_module_conn {
108 uint32_t num_connections;
111 struct apm_module_conn_obj {
112 uint32_t src_mod_inst_id;
113 uint32_t src_mod_op_port_id;
114 uint32_t dst_mod_inst_id;
115 uint32_t dst_mod_ip_port_id;
118 #define APM_PARAM_ID_GAIN 0x08001006
120 struct param_id_gain_cfg {
125 #define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008
127 struct param_id_pcm_output_format_cfg {
128 uint32_t data_format;
130 uint32_t payload_size;
133 struct payload_pcm_output_format_cfg {
136 uint16_t bits_per_sample;
139 uint16_t interleaved;
141 uint16_t num_channels;
142 uint8_t channel_mapping[];
145 #define PARAM_ID_ENC_BITRATE 0x08001052
147 struct param_id_enc_bitrate_param {
151 #define DATA_FORMAT_FIXED_POINT 1
152 #define DATA_FORMAT_GENERIC_COMPRESSED 5
153 #define DATA_FORMAT_RAW_COMPRESSED 6
154 #define PCM_LSB_ALIGNED 1
155 #define PCM_MSB_ALIGNED 2
156 #define PCM_LITTLE_ENDIAN 1
157 #define PCM_BIT_ENDIAN 2
159 #define MEDIA_FMT_ID_PCM 0x09001000
160 #define MEDIA_FMT_ID_MP3 0x09001009
161 #define PCM_CHANNEL_L 1
162 #define PCM_CHANNEL_R 2
163 #define SAMPLE_RATE_48K 48000
164 #define BIT_WIDTH_16 16
166 #define APM_PARAM_ID_PROP_PORT_INFO 0x08001015
168 struct apm_modules_prop_info {
169 uint32_t max_ip_port;
170 uint32_t max_op_port;
173 /* Shared memory module */
174 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000
175 #define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31)
176 #define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30)
177 #define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29)
178 #define WR_SH_MEM_EP_EOF_FLAG BIT(4)
180 struct apm_data_cmd_wr_sh_mem_ep_data_buffer {
181 uint32_t buf_addr_lsw;
182 uint32_t buf_addr_msw;
183 uint32_t mem_map_handle;
185 uint32_t timestamp_lsw;
186 uint32_t timestamp_msw;
190 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A
192 struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 {
193 uint32_t buf_addr_lsw;
194 uint32_t buf_addr_msw;
195 uint32_t mem_map_handle;
197 uint32_t timestamp_lsw;
198 uint32_t timestamp_msw;
200 uint32_t md_addr_lsw;
201 uint32_t md_addr_msw;
202 uint32_t md_map_handle;
203 uint32_t md_buf_size;
206 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000
208 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done {
209 uint32_t buf_addr_lsw;
210 uint32_t buf_addr_msw;
211 uint32_t mem_map_handle;
216 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004
218 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 {
219 uint32_t buf_addr_lsw;
220 uint32_t buf_addr_msw;
221 uint32_t mem_map_handle;
223 uint32_t md_buf_addr_lsw;
224 uint32_t md_buf_addr_msw;
225 uint32_t md_mem_map_handle;
229 #define PARAM_ID_MEDIA_FORMAT 0x0800100C
230 #define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001
232 struct apm_media_format {
233 uint32_t data_format;
235 uint32_t payload_size;
238 #define MEDIA_FMT_ID_FLAC 0x09001004
240 struct payload_media_fmt_flac_t {
241 uint16_t num_channels;
242 uint16_t sample_size;
243 uint16_t min_blk_size;
244 uint16_t max_blk_size;
245 uint32_t sample_rate;
246 uint32_t min_frame_size;
247 uint32_t max_frame_size;
250 #define MEDIA_FMT_ID_AAC 0x09001001
252 struct payload_media_fmt_aac_t {
253 uint16_t aac_fmt_flag;
254 uint16_t audio_obj_type;
255 uint16_t num_channels;
256 uint16_t total_size_of_PCE_bits;
257 uint32_t sample_rate;
260 #define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002
261 #define WR_SH_MEM_EP_EOS_POLICY_LAST 1
262 #define WR_SH_MEM_EP_EOS_POLICY_EACH 2
264 struct data_cmd_wr_sh_mem_ep_eos {
269 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003
271 struct data_cmd_rd_sh_mem_ep_data_buffer {
272 uint32_t buf_addr_lsw;
273 uint32_t buf_addr_msw;
274 uint32_t mem_map_handle;
278 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002
280 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done {
282 uint32_t buf_addr_lsw;
283 uint32_t buf_addr_msw;
284 uint32_t mem_map_handle;
287 uint32_t timestamp_lsw;
288 uint32_t timestamp_msw;
293 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B
295 struct data_cmd_rd_sh_mem_ep_data_buffer_v2 {
296 uint32_t buf_addr_lsw;
297 uint32_t buf_addr_msw;
298 uint32_t mem_map_handle;
300 uint32_t md_buf_addr_lsw;
301 uint32_t md_buf_addr_msw;
302 uint32_t md_mem_map_handle;
303 uint32_t md_buf_size;
306 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005
308 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 {
310 uint32_t buf_addr_lsw;
311 uint32_t buf_addr_msw;
312 uint32_t mem_map_handle;
315 uint32_t timestamp_lsw;
316 uint32_t timestamp_msw;
320 uint32_t md_buf_addr_lsw;
321 uint32_t md_buf_addr_msw;
322 uint32_t md_mem_map_handle;
326 #define PARAM_ID_RD_SH_MEM_CFG 0x08001007
328 struct param_id_rd_sh_mem_cfg {
329 uint32_t num_frames_per_buffer;
330 uint32_t metadata_control_flags;
334 #define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001
336 struct data_cmd_wr_sh_mem_ep_eos_rendered {
337 uint32_t module_instance_id;
338 uint32_t render_status;
341 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000
343 struct apm_cmd_header {
344 uint32_t payload_address_lsw;
345 uint32_t payload_address_msw;
346 uint32_t mem_map_handle;
347 uint32_t payload_size;
350 #define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header)
352 struct apm_module_param_data {
353 uint32_t module_instance_id;
359 #define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data)
361 struct apm_module_param_shared_data {
366 struct apm_prop_data {
371 /* Sub-Graph Properties */
372 #define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001
374 struct apm_param_id_sub_graph_cfg {
375 uint32_t num_sub_graphs;
378 struct apm_sub_graph_cfg {
379 uint32_t sub_graph_id;
380 uint32_t num_sub_graph_prop;
383 #define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E
385 struct apm_sg_prop_id_perf_mode {
389 #define APM_SG_PROP_ID_PERF_MODE_SIZE 4
391 #define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F
393 struct apm_sg_prop_id_direction {
397 #define APM_SG_PROP_ID_DIR_SIZE 4
399 #define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010
400 #define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1
401 #define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2
402 #define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3
404 struct apm_sg_prop_id_scenario_id {
405 uint32_t scenario_id;
408 #define APM_SG_PROP_ID_SID_SIZE 4
410 #define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000
412 struct apm_param_id_container_cfg {
413 uint32_t num_containers;
416 struct apm_container_cfg {
417 uint32_t container_id;
421 struct apm_cont_capability {
422 uint32_t capability_id;
425 #define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011
426 #define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8
428 #define APM_PROP_ID_INVALID 0x0
429 #define APM_CONTAINER_CAP_ID_PP 0x1
430 #define APM_CONTAINER_CAP_ID_PP 0x1
432 struct apm_cont_prop_id_cap_list {
433 uint32_t num_capability_id;
436 #define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012
438 struct apm_cont_prop_id_graph_pos {
442 #define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013
444 struct apm_cont_prop_id_stack_size {
448 #define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014
450 struct apm_cont_prop_id_domain {
451 uint32_t proc_domain;
454 #define CONFIG_I2S_WS_SRC_EXTERNAL 0x0
455 #define CONFIG_I2S_WS_SRC_INTERNAL 0x1
457 #define PARAM_ID_I2S_INTF_CFG 0x08001019
458 struct param_id_i2s_intf_cfg {
461 uint16_t sd_line_idx;
465 #define I2S_INTF_TYPE_PRIMARY 0
466 #define I2S_INTF_TYPE_SECOINDARY 1
467 #define I2S_INTF_TYPE_TERTINARY 2
468 #define I2S_INTF_TYPE_QUATERNARY 3
469 #define I2S_INTF_TYPE_QUINARY 4
475 #define PORT_ID_I2S_INPUT 2
476 #define PORT_ID_I2S_OUPUT 1
477 #define I2S_STACK_SIZE 2048
479 #define PARAM_ID_DISPLAY_PORT_INTF_CFG 0x08001154
481 struct param_id_display_port_intf_cfg {
482 uint32_t channel_allocation;
483 /* Multi-Steam Transport index */
488 #define PARAM_ID_HW_EP_MF_CFG 0x08001017
489 struct param_id_hw_ep_mf {
490 uint32_t sample_rate;
492 uint16_t num_channels;
493 uint32_t data_format;
496 #define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018
498 struct param_id_fram_size_factor {
499 uint32_t frame_size_factor;
502 #define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB
504 struct apm_cont_prop_id_parent_container {
505 uint32_t parent_container_id;
508 #define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174
509 #define APM_CONT_HEAP_DEFAULT 0x1
510 #define APM_CONT_HEAP_LOW_POWER 0x2
512 struct apm_cont_prop_id_headp_id {
516 struct apm_modules_list {
517 uint32_t sub_graph_id;
518 uint32_t container_id;
519 uint32_t num_modules;
522 struct apm_module_obj {
524 uint32_t instance_id;
527 #define APM_MODULE_PROP_ID_PORT_INFO 0x08001015
528 #define APM_MODULE_PROP_ID_PORT_INFO_SZ 8
529 struct apm_module_prop_id_port_info {
530 uint32_t max_ip_port;
531 uint32_t max_op_port;
534 #define DATA_LOGGING_MAX_INPUT_PORTS 0x1
535 #define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1
536 #define DATA_LOGGING_STACK_SIZE 2048
537 #define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031
539 struct data_logging_config {
541 uint32_t log_tap_point_id;
545 #define PARAM_ID_SAL_OUTPUT_CFG 0x08001016
546 struct param_id_sal_output_config {
547 uint32_t bits_per_sample;
550 #define PARAM_ID_SAL_LIMITER_ENABLE 0x0800101E
551 struct param_id_sal_limiter_enable {
555 #define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024
556 #define PARAM_ID_EARLY_EOS_DELAY 0x0800114C
557 #define EARLY_EOS_DELAY_MS 150
559 struct param_id_mfc_media_format {
560 uint32_t sample_rate;
562 uint16_t num_channels;
563 uint16_t channel_mapping[];
566 struct param_id_gapless_early_eos_delay_t {
567 uint32_t early_eos_delay_ms;
570 struct media_format {
571 uint32_t data_format;
573 uint32_t payload_size;
576 struct payload_media_fmt_pcm {
577 uint32_t sample_rate;
580 uint16_t bits_per_sample;
583 uint16_t num_channels;
584 uint8_t channel_mapping[];
587 #define PARAM_ID_MODULE_ENABLE 0x08001026
588 struct param_id_module_enable {
592 #define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063
594 struct param_id_codec_dma_intf_cfg {
604 * RX2 | TX2 = 3... so on
607 uint32_t active_channels_mask;
610 struct audio_hw_clk_cfg {
613 uint32_t clock_attri;
617 struct audio_hw_clk_rel_cfg {
621 #define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176
622 #define AR_HW_EP_POWER_MODE_0 0 /* default */
623 #define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */
624 #define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */
626 struct param_id_hw_ep_power_mode_cfg {
630 #define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233
631 #define AR_HW_EP_DMA_DATA_ALIGN_MSB 0
632 #define AR_HW_EP_DMA_DATA_ALIGN_LSB 1
633 #define AR_PCM_MAX_NUM_CHANNEL 8
635 struct param_id_hw_ep_dma_data_align {
636 uint32_t dma_data_align;
639 #define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035
640 #define VOL_CTRL_DEFAULT_GAIN 0x2000
642 struct param_id_vol_ctrl_master_gain {
643 uint16_t master_gain;
648 #define PARAM_ID_REMOVE_INITIAL_SILENCE 0x0800114B
649 #define PARAM_ID_REMOVE_TRAILING_SILENCE 0x0800115D
651 #define PARAM_ID_REAL_MODULE_ID 0x0800100B
653 struct param_id_placeholder_real_module_id {
654 uint32_t real_module_id;
658 struct audioreach_connection {
660 uint32_t src_mod_inst_id;
661 uint32_t src_mod_op_port_id;
662 uint32_t dst_mod_inst_id;
663 uint32_t dst_mod_ip_port_id;
664 struct list_head node;
667 struct audioreach_graph_info {
669 uint32_t num_sub_graphs;
670 struct list_head sg_list;
671 /* DPCM connection from FE Graph to BE graph */
672 uint32_t src_mod_inst_id;
673 uint32_t src_mod_op_port_id;
674 uint32_t dst_mod_inst_id;
675 uint32_t dst_mod_ip_port_id;
678 struct audioreach_sub_graph {
679 uint32_t sub_graph_id;
682 uint32_t scenario_id;
683 struct list_head node;
685 struct audioreach_graph_info *info;
686 uint32_t num_containers;
687 struct list_head container_list;
690 struct audioreach_container {
691 uint32_t container_id;
692 uint32_t capability_id;
695 uint32_t proc_domain;
696 struct list_head node;
698 uint32_t num_modules;
699 struct list_head modules_list;
700 struct audioreach_sub_graph *sub_graph;
703 #define AR_MAX_MOD_LINKS 8
705 struct audioreach_module {
707 uint32_t instance_id;
709 uint32_t max_ip_port;
710 uint32_t max_op_port;
715 uint32_t num_connections;
717 uint32_t src_mod_inst_id;
718 uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS];
719 uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS];
720 uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS];
722 /* Format specifics */
728 uint32_t hw_interface_idx;
729 uint32_t sd_line_idx;
731 uint32_t frame_size_factor;
732 uint32_t data_format;
733 uint32_t hw_interface_type;
735 /* PCM module specific */
736 uint32_t interleave_type;
738 /* GAIN/Vol Control Module */
743 uint32_t log_tap_point_id;
747 struct list_head node;
748 struct audioreach_container *container;
749 struct snd_soc_dapm_widget *widget;
752 struct audioreach_module_config {
760 u16 active_channels_mask;
762 u32 channel_allocation;
765 struct snd_codec codec;
766 u8 channel_map[AR_PCM_MAX_NUM_CHANNEL];
769 /* Packet Allocation routines */
770 void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t
772 void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode,
773 uint32_t token, uint32_t src_port,
775 void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token,
777 void *audioreach_alloc_pkt(int payload_size, uint32_t opcode,
778 uint32_t token, uint32_t src_port,
780 void *audioreach_alloc_graph_pkt(struct q6apm *apm, struct audioreach_graph_info
782 /* Topology specific */
783 int audioreach_tplg_init(struct snd_soc_component *component);
785 /* Module specific */
786 void audioreach_graph_free_buf(struct q6apm_graph *graph);
787 int audioreach_map_memory_regions(struct q6apm_graph *graph,
788 unsigned int dir, size_t period_sz,
789 unsigned int periods,
791 int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result,
792 struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait,
793 struct gpr_pkt *pkt, uint32_t rsp_opcode);
794 int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt,
795 uint32_t rsp_opcode);
796 int audioreach_set_media_format(struct q6apm_graph *graph,
797 struct audioreach_module *module,
798 struct audioreach_module_config *cfg);
799 int audioreach_shared_memory_send_eos(struct q6apm_graph *graph);
800 int audioreach_gain_set_vol_ctrl(struct q6apm *apm,
801 struct audioreach_module *module, int vol);
802 int audioreach_send_u32_param(struct q6apm_graph *graph, struct audioreach_module *module,
803 uint32_t param_id, uint32_t param_val);
804 int audioreach_compr_set_param(struct q6apm_graph *graph, struct audioreach_module_config *mcfg);
806 #endif /* __AUDIOREACH_H__ */