2 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
16 #include <linux/dma-mapping.h>
17 #include <linux/export.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <sound/pcm_params.h>
22 #include <linux/regmap.h>
23 #include <sound/soc.h>
24 #include "lpass-lpaif-reg.h"
27 #define DRV_NAME "lpass-platform"
29 struct lpass_pcm_data {
34 #define LPASS_PLATFORM_BUFFER_SIZE (16 * 1024)
35 #define LPASS_PLATFORM_PERIODS 2
37 static const struct snd_pcm_hardware lpass_platform_pcm_hardware = {
38 .info = SNDRV_PCM_INFO_MMAP |
39 SNDRV_PCM_INFO_MMAP_VALID |
40 SNDRV_PCM_INFO_INTERLEAVED |
41 SNDRV_PCM_INFO_PAUSE |
42 SNDRV_PCM_INFO_RESUME,
43 .formats = SNDRV_PCM_FMTBIT_S16 |
44 SNDRV_PCM_FMTBIT_S24 |
46 .rates = SNDRV_PCM_RATE_8000_192000,
51 .buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
52 .period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
53 LPASS_PLATFORM_PERIODS,
54 .period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
55 LPASS_PLATFORM_PERIODS,
56 .periods_min = LPASS_PLATFORM_PERIODS,
57 .periods_max = LPASS_PLATFORM_PERIODS,
61 static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
63 struct snd_pcm_runtime *runtime = substream->runtime;
64 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
65 struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai;
66 struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
67 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
68 struct lpass_variant *v = drvdata->variant;
69 int ret, dma_ch, dir = substream->stream;
70 struct lpass_pcm_data *data;
72 data = kzalloc(sizeof(*data), GFP_KERNEL);
76 data->i2s_port = cpu_dai->driver->id;
77 runtime->private_data = data;
79 if (v->alloc_dma_channel)
80 dma_ch = v->alloc_dma_channel(drvdata, dir);
89 drvdata->substream[dma_ch] = substream;
91 ret = regmap_write(drvdata->lpaif_map,
92 LPAIF_DMACTL_REG(v, dma_ch, dir), 0);
94 dev_err(soc_runtime->dev,
95 "error writing to rdmactl reg: %d\n", ret);
99 data->dma_ch = dma_ch;
101 snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
103 runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
105 ret = snd_pcm_hw_constraint_integer(runtime,
106 SNDRV_PCM_HW_PARAM_PERIODS);
109 dev_err(soc_runtime->dev, "setting constraints failed: %d\n",
114 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
119 static int lpass_platform_pcmops_close(struct snd_pcm_substream *substream)
121 struct snd_pcm_runtime *runtime = substream->runtime;
122 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
123 struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
124 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
125 struct lpass_variant *v = drvdata->variant;
126 struct lpass_pcm_data *data;
128 data = runtime->private_data;
129 drvdata->substream[data->dma_ch] = NULL;
130 if (v->free_dma_channel)
131 v->free_dma_channel(drvdata, data->dma_ch);
137 static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
138 struct snd_pcm_hw_params *params)
140 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
141 struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
142 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
143 struct snd_pcm_runtime *rt = substream->runtime;
144 struct lpass_pcm_data *pcm_data = rt->private_data;
145 struct lpass_variant *v = drvdata->variant;
146 snd_pcm_format_t format = params_format(params);
147 unsigned int channels = params_channels(params);
149 int ch, dir = substream->stream;
151 int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
153 ch = pcm_data->dma_ch;
155 bitwidth = snd_pcm_format_width(format);
157 dev_err(soc_runtime->dev, "invalid bit width given: %d\n",
162 regval = LPAIF_DMACTL_BURSTEN_INCR4 |
163 LPAIF_DMACTL_AUDINTF(dma_port) |
164 LPAIF_DMACTL_FIFOWM_8;
171 regval |= LPAIF_DMACTL_WPSCNT_ONE;
174 regval |= LPAIF_DMACTL_WPSCNT_TWO;
177 regval |= LPAIF_DMACTL_WPSCNT_THREE;
180 regval |= LPAIF_DMACTL_WPSCNT_FOUR;
183 dev_err(soc_runtime->dev,
184 "invalid PCM config given: bw=%d, ch=%u\n",
193 regval |= LPAIF_DMACTL_WPSCNT_ONE;
196 regval |= LPAIF_DMACTL_WPSCNT_TWO;
199 regval |= LPAIF_DMACTL_WPSCNT_FOUR;
202 regval |= LPAIF_DMACTL_WPSCNT_SIX;
205 regval |= LPAIF_DMACTL_WPSCNT_EIGHT;
208 dev_err(soc_runtime->dev,
209 "invalid PCM config given: bw=%d, ch=%u\n",
215 dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
220 ret = regmap_write(drvdata->lpaif_map,
221 LPAIF_DMACTL_REG(v, ch, dir), regval);
223 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
231 static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
233 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
234 struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
235 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
236 struct snd_pcm_runtime *rt = substream->runtime;
237 struct lpass_pcm_data *pcm_data = rt->private_data;
238 struct lpass_variant *v = drvdata->variant;
242 reg = LPAIF_DMACTL_REG(v, pcm_data->dma_ch, substream->stream);
243 ret = regmap_write(drvdata->lpaif_map, reg, 0);
245 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
251 static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
253 struct snd_pcm_runtime *runtime = substream->runtime;
254 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
255 struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
256 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
257 struct snd_pcm_runtime *rt = substream->runtime;
258 struct lpass_pcm_data *pcm_data = rt->private_data;
259 struct lpass_variant *v = drvdata->variant;
260 int ret, ch, dir = substream->stream;
262 ch = pcm_data->dma_ch;
264 ret = regmap_write(drvdata->lpaif_map,
265 LPAIF_DMABASE_REG(v, ch, dir),
268 dev_err(soc_runtime->dev, "error writing to rdmabase reg: %d\n",
273 ret = regmap_write(drvdata->lpaif_map,
274 LPAIF_DMABUFF_REG(v, ch, dir),
275 (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
277 dev_err(soc_runtime->dev, "error writing to rdmabuff reg: %d\n",
282 ret = regmap_write(drvdata->lpaif_map,
283 LPAIF_DMAPER_REG(v, ch, dir),
284 (snd_pcm_lib_period_bytes(substream) >> 2) - 1);
286 dev_err(soc_runtime->dev, "error writing to rdmaper reg: %d\n",
291 ret = regmap_update_bits(drvdata->lpaif_map,
292 LPAIF_DMACTL_REG(v, ch, dir),
293 LPAIF_DMACTL_ENABLE_MASK, LPAIF_DMACTL_ENABLE_ON);
295 dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
303 static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
306 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
307 struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
308 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
309 struct snd_pcm_runtime *rt = substream->runtime;
310 struct lpass_pcm_data *pcm_data = rt->private_data;
311 struct lpass_variant *v = drvdata->variant;
312 int ret, ch, dir = substream->stream;
314 ch = pcm_data->dma_ch;
317 case SNDRV_PCM_TRIGGER_START:
318 case SNDRV_PCM_TRIGGER_RESUME:
319 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
320 /* clear status before enabling interrupts */
321 ret = regmap_write(drvdata->lpaif_map,
322 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
325 dev_err(soc_runtime->dev,
326 "error writing to irqclear reg: %d\n", ret);
330 ret = regmap_update_bits(drvdata->lpaif_map,
331 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
335 dev_err(soc_runtime->dev,
336 "error writing to irqen reg: %d\n", ret);
340 ret = regmap_update_bits(drvdata->lpaif_map,
341 LPAIF_DMACTL_REG(v, ch, dir),
342 LPAIF_DMACTL_ENABLE_MASK,
343 LPAIF_DMACTL_ENABLE_ON);
345 dev_err(soc_runtime->dev,
346 "error writing to rdmactl reg: %d\n", ret);
350 case SNDRV_PCM_TRIGGER_STOP:
351 case SNDRV_PCM_TRIGGER_SUSPEND:
352 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
353 ret = regmap_update_bits(drvdata->lpaif_map,
354 LPAIF_DMACTL_REG(v, ch, dir),
355 LPAIF_DMACTL_ENABLE_MASK,
356 LPAIF_DMACTL_ENABLE_OFF);
358 dev_err(soc_runtime->dev,
359 "error writing to rdmactl reg: %d\n", ret);
363 ret = regmap_update_bits(drvdata->lpaif_map,
364 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST),
365 LPAIF_IRQ_ALL(ch), 0);
367 dev_err(soc_runtime->dev,
368 "error writing to irqen reg: %d\n", ret);
377 static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
378 struct snd_pcm_substream *substream)
380 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
381 struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
382 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
383 struct snd_pcm_runtime *rt = substream->runtime;
384 struct lpass_pcm_data *pcm_data = rt->private_data;
385 struct lpass_variant *v = drvdata->variant;
386 unsigned int base_addr, curr_addr;
387 int ret, ch, dir = substream->stream;
389 ch = pcm_data->dma_ch;
391 ret = regmap_read(drvdata->lpaif_map,
392 LPAIF_DMABASE_REG(v, ch, dir), &base_addr);
394 dev_err(soc_runtime->dev,
395 "error reading from rdmabase reg: %d\n", ret);
399 ret = regmap_read(drvdata->lpaif_map,
400 LPAIF_DMACURR_REG(v, ch, dir), &curr_addr);
402 dev_err(soc_runtime->dev,
403 "error reading from rdmacurr reg: %d\n", ret);
407 return bytes_to_frames(substream->runtime, curr_addr - base_addr);
410 static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
411 struct vm_area_struct *vma)
413 struct snd_pcm_runtime *runtime = substream->runtime;
415 return dma_mmap_coherent(substream->pcm->card->dev, vma,
416 runtime->dma_area, runtime->dma_addr,
420 static const struct snd_pcm_ops lpass_platform_pcm_ops = {
421 .open = lpass_platform_pcmops_open,
422 .close = lpass_platform_pcmops_close,
423 .ioctl = snd_pcm_lib_ioctl,
424 .hw_params = lpass_platform_pcmops_hw_params,
425 .hw_free = lpass_platform_pcmops_hw_free,
426 .prepare = lpass_platform_pcmops_prepare,
427 .trigger = lpass_platform_pcmops_trigger,
428 .pointer = lpass_platform_pcmops_pointer,
429 .mmap = lpass_platform_pcmops_mmap,
432 static irqreturn_t lpass_dma_interrupt_handler(
433 struct snd_pcm_substream *substream,
434 struct lpass_data *drvdata,
435 int chan, u32 interrupts)
437 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
438 struct lpass_variant *v = drvdata->variant;
439 irqreturn_t ret = IRQ_NONE;
442 if (interrupts & LPAIF_IRQ_PER(chan)) {
443 rv = regmap_write(drvdata->lpaif_map,
444 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
445 LPAIF_IRQ_PER(chan));
447 dev_err(soc_runtime->dev,
448 "error writing to irqclear reg: %d\n", rv);
451 snd_pcm_period_elapsed(substream);
455 if (interrupts & LPAIF_IRQ_XRUN(chan)) {
456 rv = regmap_write(drvdata->lpaif_map,
457 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
458 LPAIF_IRQ_XRUN(chan));
460 dev_err(soc_runtime->dev,
461 "error writing to irqclear reg: %d\n", rv);
464 dev_warn(soc_runtime->dev, "xrun warning\n");
465 snd_pcm_stop_xrun(substream);
469 if (interrupts & LPAIF_IRQ_ERR(chan)) {
470 rv = regmap_write(drvdata->lpaif_map,
471 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST),
472 LPAIF_IRQ_ERR(chan));
474 dev_err(soc_runtime->dev,
475 "error writing to irqclear reg: %d\n", rv);
478 dev_err(soc_runtime->dev, "bus access error\n");
479 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
486 static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
488 struct lpass_data *drvdata = data;
489 struct lpass_variant *v = drvdata->variant;
493 rv = regmap_read(drvdata->lpaif_map,
494 LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
496 pr_err("error reading from irqstat reg: %d\n", rv);
500 /* Handle per channel interrupts */
501 for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
502 if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
503 rv = lpass_dma_interrupt_handler(
504 drvdata->substream[chan],
505 drvdata, chan, irqs);
506 if (rv != IRQ_HANDLED)
514 static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
516 struct snd_pcm *pcm = soc_runtime->pcm;
517 struct snd_pcm_substream *psubstream, *csubstream;
518 struct snd_soc_component *component = snd_soc_rtdcom_lookup(soc_runtime, DRV_NAME);
520 size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
522 psubstream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
524 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
526 size, &psubstream->dma_buffer);
528 dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");
533 csubstream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
535 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
537 size, &csubstream->dma_buffer);
539 dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n");
541 snd_dma_free_pages(&psubstream->dma_buffer);
550 static void lpass_platform_pcm_free(struct snd_pcm *pcm)
552 struct snd_pcm_substream *substream;
555 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
556 substream = pcm->streams[i].substream;
558 snd_dma_free_pages(&substream->dma_buffer);
559 substream->dma_buffer.area = NULL;
560 substream->dma_buffer.addr = 0;
565 static const struct snd_soc_component_driver lpass_component_driver = {
567 .pcm_new = lpass_platform_pcm_new,
568 .pcm_free = lpass_platform_pcm_free,
569 .ops = &lpass_platform_pcm_ops,
572 int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
574 struct lpass_data *drvdata = platform_get_drvdata(pdev);
575 struct lpass_variant *v = drvdata->variant;
578 drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
579 if (drvdata->lpaif_irq < 0) {
580 dev_err(&pdev->dev, "error getting irq handle: %d\n",
585 /* ensure audio hardware is disabled */
586 ret = regmap_write(drvdata->lpaif_map,
587 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
589 dev_err(&pdev->dev, "error writing to irqen reg: %d\n", ret);
593 ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
594 lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
595 "lpass-irq-lpaif", drvdata);
597 dev_err(&pdev->dev, "irq request failed: %d\n", ret);
602 return devm_snd_soc_register_component(&pdev->dev,
603 &lpass_component_driver, NULL, 0);
605 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
607 MODULE_DESCRIPTION("QTi LPASS Platform Driver");
608 MODULE_LICENSE("GPL v2");