sound/soc/qcom/lpass-cpu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
   4  *
   5  * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <sound/pcm.h>
  15 #include <sound/pcm_params.h>
  16 #include <linux/regmap.h>
  17 #include <sound/soc.h>
  18 #include <sound/soc-dai.h>
  19 #include "lpass-lpaif-reg.h"
  20 #include "lpass.h"
  21
  22 #define LPASS_CPU_MAX_MI2S_LINES        4
  23 #define LPASS_CPU_I2S_SD0_MASK          BIT(0)
  24 #define LPASS_CPU_I2S_SD1_MASK          BIT(1)
  25 #define LPASS_CPU_I2S_SD2_MASK          BIT(2)
  26 #define LPASS_CPU_I2S_SD3_MASK          BIT(3)
  27 #define LPASS_CPU_I2S_SD0_1_MASK        GENMASK(1, 0)
  28 #define LPASS_CPU_I2S_SD2_3_MASK        GENMASK(3, 2)
  29 #define LPASS_CPU_I2S_SD0_1_2_MASK      GENMASK(2, 0)
  30 #define LPASS_CPU_I2S_SD0_1_2_3_MASK    GENMASK(3, 0)
  31 #define LPASS_REG_READ 1
  32 #define LPASS_REG_WRITE 0
  33
  34 /*
  35  * Channel maps for Quad channel playbacks on MI2S Secondary
  36  */
  37 static struct snd_pcm_chmap_elem lpass_quad_chmaps[] = {
  38                 { .channels = 4,
  39                   .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_RL,
  40                                 SNDRV_CHMAP_FR, SNDRV_CHMAP_RR } },
  41                 { }
  42 };
  43 static int lpass_cpu_init_i2sctl_bitfields(struct device *dev,
  44                         struct lpaif_i2sctl *i2sctl, struct regmap *map)
  45 {
  46         struct lpass_data *drvdata = dev_get_drvdata(dev);
  47         struct lpass_variant *v = drvdata->variant;
  48
  49         i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback);
  50         i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken);
  51         i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode);
  52         i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono);
  53         i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen);
  54         i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode);
  55         i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono);
  56         i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc);
  57         i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth);
  58
  59         if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) ||
  60             IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) ||
  61             IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) ||
  62             IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) ||
  63             IS_ERR(i2sctl->bitwidth))
  64                 return -EINVAL;
  65
  66         return 0;
  67 }
  68
  69 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  70                 unsigned int freq, int dir)
  71 {
  72         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  73         int ret;
  74
  75         ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
  76         if (ret)
  77                 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
  78                         freq, ret);
  79
  80         return ret;
  81 }
  82
  83 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
  84                 struct snd_soc_dai *dai)
  85 {
  86         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  87         int ret;
  88
  89         ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
  90         if (ret) {
  91                 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
  92                 return ret;
  93         }
  94         ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
  95         if (ret) {
  96                 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
  97                 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
  98                 return ret;
  99         }
 100         return 0;
 101 }
 102
 103 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
 104                 struct snd_soc_dai *dai)
 105 {
 106         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 107         struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
 108         unsigned int id = dai->driver->id;
 109
 110         clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
 111         /*
 112          * Ensure LRCLK is disabled even in device node validation.
 113          * Will not impact if disabled in lpass_cpu_daiops_trigger()
 114          * suspend.
 115          */
 116         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 117                 regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_DISABLE);
 118         else
 119                 regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_DISABLE);
 120
 121         /*
 122          * BCLK may not be enabled if lpass_cpu_daiops_prepare is called before
 123          * lpass_cpu_daiops_shutdown. It's paired with the clk_enable in
 124          * lpass_cpu_daiops_prepare.
 125          */
 126         if (drvdata->mi2s_was_prepared[dai->driver->id]) {
 127                 drvdata->mi2s_was_prepared[dai->driver->id] = false;
 128                 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
 129         }
 130
 131         clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
 132 }
 133
 134 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
 135                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 136 {
 137         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 138         struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
 139         unsigned int id = dai->driver->id;
 140         snd_pcm_format_t format = params_format(params);
 141         unsigned int channels = params_channels(params);
 142         unsigned int rate = params_rate(params);
 143         unsigned int mode;
 144         unsigned int regval;
 145         int bitwidth, ret;
 146
 147         bitwidth = snd_pcm_format_width(format);
 148         if (bitwidth < 0) {
 149                 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
 150                 return bitwidth;
 151         }
 152
 153         ret = regmap_fields_write(i2sctl->loopback, id,
 154                                  LPAIF_I2SCTL_LOOPBACK_DISABLE);
 155         if (ret) {
 156                 dev_err(dai->dev, "error updating loopback field: %d\n", ret);
 157                 return ret;
 158         }
 159
 160         ret = regmap_fields_write(i2sctl->wssrc, id,
 161                                  LPAIF_I2SCTL_WSSRC_INTERNAL);
 162         if (ret) {
 163                 dev_err(dai->dev, "error updating wssrc field: %d\n", ret);
 164                 return ret;
 165         }
 166
 167         switch (bitwidth) {
 168         case 16:
 169                 regval = LPAIF_I2SCTL_BITWIDTH_16;
 170                 break;
 171         case 24:
 172                 regval = LPAIF_I2SCTL_BITWIDTH_24;
 173                 break;
 174         case 32:
 175                 regval = LPAIF_I2SCTL_BITWIDTH_32;
 176                 break;
 177         default:
 178                 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
 179                 return -EINVAL;
 180         }
 181
 182         ret = regmap_fields_write(i2sctl->bitwidth, id, regval);
 183         if (ret) {
 184                 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret);
 185                 return ret;
 186         }
 187
 188         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 189                 mode = drvdata->mi2s_playback_sd_mode[id];
 190         else
 191                 mode = drvdata->mi2s_capture_sd_mode[id];
 192
 193         if (!mode) {
 194                 dev_err(dai->dev, "no line is assigned\n");
 195                 return -EINVAL;
 196         }
 197
 198         switch (channels) {
 199         case 1:
 200         case 2:
 201                 switch (mode) {
 202                 case LPAIF_I2SCTL_MODE_QUAD01:
 203                 case LPAIF_I2SCTL_MODE_6CH:
 204                 case LPAIF_I2SCTL_MODE_8CH:
 205                         mode = LPAIF_I2SCTL_MODE_SD0;
 206                         break;
 207                 case LPAIF_I2SCTL_MODE_QUAD23:
 208                         mode = LPAIF_I2SCTL_MODE_SD2;
 209                         break;
 210                 }
 211
 212                 break;
 213         case 4:
 214                 if (mode < LPAIF_I2SCTL_MODE_QUAD01) {
 215                         dev_err(dai->dev, "cannot configure 4 channels with mode %d\n",
 216                                 mode);
 217                         return -EINVAL;
 218                 }
 219
 220                 switch (mode) {
 221                 case LPAIF_I2SCTL_MODE_6CH:
 222                 case LPAIF_I2SCTL_MODE_8CH:
 223                         mode = LPAIF_I2SCTL_MODE_QUAD01;
 224                         break;
 225                 }
 226                 break;
 227         case 6:
 228                 if (mode < LPAIF_I2SCTL_MODE_6CH) {
 229                         dev_err(dai->dev, "cannot configure 6 channels with mode %d\n",
 230                                 mode);
 231                         return -EINVAL;
 232                 }
 233
 234                 switch (mode) {
 235                 case LPAIF_I2SCTL_MODE_8CH:
 236                         mode = LPAIF_I2SCTL_MODE_6CH;
 237                         break;
 238                 }
 239                 break;
 240         case 8:
 241                 if (mode < LPAIF_I2SCTL_MODE_8CH) {
 242                         dev_err(dai->dev, "cannot configure 8 channels with mode %d\n",
 243                                 mode);
 244                         return -EINVAL;
 245                 }
 246                 break;
 247         default:
 248                 dev_err(dai->dev, "invalid channels given: %u\n", channels);
 249                 return -EINVAL;
 250         }
 251
 252         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 253                 ret = regmap_fields_write(i2sctl->spkmode, id,
 254                                          LPAIF_I2SCTL_SPKMODE(mode));
 255                 if (ret) {
 256                         dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n",
 257                                 ret);
 258                         return ret;
 259                 }
 260                 if (channels >= 2)
 261                         ret = regmap_fields_write(i2sctl->spkmono, id,
 262                                                  LPAIF_I2SCTL_SPKMONO_STEREO);
 263                 else
 264                         ret = regmap_fields_write(i2sctl->spkmono, id,
 265                                                  LPAIF_I2SCTL_SPKMONO_MONO);
 266         } else {
 267                 ret = regmap_fields_write(i2sctl->micmode, id,
 268                                          LPAIF_I2SCTL_MICMODE(mode));
 269                 if (ret) {
 270                         dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n",
 271                                 ret);
 272                         return ret;
 273                 }
 274                 if (channels >= 2)
 275                         ret = regmap_fields_write(i2sctl->micmono, id,
 276                                                  LPAIF_I2SCTL_MICMONO_STEREO);
 277                 else
 278                         ret = regmap_fields_write(i2sctl->micmono, id,
 279                                                  LPAIF_I2SCTL_MICMONO_MONO);
 280         }
 281
 282         if (ret) {
 283                 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n",
 284                         ret);
 285                 return ret;
 286         }
 287
 288         ret = clk_set_rate(drvdata->mi2s_bit_clk[id],
 289                            rate * bitwidth * 2);
 290         if (ret) {
 291                 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
 292                         rate * bitwidth * 2, ret);
 293                 return ret;
 294         }
 295
 296         return 0;
 297 }
 298
 299 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
 300                 int cmd, struct snd_soc_dai *dai)
 301 {
 302         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 303         struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
 304         unsigned int id = dai->driver->id;
 305         int ret = -EINVAL;
 306
 307         switch (cmd) {
 308         case SNDRV_PCM_TRIGGER_START:
 309         case SNDRV_PCM_TRIGGER_RESUME:
 310         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 311                 /*
 312                  * Ensure lpass BCLK/LRCLK is enabled during
 313                  * device resume as lpass_cpu_daiops_prepare() is not called
 314                  * after the device resumes. We don't check mi2s_was_prepared before
 315                  * enable/disable BCLK in trigger events because:
 316                  *  1. These trigger events are paired, so the BCLK
 317                  *     enable_count is balanced.
 318                  *  2. the BCLK can be shared (ex: headset and headset mic),
 319                  *     we need to increase the enable_count so that we don't
 320                  *     turn off the shared BCLK while other devices are using
 321                  *     it.
 322                  */
 323                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 324                         ret = regmap_fields_write(i2sctl->spken, id,
 325                                                  LPAIF_I2SCTL_SPKEN_ENABLE);
 326                 } else  {
 327                         ret = regmap_fields_write(i2sctl->micen, id,
 328                                                  LPAIF_I2SCTL_MICEN_ENABLE);
 329                 }
 330                 if (ret)
 331                         dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
 332                                 ret);
 333
 334                 ret = clk_enable(drvdata->mi2s_bit_clk[id]);
 335                 if (ret) {
 336                         dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
 337                         clk_disable(drvdata->mi2s_osr_clk[id]);
 338                         return ret;
 339                 }
 340                 break;
 341         case SNDRV_PCM_TRIGGER_STOP:
 342         case SNDRV_PCM_TRIGGER_SUSPEND:
 343         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 344                 /*
 345                  * To ensure lpass BCLK/LRCLK is disabled during
 346                  * device suspend.
 347                  */
 348                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 349                         ret = regmap_fields_write(i2sctl->spken, id,
 350                                                  LPAIF_I2SCTL_SPKEN_DISABLE);
 351                 } else  {
 352                         ret = regmap_fields_write(i2sctl->micen, id,
 353                                                  LPAIF_I2SCTL_MICEN_DISABLE);
 354                 }
 355                 if (ret)
 356                         dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
 357                                 ret);
 358
 359                 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
 360
 361                 break;
 362         }
 363
 364         return ret;
 365 }
 366
 367 static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
 368                 struct snd_soc_dai *dai)
 369 {
 370         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 371         struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
 372         unsigned int id = dai->driver->id;
 373         int ret;
 374
 375         /*
 376          * Ensure lpass BCLK/LRCLK is enabled bit before playback/capture
 377          * data flow starts. This allows other codec to have some delay before
 378          * the data flow.
 379          * (ex: to drop start up pop noise before capture starts).
 380          */
 381         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 382                 ret = regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_ENABLE);
 383         else
 384                 ret = regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_ENABLE);
 385
 386         if (ret) {
 387                 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
 388                 return ret;
 389         }
 390
 391         /*
 392          * Check mi2s_was_prepared before enabling BCLK as lpass_cpu_daiops_prepare can
 393          * be called multiple times. It's paired with the clk_disable in
 394          * lpass_cpu_daiops_shutdown.
 395          */
 396         if (!drvdata->mi2s_was_prepared[dai->driver->id]) {
 397                 ret = clk_enable(drvdata->mi2s_bit_clk[id]);
 398                 if (ret) {
 399                         dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
 400                         return ret;
 401                 }
 402                 drvdata->mi2s_was_prepared[dai->driver->id] = true;
 403         }
 404         return 0;
 405 }
 406
 407 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
 408         .set_sysclk     = lpass_cpu_daiops_set_sysclk,
 409         .startup        = lpass_cpu_daiops_startup,
 410         .shutdown       = lpass_cpu_daiops_shutdown,
 411         .hw_params      = lpass_cpu_daiops_hw_params,
 412         .trigger        = lpass_cpu_daiops_trigger,
 413         .prepare        = lpass_cpu_daiops_prepare,
 414 };
 415 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
 416
 417 int lpass_cpu_pcm_new(struct snd_soc_pcm_runtime *rtd,
 418                                 struct snd_soc_dai *dai)
 419 {
 420         int ret;
 421         struct snd_soc_dai_driver *drv = dai->driver;
 422         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 423
 424         if (drvdata->mi2s_playback_sd_mode[dai->id] == LPAIF_I2SCTL_MODE_QUAD01) {
 425                 ret =  snd_pcm_add_chmap_ctls(rtd->pcm, SNDRV_PCM_STREAM_PLAYBACK,
 426                                 lpass_quad_chmaps, drv->playback.channels_max, 0,
 427                                 NULL);
 428                 if (ret < 0)
 429                         return ret;
 430         }
 431
 432         return 0;
 433 }
 434 EXPORT_SYMBOL_GPL(lpass_cpu_pcm_new);
 435
 436 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
 437 {
 438         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 439         int ret;
 440
 441         /* ensure audio hardware is disabled */
 442         ret = regmap_write(drvdata->lpaif_map,
 443                         LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
 444         if (ret)
 445                 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
 446
 447         return ret;
 448 }
 449 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
 450
 451 static int asoc_qcom_of_xlate_dai_name(struct snd_soc_component *component,
 452                                    const struct of_phandle_args *args,
 453                                    const char **dai_name)
 454 {
 455         struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
 456         struct lpass_variant *variant = drvdata->variant;
 457         int id = args->args[0];
 458         int ret = -EINVAL;
 459         int i;
 460
 461         for (i = 0; i  < variant->num_dai; i++) {
 462                 if (variant->dai_driver[i].id == id) {
 463                         *dai_name = variant->dai_driver[i].name;
 464                         ret = 0;
 465                         break;
 466                 }
 467         }
 468
 469         return ret;
 470 }
 471
 472 static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
 473         .name = "lpass-cpu",
 474         .of_xlate_dai_name = asoc_qcom_of_xlate_dai_name,
 475         .legacy_dai_naming = 1,
 476 };
 477
 478 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
 479 {
 480         struct lpass_data *drvdata = dev_get_drvdata(dev);
 481         struct lpass_variant *v = drvdata->variant;
 482         int i;
 483
 484         for (i = 0; i < v->i2s_ports; ++i)
 485                 if (reg == LPAIF_I2SCTL_REG(v, i))
 486                         return true;
 487
 488         for (i = 0; i < v->irq_ports; ++i) {
 489                 if (reg == LPAIF_IRQEN_REG(v, i))
 490                         return true;
 491                 if (reg == LPAIF_IRQCLEAR_REG(v, i))
 492                         return true;
 493         }
 494
 495         for (i = 0; i < v->rdma_channels; ++i) {
 496                 if (reg == LPAIF_RDMACTL_REG(v, i))
 497                         return true;
 498                 if (reg == LPAIF_RDMABASE_REG(v, i))
 499                         return true;
 500                 if (reg == LPAIF_RDMABUFF_REG(v, i))
 501                         return true;
 502                 if (reg == LPAIF_RDMAPER_REG(v, i))
 503                         return true;
 504         }
 505
 506         for (i = 0; i < v->wrdma_channels; ++i) {
 507                 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
 508                         return true;
 509                 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
 510                         return true;
 511                 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
 512                         return true;
 513                 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
 514                         return true;
 515         }
 516
 517         return false;
 518 }
 519
 520 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
 521 {
 522         struct lpass_data *drvdata = dev_get_drvdata(dev);
 523         struct lpass_variant *v = drvdata->variant;
 524         int i;
 525
 526         for (i = 0; i < v->i2s_ports; ++i)
 527                 if (reg == LPAIF_I2SCTL_REG(v, i))
 528                         return true;
 529
 530         for (i = 0; i < v->irq_ports; ++i) {
 531                 if (reg == LPAIF_IRQCLEAR_REG(v, i))
 532                         return true;
 533                 if (reg == LPAIF_IRQEN_REG(v, i))
 534                         return true;
 535                 if (reg == LPAIF_IRQSTAT_REG(v, i))
 536                         return true;
 537         }
 538
 539         for (i = 0; i < v->rdma_channels; ++i) {
 540                 if (reg == LPAIF_RDMACTL_REG(v, i))
 541                         return true;
 542                 if (reg == LPAIF_RDMABASE_REG(v, i))
 543                         return true;
 544                 if (reg == LPAIF_RDMABUFF_REG(v, i))
 545                         return true;
 546                 if (reg == LPAIF_RDMACURR_REG(v, i))
 547                         return true;
 548                 if (reg == LPAIF_RDMAPER_REG(v, i))
 549                         return true;
 550         }
 551
 552         for (i = 0; i < v->wrdma_channels; ++i) {
 553                 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
 554                         return true;
 555                 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
 556                         return true;
 557                 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
 558                         return true;
 559                 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
 560                         return true;
 561                 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
 562                         return true;
 563         }
 564
 565         return false;
 566 }
 567
 568 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
 569 {
 570         struct lpass_data *drvdata = dev_get_drvdata(dev);
 571         struct lpass_variant *v = drvdata->variant;
 572         int i;
 573
 574         for (i = 0; i < v->irq_ports; ++i) {
 575                 if (reg == LPAIF_IRQCLEAR_REG(v, i))
 576                         return true;
 577                 if (reg == LPAIF_IRQSTAT_REG(v, i))
 578                         return true;
 579         }
 580
 581         for (i = 0; i < v->rdma_channels; ++i)
 582                 if (reg == LPAIF_RDMACURR_REG(v, i))
 583                         return true;
 584
 585         for (i = 0; i < v->wrdma_channels; ++i)
 586                 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
 587                         return true;
 588
 589         return false;
 590 }
 591
 592 static struct regmap_config lpass_cpu_regmap_config = {
 593         .name = "lpass_cpu",
 594         .reg_bits = 32,
 595         .reg_stride = 4,
 596         .val_bits = 32,
 597         .writeable_reg = lpass_cpu_regmap_writeable,
 598         .readable_reg = lpass_cpu_regmap_readable,
 599         .volatile_reg = lpass_cpu_regmap_volatile,
 600         .cache_type = REGCACHE_FLAT,
 601 };
 602
 603 static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)
 604 {
 605         struct lpass_data *drvdata = dev_get_drvdata(dev);
 606         struct lpass_variant *v = drvdata->variant;
 607         unsigned int i;
 608         struct lpass_hdmi_tx_ctl *tx_ctl;
 609         struct regmap_field *legacy_en;
 610         struct lpass_vbit_ctrl *vbit_ctl;
 611         struct regmap_field *tx_parity;
 612         struct lpass_dp_metadata_ctl *meta_ctl;
 613         struct lpass_sstream_ctl *sstream_ctl;
 614         struct regmap_field *ch_msb;
 615         struct regmap_field *ch_lsb;
 616         struct lpass_hdmitx_dmactl *tx_dmactl;
 617         int rval;
 618
 619         tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL);
 620         if (!tx_ctl)
 621                 return -ENOMEM;
 622
 623         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);
 624         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);
 625         drvdata->tx_ctl = tx_ctl;
 626
 627         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);
 628         drvdata->hdmitx_legacy_en = legacy_en;
 629
 630         vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL);
 631         if (!vbit_ctl)
 632                 return -ENOMEM;
 633
 634         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);
 635         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);
 636         drvdata->vbit_ctl = vbit_ctl;
 637
 638
 639         QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);
 640         drvdata->hdmitx_parity_calc_en = tx_parity;
 641
 642         meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL);
 643         if (!meta_ctl)
 644                 return -ENOMEM;
 645
 646         rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);
 647         if (rval)
 648                 return rval;
 649         drvdata->meta_ctl = meta_ctl;
 650
 651         sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL);
 652         if (!sstream_ctl)
 653                 return -ENOMEM;
 654
 655         rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);
 656         if (rval)
 657                 return rval;
 658
 659         drvdata->sstream_ctl = sstream_ctl;
 660
 661         for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) {
 662                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);
 663                 drvdata->hdmitx_ch_msb[i] = ch_msb;
 664
 665                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);
 666                 drvdata->hdmitx_ch_lsb[i] = ch_lsb;
 667
 668                 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL);
 669                 if (!tx_dmactl)
 670                         return -ENOMEM;
 671
 672                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);
 673                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);
 674                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);
 675                 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);
 676                 drvdata->hdmi_tx_dmactl[i] = tx_dmactl;
 677         }
 678         return 0;
 679 }
 680
 681 static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg)
 682 {
 683         struct lpass_data *drvdata = dev_get_drvdata(dev);
 684         struct lpass_variant *v = drvdata->variant;
 685         int i;
 686
 687         if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
 688                 return true;
 689         if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
 690                 return true;
 691         if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
 692                 return true;
 693         if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
 694                 return true;
 695         if (reg == LPASS_HDMI_TX_DP_ADDR(v))
 696                 return true;
 697         if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
 698                 return true;
 699         if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
 700                 return true;
 701         if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v))
 702                 return true;
 703
 704         for (i = 0; i < v->hdmi_rdma_channels; i++) {
 705                 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
 706                         return true;
 707                 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
 708                         return true;
 709                 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
 710                         return true;
 711         }
 712
 713         for (i = 0; i < v->hdmi_rdma_channels; ++i) {
 714                 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
 715                         return true;
 716                 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
 717                         return true;
 718                 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
 719                         return true;
 720                 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
 721                         return true;
 722         }
 723         return false;
 724 }
 725
 726 static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg)
 727 {
 728         struct lpass_data *drvdata = dev_get_drvdata(dev);
 729         struct lpass_variant *v = drvdata->variant;
 730         int i;
 731
 732         if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
 733                 return true;
 734         if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
 735                 return true;
 736         if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
 737                 return true;
 738
 739         for (i = 0; i < v->hdmi_rdma_channels; i++) {
 740                 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
 741                         return true;
 742                 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
 743                         return true;
 744                 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
 745                         return true;
 746         }
 747
 748         if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
 749                 return true;
 750         if (reg == LPASS_HDMI_TX_DP_ADDR(v))
 751                 return true;
 752         if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
 753                 return true;
 754         if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
 755                 return true;
 756         if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
 757                 return true;
 758
 759         for (i = 0; i < v->hdmi_rdma_channels; ++i) {
 760                 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
 761                         return true;
 762                 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
 763                         return true;
 764                 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
 765                         return true;
 766                 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
 767                         return true;
 768                 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
 769                         return true;
 770         }
 771
 772         return false;
 773 }
 774
 775 static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg)
 776 {
 777         struct lpass_data *drvdata = dev_get_drvdata(dev);
 778         struct lpass_variant *v = drvdata->variant;
 779         int i;
 780
 781         if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
 782                 return true;
 783         if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
 784                 return true;
 785         if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
 786                 return true;
 787         if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
 788                 return true;
 789
 790         for (i = 0; i < v->hdmi_rdma_channels; ++i) {
 791                 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
 792                         return true;
 793                 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
 794                         return true;
 795                 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
 796                         return true;
 797                 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
 798                         return true;
 799         }
 800         return false;
 801 }
 802
 803 static struct regmap_config lpass_hdmi_regmap_config = {
 804         .name = "lpass_hdmi",
 805         .reg_bits = 32,
 806         .reg_stride = 4,
 807         .val_bits = 32,
 808         .writeable_reg = lpass_hdmi_regmap_writeable,
 809         .readable_reg = lpass_hdmi_regmap_readable,
 810         .volatile_reg = lpass_hdmi_regmap_volatile,
 811         .cache_type = REGCACHE_FLAT,
 812 };
 813
 814 static bool __lpass_rxtx_regmap_accessible(struct device *dev, unsigned int reg, bool rw)
 815 {
 816         struct lpass_data *drvdata = dev_get_drvdata(dev);
 817         struct lpass_variant *v = drvdata->variant;
 818         int i;
 819
 820         for (i = 0; i < v->rxtx_irq_ports; ++i) {
 821                 if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
 822                         return true;
 823                 if (reg == LPAIF_RXTX_IRQEN_REG(v, i))
 824                         return true;
 825                 if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
 826                         return true;
 827         }
 828
 829         for (i = 0; i < v->rxtx_rdma_channels; ++i) {
 830                 if (reg == LPAIF_CDC_RXTX_RDMACTL_REG(v, i, LPASS_CDC_DMA_RX0))
 831                         return true;
 832                 if (reg == LPAIF_CDC_RXTX_RDMABASE_REG(v, i, LPASS_CDC_DMA_RX0))
 833                         return true;
 834                 if (reg == LPAIF_CDC_RXTX_RDMABUFF_REG(v, i, LPASS_CDC_DMA_RX0))
 835                         return true;
 836                 if (rw == LPASS_REG_READ) {
 837                         if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
 838                                 return true;
 839                 }
 840                 if (reg == LPAIF_CDC_RXTX_RDMAPER_REG(v, i, LPASS_CDC_DMA_RX0))
 841                         return true;
 842                 if (reg == LPAIF_CDC_RXTX_RDMA_INTF_REG(v, i, LPASS_CDC_DMA_RX0))
 843                         return true;
 844         }
 845
 846         for (i = 0; i < v->rxtx_wrdma_channels; ++i) {
 847                 if (reg == LPAIF_CDC_RXTX_WRDMACTL_REG(v, i + v->rxtx_wrdma_channel_start,
 848                                                         LPASS_CDC_DMA_TX3))
 849                         return true;
 850                 if (reg == LPAIF_CDC_RXTX_WRDMABASE_REG(v, i + v->rxtx_wrdma_channel_start,
 851                                                         LPASS_CDC_DMA_TX3))
 852                         return true;
 853                 if (reg == LPAIF_CDC_RXTX_WRDMABUFF_REG(v, i + v->rxtx_wrdma_channel_start,
 854                                                         LPASS_CDC_DMA_TX3))
 855                         return true;
 856                 if (rw == LPASS_REG_READ) {
 857                         if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
 858                                 return true;
 859                 }
 860                 if (reg == LPAIF_CDC_RXTX_WRDMAPER_REG(v, i + v->rxtx_wrdma_channel_start,
 861                                                         LPASS_CDC_DMA_TX3))
 862                         return true;
 863                 if (reg == LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, i + v->rxtx_wrdma_channel_start,
 864                                                         LPASS_CDC_DMA_TX3))
 865                         return true;
 866         }
 867         return false;
 868 }
 869
 870 static bool lpass_rxtx_regmap_writeable(struct device *dev, unsigned int reg)
 871 {
 872         return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_WRITE);
 873 }
 874
 875 static bool lpass_rxtx_regmap_readable(struct device *dev, unsigned int reg)
 876 {
 877         return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_READ);
 878 }
 879
 880 static bool lpass_rxtx_regmap_volatile(struct device *dev, unsigned int reg)
 881 {
 882         struct lpass_data *drvdata = dev_get_drvdata(dev);
 883         struct lpass_variant *v = drvdata->variant;
 884         int i;
 885
 886         for (i = 0; i < v->rxtx_irq_ports; ++i) {
 887                 if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
 888                         return true;
 889                 if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
 890                         return true;
 891         }
 892
 893         for (i = 0; i < v->rxtx_rdma_channels; ++i)
 894                 if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
 895                         return true;
 896
 897         for (i = 0; i < v->rxtx_wrdma_channels; ++i)
 898                 if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i + v->rxtx_wrdma_channel_start,
 899                                                         LPASS_CDC_DMA_TX3))
 900                         return true;
 901
 902         return false;
 903 }
 904
 905 static bool __lpass_va_regmap_accessible(struct device *dev, unsigned int reg, bool rw)
 906 {
 907         struct lpass_data *drvdata = dev_get_drvdata(dev);
 908         struct lpass_variant *v = drvdata->variant;
 909         int i;
 910
 911         for (i = 0; i < v->va_irq_ports; ++i) {
 912                 if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
 913                         return true;
 914                 if (reg == LPAIF_VA_IRQEN_REG(v, i))
 915                         return true;
 916                 if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
 917                         return true;
 918         }
 919
 920         for (i = 0; i < v->va_wrdma_channels; ++i) {
 921                 if (reg == LPAIF_CDC_VA_WRDMACTL_REG(v, i + v->va_wrdma_channel_start,
 922                                                         LPASS_CDC_DMA_VA_TX0))
 923                         return true;
 924                 if (reg == LPAIF_CDC_VA_WRDMABASE_REG(v, i + v->va_wrdma_channel_start,
 925                                                         LPASS_CDC_DMA_VA_TX0))
 926                         return true;
 927                 if (reg == LPAIF_CDC_VA_WRDMABUFF_REG(v, i + v->va_wrdma_channel_start,
 928                                                         LPASS_CDC_DMA_VA_TX0))
 929                         return true;
 930                 if (rw == LPASS_REG_READ) {
 931                         if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
 932                                                         LPASS_CDC_DMA_VA_TX0))
 933                                 return true;
 934                 }
 935                 if (reg == LPAIF_CDC_VA_WRDMAPER_REG(v, i + v->va_wrdma_channel_start,
 936                                                         LPASS_CDC_DMA_VA_TX0))
 937                         return true;
 938                 if (reg == LPAIF_CDC_VA_WRDMA_INTF_REG(v, i + v->va_wrdma_channel_start,
 939                                                         LPASS_CDC_DMA_VA_TX0))
 940                         return true;
 941         }
 942         return false;
 943 }
 944
 945 static bool lpass_va_regmap_writeable(struct device *dev, unsigned int reg)
 946 {
 947         return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_WRITE);
 948 }
 949
 950 static bool lpass_va_regmap_readable(struct device *dev, unsigned int reg)
 951 {
 952         return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_READ);
 953 }
 954
 955 static bool lpass_va_regmap_volatile(struct device *dev, unsigned int reg)
 956 {
 957         struct lpass_data *drvdata = dev_get_drvdata(dev);
 958         struct lpass_variant *v = drvdata->variant;
 959         int i;
 960
 961         for (i = 0; i < v->va_irq_ports; ++i) {
 962                 if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
 963                         return true;
 964                 if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
 965                         return true;
 966         }
 967
 968         for (i = 0; i < v->va_wrdma_channels; ++i) {
 969                 if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
 970                                                         LPASS_CDC_DMA_VA_TX0))
 971                         return true;
 972         }
 973
 974         return false;
 975 }
 976
 977 static struct regmap_config lpass_rxtx_regmap_config = {
 978         .reg_bits = 32,
 979         .reg_stride = 4,
 980         .val_bits = 32,
 981         .writeable_reg = lpass_rxtx_regmap_writeable,
 982         .readable_reg = lpass_rxtx_regmap_readable,
 983         .volatile_reg = lpass_rxtx_regmap_volatile,
 984         .cache_type = REGCACHE_FLAT,
 985 };
 986
 987 static struct regmap_config lpass_va_regmap_config = {
 988         .reg_bits = 32,
 989         .reg_stride = 4,
 990         .val_bits = 32,
 991         .writeable_reg = lpass_va_regmap_writeable,
 992         .readable_reg = lpass_va_regmap_readable,
 993         .volatile_reg = lpass_va_regmap_volatile,
 994         .cache_type = REGCACHE_FLAT,
 995 };
 996
 997 static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,
 998                                                 struct device_node *node,
 999                                                 const char *name)
1000 {
1001         unsigned int lines[LPASS_CPU_MAX_MI2S_LINES];
1002         unsigned int sd_line_mask = 0;
1003         int num_lines, i;
1004
1005         num_lines = of_property_read_variable_u32_array(node, name, lines, 0,
1006                                                         LPASS_CPU_MAX_MI2S_LINES);
1007         if (num_lines < 0)
1008                 return LPAIF_I2SCTL_MODE_NONE;
1009
1010         for (i = 0; i < num_lines; i++)
1011                 sd_line_mask |= BIT(lines[i]);
1012
1013         switch (sd_line_mask) {
1014         case LPASS_CPU_I2S_SD0_MASK:
1015                 return LPAIF_I2SCTL_MODE_SD0;
1016         case LPASS_CPU_I2S_SD1_MASK:
1017                 return LPAIF_I2SCTL_MODE_SD1;
1018         case LPASS_CPU_I2S_SD2_MASK:
1019                 return LPAIF_I2SCTL_MODE_SD2;
1020         case LPASS_CPU_I2S_SD3_MASK:
1021                 return LPAIF_I2SCTL_MODE_SD3;
1022         case LPASS_CPU_I2S_SD0_1_MASK:
1023                 return LPAIF_I2SCTL_MODE_QUAD01;
1024         case LPASS_CPU_I2S_SD2_3_MASK:
1025                 return LPAIF_I2SCTL_MODE_QUAD23;
1026         case LPASS_CPU_I2S_SD0_1_2_MASK:
1027                 return LPAIF_I2SCTL_MODE_6CH;
1028         case LPASS_CPU_I2S_SD0_1_2_3_MASK:
1029                 return LPAIF_I2SCTL_MODE_8CH;
1030         default:
1031                 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask);
1032                 return LPAIF_I2SCTL_MODE_NONE;
1033         }
1034 }
1035
1036 static void of_lpass_cpu_parse_dai_data(struct device *dev,
1037                                         struct lpass_data *data)
1038 {
1039         struct device_node *node;
1040         int ret, i, id;
1041
1042         /* Allow all channels by default for backwards compatibility */
1043         for (i = 0; i < data->variant->num_dai; i++) {
1044                 id = data->variant->dai_driver[i].id;
1045                 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
1046                 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
1047         }
1048
1049         for_each_child_of_node(dev->of_node, node) {
1050                 ret = of_property_read_u32(node, "reg", &id);
1051                 if (ret || id < 0) {
1052                         dev_err(dev, "valid dai id not found: %d\n", ret);
1053                         continue;
1054                 }
1055                 if (id == LPASS_DP_RX) {
1056                         data->hdmi_port_enable = 1;
1057                 } else if (is_cdc_dma_port(id)) {
1058                         data->codec_dma_enable = 1;
1059                 } else {
1060                         data->mi2s_playback_sd_mode[id] =
1061                                 of_lpass_cpu_parse_sd_lines(dev, node,
1062                                                             "qcom,playback-sd-lines");
1063                         data->mi2s_capture_sd_mode[id] =
1064                                 of_lpass_cpu_parse_sd_lines(dev, node,
1065                                                     "qcom,capture-sd-lines");
1066                 }
1067         }
1068 }
1069
1070 static int of_lpass_cdc_dma_clks_parse(struct device *dev,
1071                                         struct lpass_data *data)
1072 {
1073         data->codec_mem0 = devm_clk_get(dev, "audio_cc_codec_mem0");
1074         if (IS_ERR(data->codec_mem0))
1075                 return PTR_ERR(data->codec_mem0);
1076
1077         data->codec_mem1 = devm_clk_get(dev, "audio_cc_codec_mem1");
1078         if (IS_ERR(data->codec_mem1))
1079                 return PTR_ERR(data->codec_mem1);
1080
1081         data->codec_mem2 = devm_clk_get(dev, "audio_cc_codec_mem2");
1082         if (IS_ERR(data->codec_mem2))
1083                 return PTR_ERR(data->codec_mem2);
1084
1085         data->va_mem0 = devm_clk_get(dev, "aon_cc_va_mem0");
1086         if (IS_ERR(data->va_mem0))
1087                 return PTR_ERR(data->va_mem0);
1088
1089         return 0;
1090 }
1091
1092 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
1093 {
1094         struct lpass_data *drvdata;
1095         struct device_node *dsp_of_node;
1096         struct resource *res;
1097         struct lpass_variant *variant;
1098         struct device *dev = &pdev->dev;
1099         const struct of_device_id *match;
1100         int ret, i, dai_id;
1101
1102         dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
1103         if (dsp_of_node) {
1104                 dev_err(dev, "DSP exists and holds audio resources\n");
1105                 of_node_put(dsp_of_node);
1106                 return -EBUSY;
1107         }
1108
1109         drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL);
1110         if (!drvdata)
1111                 return -ENOMEM;
1112         platform_set_drvdata(pdev, drvdata);
1113
1114         match = of_match_device(dev->driver->of_match_table, dev);
1115         if (!match || !match->data)
1116                 return -EINVAL;
1117
1118         if (of_device_is_compatible(dev->of_node, "qcom,lpass-cpu-apq8016")) {
1119                 dev_warn(dev, "%s compatible is deprecated\n",
1120                          match->compatible);
1121         }
1122
1123         drvdata->variant = (struct lpass_variant *)match->data;
1124         variant = drvdata->variant;
1125
1126         of_lpass_cpu_parse_dai_data(dev, drvdata);
1127
1128         if (drvdata->codec_dma_enable) {
1129                 drvdata->rxtx_lpaif =
1130                                 devm_platform_ioremap_resource_byname(pdev, "lpass-rxtx-lpaif");
1131                 if (IS_ERR(drvdata->rxtx_lpaif))
1132                         return PTR_ERR(drvdata->rxtx_lpaif);
1133
1134                 drvdata->va_lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-va-lpaif");
1135                 if (IS_ERR(drvdata->va_lpaif))
1136                         return PTR_ERR(drvdata->va_lpaif);
1137
1138                 lpass_rxtx_regmap_config.max_register = LPAIF_CDC_RXTX_WRDMAPER_REG(variant,
1139                                         variant->rxtx_wrdma_channels +
1140                                         variant->rxtx_wrdma_channel_start, LPASS_CDC_DMA_TX3);
1141
1142                 drvdata->rxtx_lpaif_map = devm_regmap_init_mmio(dev, drvdata->rxtx_lpaif,
1143                                         &lpass_rxtx_regmap_config);
1144                 if (IS_ERR(drvdata->rxtx_lpaif_map))
1145                         return PTR_ERR(drvdata->rxtx_lpaif_map);
1146
1147                 lpass_va_regmap_config.max_register = LPAIF_CDC_VA_WRDMAPER_REG(variant,
1148                                         variant->va_wrdma_channels +
1149                                         variant->va_wrdma_channel_start, LPASS_CDC_DMA_VA_TX0);
1150
1151                 drvdata->va_lpaif_map = devm_regmap_init_mmio(dev, drvdata->va_lpaif,
1152                                         &lpass_va_regmap_config);
1153                 if (IS_ERR(drvdata->va_lpaif_map))
1154                         return PTR_ERR(drvdata->va_lpaif_map);
1155
1156                 ret = of_lpass_cdc_dma_clks_parse(dev, drvdata);
1157                 if (ret) {
1158                         dev_err(dev, "failed to get cdc dma clocks %d\n", ret);
1159                         return ret;
1160                 }
1161
1162                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-rxtx-cdc-dma-lpm");
1163                 drvdata->rxtx_cdc_dma_lpm_buf = res->start;
1164
1165                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-va-cdc-dma-lpm");
1166                 drvdata->va_cdc_dma_lpm_buf = res->start;
1167         }
1168
1169         drvdata->lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-lpaif");
1170         if (IS_ERR(drvdata->lpaif))
1171                 return PTR_ERR(drvdata->lpaif);
1172
1173         lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
1174                                                 variant->wrdma_channels +
1175                                                 variant->wrdma_channel_start);
1176
1177         drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif,
1178                         &lpass_cpu_regmap_config);
1179         if (IS_ERR(drvdata->lpaif_map)) {
1180                 dev_err(dev, "error initializing regmap: %ld\n",
1181                         PTR_ERR(drvdata->lpaif_map));
1182                 return PTR_ERR(drvdata->lpaif_map);
1183         }
1184
1185         if (drvdata->hdmi_port_enable) {
1186                 drvdata->hdmiif = devm_platform_ioremap_resource_byname(pdev, "lpass-hdmiif");
1187                 if (IS_ERR(drvdata->hdmiif))
1188                         return PTR_ERR(drvdata->hdmiif);
1189
1190                 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant,
1191                                         variant->hdmi_rdma_channels - 1);
1192                 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif,
1193                                         &lpass_hdmi_regmap_config);
1194                 if (IS_ERR(drvdata->hdmiif_map)) {
1195                         dev_err(dev, "error initializing regmap: %ld\n",
1196                         PTR_ERR(drvdata->hdmiif_map));
1197                         return PTR_ERR(drvdata->hdmiif_map);
1198                 }
1199         }
1200
1201         if (variant->init) {
1202                 ret = variant->init(pdev);
1203                 if (ret) {
1204                         dev_err(dev, "error initializing variant: %d\n", ret);
1205                         return ret;
1206                 }
1207         }
1208
1209         for (i = 0; i < variant->num_dai; i++) {
1210                 dai_id = variant->dai_driver[i].id;
1211                 if (dai_id == LPASS_DP_RX || is_cdc_dma_port(dai_id))
1212                         continue;
1213
1214                 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev,
1215                                              variant->dai_osr_clk_names[i]);
1216                 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev,
1217                                                 variant->dai_bit_clk_names[i]);
1218                 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
1219                         dev_err(dev,
1220                                 "error getting %s: %ld\n",
1221                                 variant->dai_bit_clk_names[i],
1222                                 PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
1223                         return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
1224                 }
1225                 if (drvdata->mi2s_playback_sd_mode[dai_id] ==
1226                         LPAIF_I2SCTL_MODE_QUAD01) {
1227                         variant->dai_driver[dai_id].playback.channels_min = 4;
1228                         variant->dai_driver[dai_id].playback.channels_max = 4;
1229                 }
1230         }
1231
1232         /* Allocation for i2sctl regmap fields */
1233         drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl),
1234                                         GFP_KERNEL);
1235
1236         /* Initialize bitfields for dai I2SCTL register */
1237         ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl,
1238                                                 drvdata->lpaif_map);
1239         if (ret) {
1240                 dev_err(dev, "error init i2sctl field: %d\n", ret);
1241                 return ret;
1242         }
1243
1244         if (drvdata->hdmi_port_enable) {
1245                 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map);
1246                 if (ret) {
1247                         dev_err(dev, "%s error  hdmi init failed\n", __func__);
1248                         return ret;
1249                 }
1250         }
1251         ret = devm_snd_soc_register_component(dev,
1252                                               &lpass_cpu_comp_driver,
1253                                               variant->dai_driver,
1254                                               variant->num_dai);
1255         if (ret) {
1256                 dev_err(dev, "error registering cpu driver: %d\n", ret);
1257                 goto err;
1258         }
1259
1260         ret = asoc_qcom_lpass_platform_register(pdev);
1261         if (ret) {
1262                 dev_err(dev, "error registering platform driver: %d\n", ret);
1263                 goto err;
1264         }
1265
1266 err:
1267         return ret;
1268 }
1269 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
1270
1271 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
1272 {
1273         struct lpass_data *drvdata = platform_get_drvdata(pdev);
1274
1275         if (drvdata->variant->exit)
1276                 drvdata->variant->exit(pdev);
1277
1278
1279         return 0;
1280 }
1281 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
1282
1283 void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev)
1284 {
1285         struct lpass_data *drvdata = platform_get_drvdata(pdev);
1286
1287         if (drvdata->variant->exit)
1288                 drvdata->variant->exit(pdev);
1289
1290 }
1291 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown);
1292
1293 MODULE_DESCRIPTION("QTi LPASS CPU Driver");
1294 MODULE_LICENSE("GPL v2");