sound/soc/qcom/lpass-cpu.c

   1 /*
   2  * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <linux/regmap.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dai.h>
  27 #include "lpass-lpaif-reg.h"
  28 #include "lpass.h"
  29
  30 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  31                 unsigned int freq, int dir)
  32 {
  33         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  34         int ret;
  35
  36         ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
  37         if (ret)
  38                 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
  39                         freq, ret);
  40
  41         return ret;
  42 }
  43
  44 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
  45                 struct snd_soc_dai *dai)
  46 {
  47         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  48         int ret;
  49
  50         ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
  51         if (ret) {
  52                 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
  53                 return ret;
  54         }
  55
  56         ret = clk_prepare_enable(drvdata->mi2s_bit_clk[dai->driver->id]);
  57         if (ret) {
  58                 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
  59                 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
  60                 return ret;
  61         }
  62
  63         return 0;
  64 }
  65
  66 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
  67                 struct snd_soc_dai *dai)
  68 {
  69         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  70
  71         clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
  72
  73         clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
  74 }
  75
  76 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
  77                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  78 {
  79         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  80         snd_pcm_format_t format = params_format(params);
  81         unsigned int channels = params_channels(params);
  82         unsigned int rate = params_rate(params);
  83         unsigned int regval;
  84         int bitwidth, ret;
  85
  86         bitwidth = snd_pcm_format_width(format);
  87         if (bitwidth < 0) {
  88                 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
  89                 return bitwidth;
  90         }
  91
  92         regval = LPAIF_I2SCTL_LOOPBACK_DISABLE |
  93                         LPAIF_I2SCTL_WSSRC_INTERNAL;
  94
  95         switch (bitwidth) {
  96         case 16:
  97                 regval |= LPAIF_I2SCTL_BITWIDTH_16;
  98                 break;
  99         case 24:
 100                 regval |= LPAIF_I2SCTL_BITWIDTH_24;
 101                 break;
 102         case 32:
 103                 regval |= LPAIF_I2SCTL_BITWIDTH_32;
 104                 break;
 105         default:
 106                 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
 107                 return -EINVAL;
 108         }
 109
 110         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 111                 switch (channels) {
 112                 case 1:
 113                         regval |= LPAIF_I2SCTL_SPKMODE_SD0;
 114                         regval |= LPAIF_I2SCTL_SPKMONO_MONO;
 115                         break;
 116                 case 2:
 117                         regval |= LPAIF_I2SCTL_SPKMODE_SD0;
 118                         regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
 119                         break;
 120                 case 4:
 121                         regval |= LPAIF_I2SCTL_SPKMODE_QUAD01;
 122                         regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
 123                         break;
 124                 case 6:
 125                         regval |= LPAIF_I2SCTL_SPKMODE_6CH;
 126                         regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
 127                         break;
 128                 case 8:
 129                         regval |= LPAIF_I2SCTL_SPKMODE_8CH;
 130                         regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
 131                         break;
 132                 default:
 133                         dev_err(dai->dev, "invalid channels given: %u\n",
 134                                 channels);
 135                         return -EINVAL;
 136                 }
 137         } else {
 138                 switch (channels) {
 139                 case 1:
 140                         regval |= LPAIF_I2SCTL_MICMODE_SD0;
 141                         regval |= LPAIF_I2SCTL_MICMONO_MONO;
 142                         break;
 143                 case 2:
 144                         regval |= LPAIF_I2SCTL_MICMODE_SD0;
 145                         regval |= LPAIF_I2SCTL_MICMONO_STEREO;
 146                         break;
 147                 case 4:
 148                         regval |= LPAIF_I2SCTL_MICMODE_QUAD01;
 149                         regval |= LPAIF_I2SCTL_MICMONO_STEREO;
 150                         break;
 151                 case 6:
 152                         regval |= LPAIF_I2SCTL_MICMODE_6CH;
 153                         regval |= LPAIF_I2SCTL_MICMONO_STEREO;
 154                         break;
 155                 case 8:
 156                         regval |= LPAIF_I2SCTL_MICMODE_8CH;
 157                         regval |= LPAIF_I2SCTL_MICMONO_STEREO;
 158                         break;
 159                 default:
 160                         dev_err(dai->dev, "invalid channels given: %u\n",
 161                                 channels);
 162                         return -EINVAL;
 163                 }
 164         }
 165
 166         ret = regmap_write(drvdata->lpaif_map,
 167                            LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
 168                            regval);
 169         if (ret) {
 170                 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
 171                 return ret;
 172         }
 173
 174         ret = clk_set_rate(drvdata->mi2s_bit_clk[dai->driver->id],
 175                            rate * bitwidth * 2);
 176         if (ret) {
 177                 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
 178                         rate * bitwidth * 2, ret);
 179                 return ret;
 180         }
 181
 182         return 0;
 183 }
 184
 185 static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
 186                 struct snd_soc_dai *dai)
 187 {
 188         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 189         int ret;
 190         unsigned int val, mask;
 191
 192         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 193                 val = LPAIF_I2SCTL_SPKEN_ENABLE;
 194                 mask = LPAIF_I2SCTL_SPKEN_MASK;
 195         } else  {
 196                 val = LPAIF_I2SCTL_MICEN_ENABLE;
 197                 mask = LPAIF_I2SCTL_MICEN_MASK;
 198         }
 199
 200         ret = regmap_update_bits(drvdata->lpaif_map,
 201                         LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
 202                         mask, val);
 203         if (ret)
 204                 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
 205
 206         return ret;
 207 }
 208
 209 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
 210                 int cmd, struct snd_soc_dai *dai)
 211 {
 212         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 213         int ret = -EINVAL;
 214         unsigned int val, mask;
 215
 216         switch (cmd) {
 217         case SNDRV_PCM_TRIGGER_START:
 218         case SNDRV_PCM_TRIGGER_RESUME:
 219         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 220                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 221                         val = LPAIF_I2SCTL_SPKEN_ENABLE;
 222                         mask = LPAIF_I2SCTL_SPKEN_MASK;
 223                 } else  {
 224                         val = LPAIF_I2SCTL_MICEN_ENABLE;
 225                         mask = LPAIF_I2SCTL_MICEN_MASK;
 226                 }
 227
 228                 ret = regmap_update_bits(drvdata->lpaif_map,
 229                                 LPAIF_I2SCTL_REG(drvdata->variant,
 230                                                 dai->driver->id),
 231                                 mask, val);
 232                 if (ret)
 233                         dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
 234                                 ret);
 235                 break;
 236         case SNDRV_PCM_TRIGGER_STOP:
 237         case SNDRV_PCM_TRIGGER_SUSPEND:
 238         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 239                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 240                         val = LPAIF_I2SCTL_SPKEN_DISABLE;
 241                         mask = LPAIF_I2SCTL_SPKEN_MASK;
 242                 } else  {
 243                         val = LPAIF_I2SCTL_MICEN_DISABLE;
 244                         mask = LPAIF_I2SCTL_MICEN_MASK;
 245                 }
 246
 247                 ret = regmap_update_bits(drvdata->lpaif_map,
 248                                 LPAIF_I2SCTL_REG(drvdata->variant,
 249                                                 dai->driver->id),
 250                                 mask, val);
 251                 if (ret)
 252                         dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
 253                                 ret);
 254                 break;
 255         }
 256
 257         return ret;
 258 }
 259
 260 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
 261         .set_sysclk     = lpass_cpu_daiops_set_sysclk,
 262         .startup        = lpass_cpu_daiops_startup,
 263         .shutdown       = lpass_cpu_daiops_shutdown,
 264         .hw_params      = lpass_cpu_daiops_hw_params,
 265         .prepare        = lpass_cpu_daiops_prepare,
 266         .trigger        = lpass_cpu_daiops_trigger,
 267 };
 268 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
 269
 270 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
 271 {
 272         struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 273         int ret;
 274
 275         /* ensure audio hardware is disabled */
 276         ret = regmap_write(drvdata->lpaif_map,
 277                         LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
 278         if (ret)
 279                 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
 280
 281         return ret;
 282 }
 283 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
 284
 285 static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
 286         .name = "lpass-cpu",
 287 };
 288
 289 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
 290 {
 291         struct lpass_data *drvdata = dev_get_drvdata(dev);
 292         struct lpass_variant *v = drvdata->variant;
 293         int i;
 294
 295         for (i = 0; i < v->i2s_ports; ++i)
 296                 if (reg == LPAIF_I2SCTL_REG(v, i))
 297                         return true;
 298
 299         for (i = 0; i < v->irq_ports; ++i) {
 300                 if (reg == LPAIF_IRQEN_REG(v, i))
 301                         return true;
 302                 if (reg == LPAIF_IRQCLEAR_REG(v, i))
 303                         return true;
 304         }
 305
 306         for (i = 0; i < v->rdma_channels; ++i) {
 307                 if (reg == LPAIF_RDMACTL_REG(v, i))
 308                         return true;
 309                 if (reg == LPAIF_RDMABASE_REG(v, i))
 310                         return true;
 311                 if (reg == LPAIF_RDMABUFF_REG(v, i))
 312                         return true;
 313                 if (reg == LPAIF_RDMAPER_REG(v, i))
 314                         return true;
 315         }
 316
 317         for (i = 0; i < v->wrdma_channels; ++i) {
 318                 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
 319                         return true;
 320                 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
 321                         return true;
 322                 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
 323                         return true;
 324                 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
 325                         return true;
 326         }
 327
 328         return false;
 329 }
 330
 331 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
 332 {
 333         struct lpass_data *drvdata = dev_get_drvdata(dev);
 334         struct lpass_variant *v = drvdata->variant;
 335         int i;
 336
 337         for (i = 0; i < v->i2s_ports; ++i)
 338                 if (reg == LPAIF_I2SCTL_REG(v, i))
 339                         return true;
 340
 341         for (i = 0; i < v->irq_ports; ++i) {
 342                 if (reg == LPAIF_IRQEN_REG(v, i))
 343                         return true;
 344                 if (reg == LPAIF_IRQSTAT_REG(v, i))
 345                         return true;
 346         }
 347
 348         for (i = 0; i < v->rdma_channels; ++i) {
 349                 if (reg == LPAIF_RDMACTL_REG(v, i))
 350                         return true;
 351                 if (reg == LPAIF_RDMABASE_REG(v, i))
 352                         return true;
 353                 if (reg == LPAIF_RDMABUFF_REG(v, i))
 354                         return true;
 355                 if (reg == LPAIF_RDMACURR_REG(v, i))
 356                         return true;
 357                 if (reg == LPAIF_RDMAPER_REG(v, i))
 358                         return true;
 359         }
 360
 361         for (i = 0; i < v->wrdma_channels; ++i) {
 362                 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
 363                         return true;
 364                 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
 365                         return true;
 366                 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
 367                         return true;
 368                 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
 369                         return true;
 370                 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
 371                         return true;
 372         }
 373
 374         return false;
 375 }
 376
 377 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
 378 {
 379         struct lpass_data *drvdata = dev_get_drvdata(dev);
 380         struct lpass_variant *v = drvdata->variant;
 381         int i;
 382
 383         for (i = 0; i < v->irq_ports; ++i)
 384                 if (reg == LPAIF_IRQSTAT_REG(v, i))
 385                         return true;
 386
 387         for (i = 0; i < v->rdma_channels; ++i)
 388                 if (reg == LPAIF_RDMACURR_REG(v, i))
 389                         return true;
 390
 391         for (i = 0; i < v->wrdma_channels; ++i)
 392                 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
 393                         return true;
 394
 395         return false;
 396 }
 397
 398 static struct regmap_config lpass_cpu_regmap_config = {
 399         .reg_bits = 32,
 400         .reg_stride = 4,
 401         .val_bits = 32,
 402         .writeable_reg = lpass_cpu_regmap_writeable,
 403         .readable_reg = lpass_cpu_regmap_readable,
 404         .volatile_reg = lpass_cpu_regmap_volatile,
 405         .cache_type = REGCACHE_FLAT,
 406 };
 407
 408 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
 409 {
 410         struct lpass_data *drvdata;
 411         struct device_node *dsp_of_node;
 412         struct resource *res;
 413         struct lpass_variant *variant;
 414         struct device *dev = &pdev->dev;
 415         const struct of_device_id *match;
 416         int ret, i, dai_id;
 417
 418         dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
 419         if (dsp_of_node) {
 420                 dev_err(&pdev->dev, "DSP exists and holds audio resources\n");
 421                 return -EBUSY;
 422         }
 423
 424         drvdata = devm_kzalloc(&pdev->dev, sizeof(struct lpass_data),
 425                         GFP_KERNEL);
 426         if (!drvdata)
 427                 return -ENOMEM;
 428         platform_set_drvdata(pdev, drvdata);
 429
 430         match = of_match_device(dev->driver->of_match_table, dev);
 431         if (!match || !match->data)
 432                 return -EINVAL;
 433
 434         drvdata->variant = (struct lpass_variant *)match->data;
 435         variant = drvdata->variant;
 436
 437         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");
 438
 439         drvdata->lpaif = devm_ioremap_resource(&pdev->dev, res);
 440         if (IS_ERR((void const __force *)drvdata->lpaif)) {
 441                 dev_err(&pdev->dev, "error mapping reg resource: %ld\n",
 442                                 PTR_ERR((void const __force *)drvdata->lpaif));
 443                 return PTR_ERR((void const __force *)drvdata->lpaif);
 444         }
 445
 446         lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
 447                                                 variant->wrdma_channels +
 448                                                 variant->wrdma_channel_start);
 449
 450         drvdata->lpaif_map = devm_regmap_init_mmio(&pdev->dev, drvdata->lpaif,
 451                         &lpass_cpu_regmap_config);
 452         if (IS_ERR(drvdata->lpaif_map)) {
 453                 dev_err(&pdev->dev, "error initializing regmap: %ld\n",
 454                         PTR_ERR(drvdata->lpaif_map));
 455                 return PTR_ERR(drvdata->lpaif_map);
 456         }
 457
 458         if (variant->init)
 459                 variant->init(pdev);
 460
 461         for (i = 0; i < variant->num_dai; i++) {
 462                 dai_id = variant->dai_driver[i].id;
 463                 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(&pdev->dev,
 464                                              variant->dai_osr_clk_names[i]);
 465                 if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) {
 466                         dev_warn(&pdev->dev,
 467                                 "%s() error getting optional %s: %ld\n",
 468                                 __func__,
 469                                 variant->dai_osr_clk_names[i],
 470                                 PTR_ERR(drvdata->mi2s_osr_clk[dai_id]));
 471
 472                         drvdata->mi2s_osr_clk[dai_id] = NULL;
 473                 }
 474
 475                 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(&pdev->dev,
 476                                                 variant->dai_bit_clk_names[i]);
 477                 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
 478                         dev_err(&pdev->dev,
 479                                 "error getting %s: %ld\n",
 480                                 variant->dai_bit_clk_names[i],
 481                                 PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
 482                         return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
 483                 }
 484         }
 485
 486         drvdata->ahbix_clk = devm_clk_get(&pdev->dev, "ahbix-clk");
 487         if (IS_ERR(drvdata->ahbix_clk)) {
 488                 dev_err(&pdev->dev, "error getting ahbix-clk: %ld\n",
 489                         PTR_ERR(drvdata->ahbix_clk));
 490                 return PTR_ERR(drvdata->ahbix_clk);
 491         }
 492
 493         ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
 494         if (ret) {
 495                 dev_err(&pdev->dev, "error setting rate on ahbix_clk: %d\n",
 496                         ret);
 497                 return ret;
 498         }
 499         dev_dbg(&pdev->dev, "set ahbix_clk rate to %lu\n",
 500                 clk_get_rate(drvdata->ahbix_clk));
 501
 502         ret = clk_prepare_enable(drvdata->ahbix_clk);
 503         if (ret) {
 504                 dev_err(&pdev->dev, "error enabling ahbix_clk: %d\n", ret);
 505                 return ret;
 506         }
 507
 508         ret = devm_snd_soc_register_component(&pdev->dev,
 509                                               &lpass_cpu_comp_driver,
 510                                               variant->dai_driver,
 511                                               variant->num_dai);
 512         if (ret) {
 513                 dev_err(&pdev->dev, "error registering cpu driver: %d\n", ret);
 514                 goto err_clk;
 515         }
 516
 517         ret = asoc_qcom_lpass_platform_register(pdev);
 518         if (ret) {
 519                 dev_err(&pdev->dev, "error registering platform driver: %d\n",
 520                         ret);
 521                 goto err_clk;
 522         }
 523
 524         return 0;
 525
 526 err_clk:
 527         clk_disable_unprepare(drvdata->ahbix_clk);
 528         return ret;
 529 }
 530 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
 531
 532 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
 533 {
 534         struct lpass_data *drvdata = platform_get_drvdata(pdev);
 535
 536         if (drvdata->variant->exit)
 537                 drvdata->variant->exit(pdev);
 538
 539         clk_disable_unprepare(drvdata->ahbix_clk);
 540
 541         return 0;
 542 }
 543 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
 544
 545 MODULE_DESCRIPTION("QTi LPASS CPU Driver");
 546 MODULE_LICENSE("GPL v2");