sound/soc/omap/omap-mcpdm.c

   1 /*
   2  * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
   3  *
   4  * Copyright (C) 2009 - 2011 Texas Instruments
   5  *
   6  * Author: Misael Lopez Cruz <misael.lopez@ti.com>
   7  * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
   8  *          Margarita Olaya <magi.olaya@ti.com>
   9  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * version 2 as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23  * 02110-1301 USA
  24  *
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33 #include <linux/irq.h>
  34 #include <linux/slab.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/of_device.h>
  37
  38 #include <sound/core.h>
  39 #include <sound/pcm.h>
  40 #include <sound/pcm_params.h>
  41 #include <sound/soc.h>
  42 #include <sound/dmaengine_pcm.h>
  43 #include <sound/omap-pcm.h>
  44
  45 #include "omap-mcpdm.h"
  46
  47 struct mcpdm_link_config {
  48         u32 link_mask; /* channel mask for the direction */
  49         u32 threshold; /* FIFO threshold */
  50 };
  51
  52 struct omap_mcpdm {
  53         struct device *dev;
  54         unsigned long phys_base;
  55         void __iomem *io_base;
  56         int irq;
  57         struct pm_qos_request pm_qos_req;
  58         int latency[2];
  59
  60         struct mutex mutex;
  61
  62         /* Playback/Capture configuration */
  63         struct mcpdm_link_config config[2];
  64
  65         /* McPDM dn offsets for rx1, and 2 channels */
  66         u32 dn_rx_offset;
  67
  68         /* McPDM needs to be restarted due to runtime reconfiguration */
  69         bool restart;
  70
  71         struct snd_dmaengine_dai_dma_data dma_data[2];
  72 };
  73
  74 /*
  75  * Stream DMA parameters
  76  */
  77
  78 static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
  79 {
  80         writel_relaxed(val, mcpdm->io_base + reg);
  81 }
  82
  83 static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
  84 {
  85         return readl_relaxed(mcpdm->io_base + reg);
  86 }
  87
  88 #ifdef DEBUG
  89 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
  90 {
  91         dev_dbg(mcpdm->dev, "***********************\n");
  92         dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
  93                         omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
  94         dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
  95                         omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
  96         dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
  97                         omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
  98         dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
  99                         omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
 100         dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
 101                         omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
 102         dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
 103                         omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
 104         dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
 105                         omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
 106         dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
 107                         omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
 108         dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
 109                         omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
 110         dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
 111                         omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
 112         dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
 113                         omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
 114         dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
 115                         omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
 116         dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
 117                         omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
 118         dev_dbg(mcpdm->dev, "***********************\n");
 119 }
 120 #else
 121 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
 122 #endif
 123
 124 /*
 125  * Enables the transfer through the PDM interface to/from the Phoenix
 126  * codec by enabling the corresponding UP or DN channels.
 127  */
 128 static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
 129 {
 130         u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
 131         u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
 132
 133         ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
 134         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 135
 136         ctrl |= link_mask;
 137         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 138
 139         ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
 140         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 141 }
 142
 143 /*
 144  * Disables the transfer through the PDM interface to/from the Phoenix
 145  * codec by disabling the corresponding UP or DN channels.
 146  */
 147 static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
 148 {
 149         u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
 150         u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;
 151
 152         ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
 153         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 154
 155         ctrl &= ~(link_mask);
 156         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 157
 158         ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
 159         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 160
 161 }
 162
 163 /*
 164  * Is the physical McPDM interface active.
 165  */
 166 static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
 167 {
 168         return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
 169                                         (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
 170 }
 171
 172 /*
 173  * Configures McPDM uplink, and downlink for audio.
 174  * This function should be called before omap_mcpdm_start.
 175  */
 176 static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
 177 {
 178         omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
 179                         MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
 180                         MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
 181
 182         /* Enable DN RX1/2 offset cancellation feature, if configured */
 183         if (mcpdm->dn_rx_offset) {
 184                 u32 dn_offset = mcpdm->dn_rx_offset;
 185
 186                 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
 187                 dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
 188                 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
 189         }
 190
 191         omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
 192                          mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
 193         omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
 194                          mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
 195
 196         omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
 197                         MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
 198 }
 199
 200 /*
 201  * Cleans McPDM uplink, and downlink configuration.
 202  * This function should be called when the stream is closed.
 203  */
 204 static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
 205 {
 206         /* Disable irq request generation for downlink */
 207         omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
 208                         MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
 209
 210         /* Disable DMA request generation for downlink */
 211         omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
 212
 213         /* Disable irq request generation for uplink */
 214         omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
 215                         MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
 216
 217         /* Disable DMA request generation for uplink */
 218         omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
 219
 220         /* Disable RX1/2 offset cancellation */
 221         if (mcpdm->dn_rx_offset)
 222                 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
 223 }
 224
 225 static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
 226 {
 227         struct omap_mcpdm *mcpdm = dev_id;
 228         int irq_status;
 229
 230         irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
 231
 232         /* Acknowledge irq event */
 233         omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
 234
 235         if (irq_status & MCPDM_DN_IRQ_FULL)
 236                 dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
 237
 238         if (irq_status & MCPDM_DN_IRQ_EMPTY)
 239                 dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
 240
 241         if (irq_status & MCPDM_DN_IRQ)
 242                 dev_dbg(mcpdm->dev, "DN (playback) write request\n");
 243
 244         if (irq_status & MCPDM_UP_IRQ_FULL)
 245                 dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
 246
 247         if (irq_status & MCPDM_UP_IRQ_EMPTY)
 248                 dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
 249
 250         if (irq_status & MCPDM_UP_IRQ)
 251                 dev_dbg(mcpdm->dev, "UP (capture) write request\n");
 252
 253         return IRQ_HANDLED;
 254 }
 255
 256 static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
 257                                   struct snd_soc_dai *dai)
 258 {
 259         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 260
 261         mutex_lock(&mcpdm->mutex);
 262
 263         if (!dai->active) {
 264                 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
 265
 266                 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
 267                 omap_mcpdm_open_streams(mcpdm);
 268         }
 269         mutex_unlock(&mcpdm->mutex);
 270
 271         return 0;
 272 }
 273
 274 static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
 275                                   struct snd_soc_dai *dai)
 276 {
 277         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 278         int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 279         int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
 280         int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
 281
 282         mutex_lock(&mcpdm->mutex);
 283
 284         if (!dai->active) {
 285                 if (omap_mcpdm_active(mcpdm)) {
 286                         omap_mcpdm_stop(mcpdm);
 287                         omap_mcpdm_close_streams(mcpdm);
 288                         mcpdm->config[0].link_mask = 0;
 289                         mcpdm->config[1].link_mask = 0;
 290                 }
 291         }
 292
 293         if (mcpdm->latency[stream2])
 294                 pm_qos_update_request(&mcpdm->pm_qos_req,
 295                                       mcpdm->latency[stream2]);
 296         else if (mcpdm->latency[stream1])
 297                 pm_qos_remove_request(&mcpdm->pm_qos_req);
 298
 299         mcpdm->latency[stream1] = 0;
 300
 301         mutex_unlock(&mcpdm->mutex);
 302 }
 303
 304 static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
 305                                     struct snd_pcm_hw_params *params,
 306                                     struct snd_soc_dai *dai)
 307 {
 308         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 309         int stream = substream->stream;
 310         struct snd_dmaengine_dai_dma_data *dma_data;
 311         u32 threshold;
 312         int channels, latency;
 313         int link_mask = 0;
 314
 315         channels = params_channels(params);
 316         switch (channels) {
 317         case 5:
 318                 if (stream == SNDRV_PCM_STREAM_CAPTURE)
 319                         /* up to 3 channels for capture */
 320                         return -EINVAL;
 321                 link_mask |= 1 << 4;
 322         case 4:
 323                 if (stream == SNDRV_PCM_STREAM_CAPTURE)
 324                         /* up to 3 channels for capture */
 325                         return -EINVAL;
 326                 link_mask |= 1 << 3;
 327         case 3:
 328                 link_mask |= 1 << 2;
 329         case 2:
 330                 link_mask |= 1 << 1;
 331         case 1:
 332                 link_mask |= 1 << 0;
 333                 break;
 334         default:
 335                 /* unsupported number of channels */
 336                 return -EINVAL;
 337         }
 338
 339         dma_data = snd_soc_dai_get_dma_data(dai, substream);
 340
 341         threshold = mcpdm->config[stream].threshold;
 342         /* Configure McPDM channels, and DMA packet size */
 343         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 344                 link_mask <<= 3;
 345
 346                 /* If capture is not running assume a stereo stream to come */
 347                 if (!mcpdm->config[!stream].link_mask)
 348                         mcpdm->config[!stream].link_mask = 0x3;
 349
 350                 dma_data->maxburst =
 351                                 (MCPDM_DN_THRES_MAX - threshold) * channels;
 352                 latency = threshold;
 353         } else {
 354                 /* If playback is not running assume a stereo stream to come */
 355                 if (!mcpdm->config[!stream].link_mask)
 356                         mcpdm->config[!stream].link_mask = (0x3 << 3);
 357
 358                 dma_data->maxburst = threshold * channels;
 359                 latency = (MCPDM_DN_THRES_MAX - threshold);
 360         }
 361
 362         /*
 363          * The DMA must act to a DMA request within latency time (usec) to avoid
 364          * under/overflow
 365          */
 366         mcpdm->latency[stream] = latency * USEC_PER_SEC / params_rate(params);
 367
 368         if (!mcpdm->latency[stream])
 369                 mcpdm->latency[stream] = 10;
 370
 371         /* Check if we need to restart McPDM with this stream */
 372         if (mcpdm->config[stream].link_mask &&
 373             mcpdm->config[stream].link_mask != link_mask)
 374                 mcpdm->restart = true;
 375
 376         mcpdm->config[stream].link_mask = link_mask;
 377
 378         return 0;
 379 }
 380
 381 static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
 382                                   struct snd_soc_dai *dai)
 383 {
 384         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 385         struct pm_qos_request *pm_qos_req = &mcpdm->pm_qos_req;
 386         int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 387         int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
 388         int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
 389         int latency = mcpdm->latency[stream2];
 390
 391         /* Prevent omap hardware from hitting off between FIFO fills */
 392         if (!latency || mcpdm->latency[stream1] < latency)
 393                 latency = mcpdm->latency[stream1];
 394
 395         if (pm_qos_request_active(pm_qos_req))
 396                 pm_qos_update_request(pm_qos_req, latency);
 397         else if (latency)
 398                 pm_qos_add_request(pm_qos_req, PM_QOS_CPU_DMA_LATENCY, latency);
 399
 400         if (!omap_mcpdm_active(mcpdm)) {
 401                 omap_mcpdm_start(mcpdm);
 402                 omap_mcpdm_reg_dump(mcpdm);
 403         } else if (mcpdm->restart) {
 404                 omap_mcpdm_stop(mcpdm);
 405                 omap_mcpdm_start(mcpdm);
 406                 mcpdm->restart = false;
 407                 omap_mcpdm_reg_dump(mcpdm);
 408         }
 409
 410         return 0;
 411 }
 412
 413 static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
 414         .startup        = omap_mcpdm_dai_startup,
 415         .shutdown       = omap_mcpdm_dai_shutdown,
 416         .hw_params      = omap_mcpdm_dai_hw_params,
 417         .prepare        = omap_mcpdm_prepare,
 418 };
 419
 420 static int omap_mcpdm_probe(struct snd_soc_dai *dai)
 421 {
 422         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 423         int ret;
 424
 425         pm_runtime_enable(mcpdm->dev);
 426
 427         /* Disable lines while request is ongoing */
 428         pm_runtime_get_sync(mcpdm->dev);
 429         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
 430
 431         ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler, 0, "McPDM",
 432                           (void *)mcpdm);
 433
 434         pm_runtime_put_sync(mcpdm->dev);
 435
 436         if (ret) {
 437                 dev_err(mcpdm->dev, "Request for IRQ failed\n");
 438                 pm_runtime_disable(mcpdm->dev);
 439         }
 440
 441         /* Configure McPDM threshold values */
 442         mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
 443         mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
 444                                                         MCPDM_UP_THRES_MAX - 3;
 445
 446         snd_soc_dai_init_dma_data(dai,
 447                                   &mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
 448                                   &mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
 449
 450         return ret;
 451 }
 452
 453 static int omap_mcpdm_remove(struct snd_soc_dai *dai)
 454 {
 455         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 456
 457         free_irq(mcpdm->irq, (void *)mcpdm);
 458         pm_runtime_disable(mcpdm->dev);
 459
 460         if (pm_qos_request_active(&mcpdm->pm_qos_req))
 461                 pm_qos_remove_request(&mcpdm->pm_qos_req);
 462
 463         return 0;
 464 }
 465
 466 #define OMAP_MCPDM_RATES        (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
 467 #define OMAP_MCPDM_FORMATS      SNDRV_PCM_FMTBIT_S32_LE
 468
 469 static struct snd_soc_dai_driver omap_mcpdm_dai = {
 470         .probe = omap_mcpdm_probe,
 471         .remove = omap_mcpdm_remove,
 472         .probe_order = SND_SOC_COMP_ORDER_LATE,
 473         .remove_order = SND_SOC_COMP_ORDER_EARLY,
 474         .playback = {
 475                 .channels_min = 1,
 476                 .channels_max = 5,
 477                 .rates = OMAP_MCPDM_RATES,
 478                 .formats = OMAP_MCPDM_FORMATS,
 479                 .sig_bits = 24,
 480         },
 481         .capture = {
 482                 .channels_min = 1,
 483                 .channels_max = 3,
 484                 .rates = OMAP_MCPDM_RATES,
 485                 .formats = OMAP_MCPDM_FORMATS,
 486                 .sig_bits = 24,
 487         },
 488         .ops = &omap_mcpdm_dai_ops,
 489 };
 490
 491 static const struct snd_soc_component_driver omap_mcpdm_component = {
 492         .name           = "omap-mcpdm",
 493 };
 494
 495 void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
 496                                     u8 rx1, u8 rx2)
 497 {
 498         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
 499
 500         mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
 501 }
 502 EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
 503
 504 static int asoc_mcpdm_probe(struct platform_device *pdev)
 505 {
 506         struct omap_mcpdm *mcpdm;
 507         struct resource *res;
 508         int ret;
 509
 510         mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
 511         if (!mcpdm)
 512                 return -ENOMEM;
 513
 514         platform_set_drvdata(pdev, mcpdm);
 515
 516         mutex_init(&mcpdm->mutex);
 517
 518         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
 519         if (res == NULL)
 520                 return -ENOMEM;
 521
 522         mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
 523         mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
 524
 525         mcpdm->dma_data[0].filter_data = "dn_link";
 526         mcpdm->dma_data[1].filter_data = "up_link";
 527
 528         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
 529         mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
 530         if (IS_ERR(mcpdm->io_base))
 531                 return PTR_ERR(mcpdm->io_base);
 532
 533         mcpdm->irq = platform_get_irq(pdev, 0);
 534         if (mcpdm->irq < 0)
 535                 return mcpdm->irq;
 536
 537         mcpdm->dev = &pdev->dev;
 538
 539         ret =  devm_snd_soc_register_component(&pdev->dev,
 540                                                &omap_mcpdm_component,
 541                                                &omap_mcpdm_dai, 1);
 542         if (ret)
 543                 return ret;
 544
 545         return omap_pcm_platform_register(&pdev->dev);
 546 }
 547
 548 static const struct of_device_id omap_mcpdm_of_match[] = {
 549         { .compatible = "ti,omap4-mcpdm", },
 550         { }
 551 };
 552 MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
 553
 554 static struct platform_driver asoc_mcpdm_driver = {
 555         .driver = {
 556                 .name   = "omap-mcpdm",
 557                 .of_match_table = omap_mcpdm_of_match,
 558         },
 559
 560         .probe  = asoc_mcpdm_probe,
 561 };
 562
 563 module_platform_driver(asoc_mcpdm_driver);
 564
 565 MODULE_ALIAS("platform:omap-mcpdm");
 566 MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
 567 MODULE_DESCRIPTION("OMAP PDM SoC Interface");
 568 MODULE_LICENSE("GPL");