2 * omap-dmic.c -- OMAP ASoC DMIC DAI driver
4 * Copyright (C) 2010 - 2011 Texas Instruments
6 * Author: David Lambert <dlambert@ti.com>
7 * Misael Lopez Cruz <misael.lopez@ti.com>
8 * Liam Girdwood <lrg@ti.com>
9 * Peter Ujfalusi <peter.ujfalusi@ti.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/err.h>
31 #include <linux/clk.h>
33 #include <linux/slab.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/of_device.h>
37 #include <sound/core.h>
38 #include <sound/pcm.h>
39 #include <sound/pcm_params.h>
40 #include <sound/initval.h>
41 #include <sound/soc.h>
42 #include <sound/dmaengine_pcm.h>
43 #include <sound/omap-pcm.h>
45 #include "omap-dmic.h"
49 void __iomem *io_base;
51 struct pm_qos_request pm_qos_req;
62 struct snd_dmaengine_dai_dma_data dma_data;
65 static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
67 writel_relaxed(val, dmic->io_base + reg);
70 static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
72 return readl_relaxed(dmic->io_base + reg);
75 static inline void omap_dmic_start(struct omap_dmic *dmic)
77 u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
79 /* Configure DMA controller */
80 omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
81 OMAP_DMIC_DMA_ENABLE);
83 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
86 static inline void omap_dmic_stop(struct omap_dmic *dmic)
88 u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
89 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
90 ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
92 /* Disable DMA request generation */
93 omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
94 OMAP_DMIC_DMA_ENABLE);
98 static inline int dmic_is_enabled(struct omap_dmic *dmic)
100 return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
101 OMAP_DMIC_UP_ENABLE_MASK;
104 static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
105 struct snd_soc_dai *dai)
107 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
110 mutex_lock(&dmic->mutex);
117 mutex_unlock(&dmic->mutex);
122 static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
123 struct snd_soc_dai *dai)
125 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
127 mutex_lock(&dmic->mutex);
129 pm_qos_remove_request(&dmic->pm_qos_req);
134 mutex_unlock(&dmic->mutex);
137 static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
139 int divider = -EINVAL;
142 * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
145 if (sample_rate == 192000) {
146 if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
147 divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
150 "invalid clock configuration for 192KHz\n");
155 switch (dmic->out_freq) {
157 if (dmic->fclk_freq != 24576000)
159 divider = 0x4; /* Divider: 16 */
162 switch (dmic->fclk_freq) {
164 divider = 0x5; /* Divider: 5 */
167 divider = 0x0; /* Divider: 8 */
170 divider = 0x2; /* Divider: 10 */
177 if (dmic->fclk_freq != 24576000)
179 divider = 0x3; /* Divider: 8 */
182 if (dmic->fclk_freq != 19200000)
184 divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
187 dev_err(dmic->dev, "invalid out frequency: %dHz\n",
195 dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
196 dmic->out_freq, dmic->fclk_freq);
200 static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
201 struct snd_pcm_hw_params *params,
202 struct snd_soc_dai *dai)
204 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
205 struct snd_dmaengine_dai_dma_data *dma_data;
208 dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
209 if (dmic->clk_div < 0) {
210 dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
211 dmic->out_freq, dmic->fclk_freq);
215 dmic->ch_enabled = 0;
216 channels = params_channels(params);
219 dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
221 dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
223 dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
226 dev_err(dmic->dev, "invalid number of legacy channels\n");
230 /* packet size is threshold * channels */
231 dma_data = snd_soc_dai_get_dma_data(dai, substream);
232 dma_data->maxburst = dmic->threshold * channels;
233 dmic->latency = (OMAP_DMIC_THRES_MAX - dmic->threshold) * USEC_PER_SEC /
239 static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
240 struct snd_soc_dai *dai)
242 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
245 if (pm_qos_request_active(&dmic->pm_qos_req))
246 pm_qos_update_request(&dmic->pm_qos_req, dmic->latency);
248 /* Configure uplink threshold */
249 omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
251 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
253 /* Set dmic out format */
254 ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
255 ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
256 OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
258 /* Configure dmic clock divider */
259 ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
260 ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
262 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
264 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
265 ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
266 OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
271 static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
272 int cmd, struct snd_soc_dai *dai)
274 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
277 case SNDRV_PCM_TRIGGER_START:
278 omap_dmic_start(dmic);
280 case SNDRV_PCM_TRIGGER_STOP:
281 omap_dmic_stop(dmic);
290 static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
293 struct clk *parent_clk;
294 char *parent_clk_name;
304 dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
309 if (dmic->sysclk == clk_id) {
310 dmic->fclk_freq = freq;
314 /* re-parent not allowed if a stream is ongoing */
315 if (dmic->active && dmic_is_enabled(dmic)) {
316 dev_err(dmic->dev, "can't re-parent when DMIC active\n");
321 case OMAP_DMIC_SYSCLK_PAD_CLKS:
322 parent_clk_name = "pad_clks_ck";
324 case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
325 parent_clk_name = "slimbus_clk";
327 case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
328 parent_clk_name = "dmic_sync_mux_ck";
331 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
335 parent_clk = clk_get(dmic->dev, parent_clk_name);
336 if (IS_ERR(parent_clk)) {
337 dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
341 mutex_lock(&dmic->mutex);
343 /* disable clock while reparenting */
344 pm_runtime_put_sync(dmic->dev);
345 ret = clk_set_parent(dmic->fclk, parent_clk);
346 pm_runtime_get_sync(dmic->dev);
348 ret = clk_set_parent(dmic->fclk, parent_clk);
350 mutex_unlock(&dmic->mutex);
353 dev_err(dmic->dev, "re-parent failed\n");
357 dmic->sysclk = clk_id;
358 dmic->fclk_freq = freq;
366 static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
371 if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
372 dev_err(dmic->dev, "output clk_id (%d) not supported\n",
382 dmic->out_freq = freq;
385 dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
393 static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
394 unsigned int freq, int dir)
396 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
398 if (dir == SND_SOC_CLOCK_IN)
399 return omap_dmic_select_fclk(dmic, clk_id, freq);
400 else if (dir == SND_SOC_CLOCK_OUT)
401 return omap_dmic_select_outclk(dmic, clk_id, freq);
403 dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
407 static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
408 .startup = omap_dmic_dai_startup,
409 .shutdown = omap_dmic_dai_shutdown,
410 .hw_params = omap_dmic_dai_hw_params,
411 .prepare = omap_dmic_dai_prepare,
412 .trigger = omap_dmic_dai_trigger,
413 .set_sysclk = omap_dmic_set_dai_sysclk,
416 static int omap_dmic_probe(struct snd_soc_dai *dai)
418 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
420 pm_runtime_enable(dmic->dev);
422 /* Disable lines while request is ongoing */
423 pm_runtime_get_sync(dmic->dev);
424 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
425 pm_runtime_put_sync(dmic->dev);
427 /* Configure DMIC threshold value */
428 dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
430 snd_soc_dai_init_dma_data(dai, NULL, &dmic->dma_data);
435 static int omap_dmic_remove(struct snd_soc_dai *dai)
437 struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
439 pm_runtime_disable(dmic->dev);
444 static struct snd_soc_dai_driver omap_dmic_dai = {
446 .probe = omap_dmic_probe,
447 .remove = omap_dmic_remove,
451 .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
452 .formats = SNDRV_PCM_FMTBIT_S32_LE,
455 .ops = &omap_dmic_dai_ops,
458 static const struct snd_soc_component_driver omap_dmic_component = {
462 static int asoc_dmic_probe(struct platform_device *pdev)
464 struct omap_dmic *dmic;
465 struct resource *res;
468 dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
472 platform_set_drvdata(pdev, dmic);
473 dmic->dev = &pdev->dev;
474 dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
476 mutex_init(&dmic->mutex);
478 dmic->fclk = devm_clk_get(dmic->dev, "fck");
479 if (IS_ERR(dmic->fclk)) {
480 dev_err(dmic->dev, "cant get fck\n");
484 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
486 dev_err(dmic->dev, "invalid dma memory resource\n");
489 dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;
491 dmic->dma_data.filter_data = "up_link";
493 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
494 dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
495 if (IS_ERR(dmic->io_base))
496 return PTR_ERR(dmic->io_base);
499 ret = devm_snd_soc_register_component(&pdev->dev,
500 &omap_dmic_component,
505 ret = omap_pcm_platform_register(&pdev->dev);
512 static const struct of_device_id omap_dmic_of_match[] = {
513 { .compatible = "ti,omap4-dmic", },
516 MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
518 static struct platform_driver asoc_dmic_driver = {
521 .of_match_table = omap_dmic_of_match,
523 .probe = asoc_dmic_probe,
526 module_platform_driver(asoc_dmic_driver);
528 MODULE_ALIAS("platform:omap-dmic");
529 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
530 MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
531 MODULE_LICENSE("GPL");