1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011 Freescale Semiconductor, Inc.
6 #include <linux/module.h>
7 #include <linux/init.h>
9 #include <linux/platform_device.h>
10 #include <linux/slab.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/delay.h>
16 #include <linux/time.h>
17 #include <sound/core.h>
18 #include <sound/pcm.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
24 #define MXS_SET_ADDR 0x4
25 #define MXS_CLR_ADDR 0x8
27 static struct mxs_saif *mxs_saif[2];
30 * SAIF is a little different with other normal SOC DAIs on clock using.
32 * For MXS, two SAIF modules are instantiated on-chip.
33 * Each SAIF has a set of clock pins and can be operating in master
34 * mode simultaneously if they are connected to different off-chip codecs.
35 * Also, one of the two SAIFs can master or drive the clock pins while the
36 * other SAIF, in slave mode, receives clocking from the master SAIF.
37 * This also means that both SAIFs must operate at the same sample rate.
39 * We abstract this as each saif has a master, the master could be
40 * itself or other saifs. In the generic saif driver, saif does not need
41 * to know the different clkmux. Saif only needs to know who is its master
42 * and operating its master to generate the proper clock rate for it.
43 * The master id is provided in mach-specific layer according to different
47 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
48 int clk_id, unsigned int freq, int dir)
50 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
63 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
64 * is provided by other SAIF, we provide a interface here to get its master
66 * Note that the master could be itself.
68 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
70 return mxs_saif[saif->master_id];
74 * Set SAIF clock and MCLK
76 static int mxs_saif_set_clk(struct mxs_saif *saif,
82 struct mxs_saif *master_saif;
84 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
86 /* Set master saif to generate proper clock */
87 master_saif = mxs_saif_get_master(saif);
91 dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
93 /* Checking if can playback and capture simutaneously */
94 if (master_saif->ongoing && rate != master_saif->cur_rate) {
96 "can not change clock, master saif%d(rate %d) is ongoing\n",
97 master_saif->id, master_saif->cur_rate);
101 scr = __raw_readl(master_saif->base + SAIF_CTRL);
102 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
103 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
108 * The SAIF clock should be either 384*fs or 512*fs.
109 * If MCLK is used, the SAIF clk ratio needs to match mclk ratio.
110 * For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs.
111 * For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs.
113 * If MCLK is not used, we just set saif clk to 512*fs.
115 ret = clk_prepare_enable(master_saif->clk);
119 if (master_saif->mclk_in_use) {
120 switch (mclk / rate) {
126 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
127 ret = clk_set_rate(master_saif->clk, 512 * rate);
133 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
134 ret = clk_set_rate(master_saif->clk, 384 * rate);
137 /* SAIF MCLK should be a sub-rate of 512x or 384x */
138 clk_disable_unprepare(master_saif->clk);
142 ret = clk_set_rate(master_saif->clk, 512 * rate);
143 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
146 clk_disable_unprepare(master_saif->clk);
151 master_saif->cur_rate = rate;
153 if (!master_saif->mclk_in_use) {
154 __raw_writel(scr, master_saif->base + SAIF_CTRL);
159 * Program the over-sample rate for MCLK output
161 * The available MCLK range is 32x, 48x... 512x. The rate
162 * could be from 8kHz to 192kH.
164 switch (mclk / rate) {
166 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
169 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
172 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
175 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
178 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
181 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
184 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
187 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
190 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
196 __raw_writel(scr, master_saif->base + SAIF_CTRL);
202 * Put and disable MCLK.
204 int mxs_saif_put_mclk(unsigned int saif_id)
206 struct mxs_saif *saif = mxs_saif[saif_id];
212 stat = __raw_readl(saif->base + SAIF_STAT);
213 if (stat & BM_SAIF_STAT_BUSY) {
214 dev_err(saif->dev, "error: busy\n");
218 clk_disable_unprepare(saif->clk);
220 /* disable MCLK output */
221 __raw_writel(BM_SAIF_CTRL_CLKGATE,
222 saif->base + SAIF_CTRL + MXS_SET_ADDR);
223 __raw_writel(BM_SAIF_CTRL_RUN,
224 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
226 saif->mclk_in_use = 0;
229 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk);
232 * Get MCLK and set clock rate, then enable it
234 * This interface is used for codecs who are using MCLK provided
237 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
240 struct mxs_saif *saif = mxs_saif[saif_id];
243 struct mxs_saif *master_saif;
249 __raw_writel(BM_SAIF_CTRL_SFTRST,
250 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
252 /* FIXME: need clear clk gate for register r/w */
253 __raw_writel(BM_SAIF_CTRL_CLKGATE,
254 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
256 master_saif = mxs_saif_get_master(saif);
257 if (saif != master_saif) {
258 dev_err(saif->dev, "can not get mclk from a non-master saif\n");
262 stat = __raw_readl(saif->base + SAIF_STAT);
263 if (stat & BM_SAIF_STAT_BUSY) {
264 dev_err(saif->dev, "error: busy\n");
268 saif->mclk_in_use = 1;
269 ret = mxs_saif_set_clk(saif, mclk, rate);
273 ret = clk_prepare_enable(saif->clk);
277 /* enable MCLK output */
278 __raw_writel(BM_SAIF_CTRL_RUN,
279 saif->base + SAIF_CTRL + MXS_SET_ADDR);
283 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk);
286 * SAIF DAI format configuration.
287 * Should only be called when port is inactive.
289 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
293 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
295 stat = __raw_readl(saif->base + SAIF_STAT);
296 if (stat & BM_SAIF_STAT_BUSY) {
297 dev_err(cpu_dai->dev, "error: busy\n");
301 /* If SAIF1 is configured as slave, the clk gate needs to be cleared
302 * before the register can be written.
304 if (saif->id != saif->master_id) {
305 __raw_writel(BM_SAIF_CTRL_SFTRST,
306 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
307 __raw_writel(BM_SAIF_CTRL_CLKGATE,
308 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
311 scr0 = __raw_readl(saif->base + SAIF_CTRL);
312 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
313 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
317 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
318 case SND_SOC_DAIFMT_I2S:
319 /* data frame low 1clk before data */
320 scr |= BM_SAIF_CTRL_DELAY;
321 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
323 case SND_SOC_DAIFMT_LEFT_J:
324 /* data frame high with data */
325 scr &= ~BM_SAIF_CTRL_DELAY;
326 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
327 scr &= ~BM_SAIF_CTRL_JUSTIFY;
333 /* DAI clock inversion */
334 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
335 case SND_SOC_DAIFMT_IB_IF:
336 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
337 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
339 case SND_SOC_DAIFMT_IB_NF:
340 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
341 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
343 case SND_SOC_DAIFMT_NB_IF:
344 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
345 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
347 case SND_SOC_DAIFMT_NB_NF:
348 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
349 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
354 * Note: We simply just support master mode since SAIF TX can only
356 * Here the master is relative to codec side.
357 * Saif internally could be slave when working on EXTMASTER mode.
358 * We just hide this to machine driver.
360 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
361 case SND_SOC_DAIFMT_BP_FP:
362 if (saif->id == saif->master_id)
363 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
365 scr |= BM_SAIF_CTRL_SLAVE_MODE;
367 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
376 static int mxs_saif_startup(struct snd_pcm_substream *substream,
377 struct snd_soc_dai *cpu_dai)
379 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
382 /* clear error status to 0 for each re-open */
383 saif->fifo_underrun = 0;
384 saif->fifo_overrun = 0;
386 /* Clear Reset for normal operations */
387 __raw_writel(BM_SAIF_CTRL_SFTRST,
388 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
390 /* clear clock gate */
391 __raw_writel(BM_SAIF_CTRL_CLKGATE,
392 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
394 ret = clk_prepare(saif->clk);
401 static void mxs_saif_shutdown(struct snd_pcm_substream *substream,
402 struct snd_soc_dai *cpu_dai)
404 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
406 clk_unprepare(saif->clk);
410 * Should only be called when port is inactive.
411 * although can be called multiple times by upper layers.
413 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
414 struct snd_pcm_hw_params *params,
415 struct snd_soc_dai *cpu_dai)
417 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
418 struct mxs_saif *master_saif;
422 master_saif = mxs_saif_get_master(saif);
426 /* mclk should already be set */
427 if (!saif->mclk && saif->mclk_in_use) {
428 dev_err(cpu_dai->dev, "set mclk first\n");
432 stat = __raw_readl(saif->base + SAIF_STAT);
433 if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) {
434 dev_err(cpu_dai->dev, "error: busy\n");
439 * Set saif clk based on sample rate.
440 * If mclk is used, we also set mclk, if not, saif->mclk is
441 * default 0, means not used.
443 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
445 dev_err(cpu_dai->dev, "unable to get proper clk\n");
449 if (saif != master_saif) {
451 * Set an initial clock rate for the saif internal logic to work
452 * properly. This is important when working in EXTMASTER mode
453 * that uses the other saif's BITCLK&LRCLK but it still needs a
454 * basic clock which should be fast enough for the internal
457 ret = clk_enable(saif->clk);
461 ret = clk_set_rate(saif->clk, 24000000);
462 clk_disable(saif->clk);
466 ret = clk_prepare(master_saif->clk);
471 scr = __raw_readl(saif->base + SAIF_CTRL);
473 scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
474 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
475 switch (params_format(params)) {
476 case SNDRV_PCM_FORMAT_S16_LE:
477 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
479 case SNDRV_PCM_FORMAT_S20_3LE:
480 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
481 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
483 case SNDRV_PCM_FORMAT_S24_LE:
484 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
485 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
492 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
494 scr &= ~BM_SAIF_CTRL_READ_MODE;
497 scr |= BM_SAIF_CTRL_READ_MODE;
500 __raw_writel(scr, saif->base + SAIF_CTRL);
504 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
505 struct snd_soc_dai *cpu_dai)
507 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
509 /* enable FIFO error irqs */
510 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
511 saif->base + SAIF_CTRL + MXS_SET_ADDR);
516 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
517 struct snd_soc_dai *cpu_dai)
519 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
520 struct mxs_saif *master_saif;
524 master_saif = mxs_saif_get_master(saif);
529 case SNDRV_PCM_TRIGGER_START:
530 case SNDRV_PCM_TRIGGER_RESUME:
531 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
532 if (saif->state == MXS_SAIF_STATE_RUNNING)
535 dev_dbg(cpu_dai->dev, "start\n");
537 ret = clk_enable(master_saif->clk);
539 dev_err(saif->dev, "Failed to enable master clock\n");
544 * If the saif's master is not itself, we also need to enable
545 * itself clk for its internal basic logic to work.
547 if (saif != master_saif) {
548 ret = clk_enable(saif->clk);
550 dev_err(saif->dev, "Failed to enable master clock\n");
551 clk_disable(master_saif->clk);
555 __raw_writel(BM_SAIF_CTRL_RUN,
556 saif->base + SAIF_CTRL + MXS_SET_ADDR);
559 if (!master_saif->mclk_in_use)
560 __raw_writel(BM_SAIF_CTRL_RUN,
561 master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
563 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
565 * write data to saif data register to trigger
567 * For 24-bit format the 32-bit FIFO register stores
568 * only one channel, so we need to write twice.
569 * This is also safe for the other non 24-bit formats.
571 __raw_writel(0, saif->base + SAIF_DATA);
572 __raw_writel(0, saif->base + SAIF_DATA);
575 * read data from saif data register to trigger
577 * For 24-bit format the 32-bit FIFO register stores
578 * only one channel, so we need to read twice.
579 * This is also safe for the other non 24-bit formats.
581 __raw_readl(saif->base + SAIF_DATA);
582 __raw_readl(saif->base + SAIF_DATA);
585 master_saif->ongoing = 1;
586 saif->state = MXS_SAIF_STATE_RUNNING;
588 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
589 __raw_readl(saif->base + SAIF_CTRL),
590 __raw_readl(saif->base + SAIF_STAT));
592 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
593 __raw_readl(master_saif->base + SAIF_CTRL),
594 __raw_readl(master_saif->base + SAIF_STAT));
596 case SNDRV_PCM_TRIGGER_SUSPEND:
597 case SNDRV_PCM_TRIGGER_STOP:
598 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
599 if (saif->state == MXS_SAIF_STATE_STOPPED)
602 dev_dbg(cpu_dai->dev, "stop\n");
604 /* wait a while for the current sample to complete */
605 delay = USEC_PER_SEC / master_saif->cur_rate;
607 if (!master_saif->mclk_in_use) {
608 __raw_writel(BM_SAIF_CTRL_RUN,
609 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
612 clk_disable(master_saif->clk);
614 if (saif != master_saif) {
615 __raw_writel(BM_SAIF_CTRL_RUN,
616 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
618 clk_disable(saif->clk);
621 master_saif->ongoing = 0;
622 saif->state = MXS_SAIF_STATE_STOPPED;
632 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
633 #define MXS_SAIF_FORMATS \
634 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
635 SNDRV_PCM_FMTBIT_S24_LE)
637 static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
638 .startup = mxs_saif_startup,
639 .shutdown = mxs_saif_shutdown,
640 .trigger = mxs_saif_trigger,
641 .prepare = mxs_saif_prepare,
642 .hw_params = mxs_saif_hw_params,
643 .set_sysclk = mxs_saif_set_dai_sysclk,
644 .set_fmt = mxs_saif_set_dai_fmt,
647 static struct snd_soc_dai_driver mxs_saif_dai = {
652 .rates = MXS_SAIF_RATES,
653 .formats = MXS_SAIF_FORMATS,
658 .rates = MXS_SAIF_RATES,
659 .formats = MXS_SAIF_FORMATS,
661 .ops = &mxs_saif_dai_ops,
664 static const struct snd_soc_component_driver mxs_saif_component = {
666 .legacy_dai_naming = 1,
669 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
671 struct mxs_saif *saif = dev_id;
674 stat = __raw_readl(saif->base + SAIF_STAT);
675 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
676 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
679 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
680 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
681 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
682 saif->base + SAIF_STAT + MXS_CLR_ADDR);
685 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
686 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
687 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
688 saif->base + SAIF_STAT + MXS_CLR_ADDR);
691 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
692 __raw_readl(saif->base + SAIF_CTRL),
693 __raw_readl(saif->base + SAIF_STAT));
698 static int mxs_saif_mclk_init(struct platform_device *pdev)
700 struct mxs_saif *saif = platform_get_drvdata(pdev);
701 struct device_node *np = pdev->dev.of_node;
705 clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk",
706 __clk_get_name(saif->clk), 0,
707 saif->base + SAIF_CTRL,
708 BP_SAIF_CTRL_BITCLK_MULT_RATE, 3,
714 dev_err(&pdev->dev, "failed to register mclk: %d\n", ret);
718 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
725 static int mxs_saif_probe(struct platform_device *pdev)
727 struct device_node *np = pdev->dev.of_node;
728 struct mxs_saif *saif;
730 struct device_node *master;
732 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
736 ret = of_alias_get_id(np, "saif");
742 if (saif->id >= ARRAY_SIZE(mxs_saif)) {
743 dev_err(&pdev->dev, "get wrong saif id\n");
748 * If there is no "fsl,saif-master" phandle, it's a saif
749 * master. Otherwise, it's a slave and its phandle points
752 master = of_parse_phandle(np, "fsl,saif-master", 0);
754 saif->master_id = saif->id;
756 ret = of_alias_get_id(master, "saif");
761 saif->master_id = ret;
763 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
764 dev_err(&pdev->dev, "get wrong master id\n");
769 mxs_saif[saif->id] = saif;
771 saif->clk = devm_clk_get(&pdev->dev, NULL);
772 if (IS_ERR(saif->clk)) {
773 ret = PTR_ERR(saif->clk);
774 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
779 saif->base = devm_platform_ioremap_resource(pdev, 0);
780 if (IS_ERR(saif->base))
781 return PTR_ERR(saif->base);
783 irq = platform_get_irq(pdev, 0);
787 saif->dev = &pdev->dev;
788 ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0,
789 dev_name(&pdev->dev), saif);
791 dev_err(&pdev->dev, "failed to request irq\n");
795 platform_set_drvdata(pdev, saif);
797 /* We only support saif0 being tx and clock master */
799 ret = mxs_saif_mclk_init(pdev);
801 dev_warn(&pdev->dev, "failed to init clocks\n");
804 ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component,
807 dev_err(&pdev->dev, "register DAI failed\n");
811 ret = mxs_pcm_platform_register(&pdev->dev);
813 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
820 static const struct of_device_id mxs_saif_dt_ids[] = {
821 { .compatible = "fsl,imx28-saif", },
824 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
826 static struct platform_driver mxs_saif_driver = {
827 .probe = mxs_saif_probe,
831 .of_match_table = mxs_saif_dt_ids,
835 module_platform_driver(mxs_saif_driver);
837 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
838 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
839 MODULE_LICENSE("GPL");
840 MODULE_ALIAS("platform:mxs-saif");