1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Copyright (c) 2018 BayLibre, SAS.
4 // Author: Jerome Brunet <jbrunet@baylibre.com>
6 /* This driver implements the frontend capture DAI of AXG based SoCs */
9 #include <linux/regmap.h>
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <sound/pcm_params.h>
13 #include <sound/soc.h>
14 #include <sound/soc-dai.h>
18 #define CTRL0_TODDR_SEL_RESAMPLE BIT(30)
19 #define CTRL0_TODDR_EXT_SIGNED BIT(29)
20 #define CTRL0_TODDR_PP_MODE BIT(28)
21 #define CTRL0_TODDR_SYNC_CH BIT(27)
22 #define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13)
23 #define CTRL0_TODDR_TYPE(x) ((x) << 13)
24 #define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8)
25 #define CTRL0_TODDR_MSB_POS(x) ((x) << 8)
26 #define CTRL0_TODDR_LSB_POS_MASK GENMASK(7, 3)
27 #define CTRL0_TODDR_LSB_POS(x) ((x) << 3)
28 #define CTRL1_TODDR_FORCE_FINISH BIT(25)
29 #define CTRL1_SEL_SHIFT 28
31 #define TODDR_MSB_POS 31
33 static int axg_toddr_pcm_new(struct snd_soc_pcm_runtime *rtd,
34 struct snd_soc_dai *dai)
36 return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_CAPTURE);
39 static int g12a_toddr_dai_prepare(struct snd_pcm_substream *substream,
40 struct snd_soc_dai *dai)
42 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
44 /* Reset the write pointer to the FIFO_INIT_ADDR */
45 regmap_update_bits(fifo->map, FIFO_CTRL1,
46 CTRL1_TODDR_FORCE_FINISH, 0);
47 regmap_update_bits(fifo->map, FIFO_CTRL1,
48 CTRL1_TODDR_FORCE_FINISH, CTRL1_TODDR_FORCE_FINISH);
49 regmap_update_bits(fifo->map, FIFO_CTRL1,
50 CTRL1_TODDR_FORCE_FINISH, 0);
55 static int axg_toddr_dai_hw_params(struct snd_pcm_substream *substream,
56 struct snd_pcm_hw_params *params,
57 struct snd_soc_dai *dai)
59 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
60 unsigned int type, width;
62 switch (params_physical_width(params)) {
64 type = 0; /* 8 samples of 8 bits */
67 type = 2; /* 4 samples of 16 bits - right justified */
70 type = 4; /* 2 samples of 32 bits - right justified */
76 width = params_width(params);
78 regmap_update_bits(fifo->map, FIFO_CTRL0,
79 CTRL0_TODDR_TYPE_MASK |
80 CTRL0_TODDR_MSB_POS_MASK |
81 CTRL0_TODDR_LSB_POS_MASK,
82 CTRL0_TODDR_TYPE(type) |
83 CTRL0_TODDR_MSB_POS(TODDR_MSB_POS) |
84 CTRL0_TODDR_LSB_POS(TODDR_MSB_POS - (width - 1)));
89 static int axg_toddr_dai_startup(struct snd_pcm_substream *substream,
90 struct snd_soc_dai *dai)
92 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
95 /* Enable pclk to access registers and clock the fifo ip */
96 ret = clk_prepare_enable(fifo->pclk);
100 /* Select orginal data - resampling not supported ATM */
101 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SEL_RESAMPLE, 0);
103 /* Only signed format are supported ATM */
104 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_EXT_SIGNED,
105 CTRL0_TODDR_EXT_SIGNED);
107 /* Apply single buffer mode to the interface */
108 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_PP_MODE, 0);
113 static void axg_toddr_dai_shutdown(struct snd_pcm_substream *substream,
114 struct snd_soc_dai *dai)
116 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
118 clk_disable_unprepare(fifo->pclk);
121 static const struct snd_soc_dai_ops axg_toddr_ops = {
122 .hw_params = axg_toddr_dai_hw_params,
123 .startup = axg_toddr_dai_startup,
124 .shutdown = axg_toddr_dai_shutdown,
127 static struct snd_soc_dai_driver axg_toddr_dai_drv = {
130 .stream_name = "Capture",
132 .channels_max = AXG_FIFO_CH_MAX,
133 .rates = AXG_FIFO_RATES,
134 .formats = AXG_FIFO_FORMATS,
136 .ops = &axg_toddr_ops,
137 .pcm_new = axg_toddr_pcm_new,
140 static const char * const axg_toddr_sel_texts[] = {
141 "IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", "IN 6", "IN 7"
144 static SOC_ENUM_SINGLE_DECL(axg_toddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
145 axg_toddr_sel_texts);
147 static const struct snd_kcontrol_new axg_toddr_in_mux =
148 SOC_DAPM_ENUM("Input Source", axg_toddr_sel_enum);
150 static const struct snd_soc_dapm_widget axg_toddr_dapm_widgets[] = {
151 SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &axg_toddr_in_mux),
152 SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
153 SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
154 SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
155 SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0),
156 SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0),
157 SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0),
158 SND_SOC_DAPM_AIF_IN("IN 6", NULL, 0, SND_SOC_NOPM, 0, 0),
159 SND_SOC_DAPM_AIF_IN("IN 7", NULL, 0, SND_SOC_NOPM, 0, 0),
162 static const struct snd_soc_dapm_route axg_toddr_dapm_routes[] = {
163 { "Capture", NULL, "SRC SEL" },
164 { "SRC SEL", "IN 0", "IN 0" },
165 { "SRC SEL", "IN 1", "IN 1" },
166 { "SRC SEL", "IN 2", "IN 2" },
167 { "SRC SEL", "IN 3", "IN 3" },
168 { "SRC SEL", "IN 4", "IN 4" },
169 { "SRC SEL", "IN 5", "IN 5" },
170 { "SRC SEL", "IN 6", "IN 6" },
171 { "SRC SEL", "IN 7", "IN 7" },
174 static const struct snd_soc_component_driver axg_toddr_component_drv = {
175 .dapm_widgets = axg_toddr_dapm_widgets,
176 .num_dapm_widgets = ARRAY_SIZE(axg_toddr_dapm_widgets),
177 .dapm_routes = axg_toddr_dapm_routes,
178 .num_dapm_routes = ARRAY_SIZE(axg_toddr_dapm_routes),
179 .ops = &axg_fifo_pcm_ops
182 static const struct axg_fifo_match_data axg_toddr_match_data = {
183 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
184 .component_drv = &axg_toddr_component_drv,
185 .dai_drv = &axg_toddr_dai_drv
188 static int g12a_toddr_dai_startup(struct snd_pcm_substream *substream,
189 struct snd_soc_dai *dai)
191 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
194 ret = axg_toddr_dai_startup(substream, dai);
199 * Make sure the first channel ends up in the at beginning of the output
200 * As weird as it looks, without this the first channel may be misplaced
201 * in memory, with a random shift of 2 channels.
203 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SYNC_CH,
204 CTRL0_TODDR_SYNC_CH);
209 static const struct snd_soc_dai_ops g12a_toddr_ops = {
210 .prepare = g12a_toddr_dai_prepare,
211 .hw_params = axg_toddr_dai_hw_params,
212 .startup = g12a_toddr_dai_startup,
213 .shutdown = axg_toddr_dai_shutdown,
216 static struct snd_soc_dai_driver g12a_toddr_dai_drv = {
219 .stream_name = "Capture",
221 .channels_max = AXG_FIFO_CH_MAX,
222 .rates = AXG_FIFO_RATES,
223 .formats = AXG_FIFO_FORMATS,
225 .ops = &g12a_toddr_ops,
226 .pcm_new = axg_toddr_pcm_new,
229 static const struct snd_soc_component_driver g12a_toddr_component_drv = {
230 .dapm_widgets = axg_toddr_dapm_widgets,
231 .num_dapm_widgets = ARRAY_SIZE(axg_toddr_dapm_widgets),
232 .dapm_routes = axg_toddr_dapm_routes,
233 .num_dapm_routes = ARRAY_SIZE(axg_toddr_dapm_routes),
234 .ops = &g12a_fifo_pcm_ops
237 static const struct axg_fifo_match_data g12a_toddr_match_data = {
238 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
239 .component_drv = &g12a_toddr_component_drv,
240 .dai_drv = &g12a_toddr_dai_drv
243 static const char * const sm1_toddr_sel_texts[] = {
244 "IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", "IN 6", "IN 7",
245 "IN 8", "IN 9", "IN 10", "IN 11", "IN 12", "IN 13", "IN 14", "IN 15"
248 static SOC_ENUM_SINGLE_DECL(sm1_toddr_sel_enum, FIFO_CTRL1, CTRL1_SEL_SHIFT,
249 sm1_toddr_sel_texts);
251 static const struct snd_kcontrol_new sm1_toddr_in_mux =
252 SOC_DAPM_ENUM("Input Source", sm1_toddr_sel_enum);
254 static const struct snd_soc_dapm_widget sm1_toddr_dapm_widgets[] = {
255 SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &sm1_toddr_in_mux),
256 SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
257 SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
258 SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
259 SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0),
260 SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0),
261 SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0),
262 SND_SOC_DAPM_AIF_IN("IN 6", NULL, 0, SND_SOC_NOPM, 0, 0),
263 SND_SOC_DAPM_AIF_IN("IN 7", NULL, 0, SND_SOC_NOPM, 0, 0),
264 SND_SOC_DAPM_AIF_IN("IN 8", NULL, 0, SND_SOC_NOPM, 0, 0),
265 SND_SOC_DAPM_AIF_IN("IN 9", NULL, 0, SND_SOC_NOPM, 0, 0),
266 SND_SOC_DAPM_AIF_IN("IN 10", NULL, 0, SND_SOC_NOPM, 0, 0),
267 SND_SOC_DAPM_AIF_IN("IN 11", NULL, 0, SND_SOC_NOPM, 0, 0),
268 SND_SOC_DAPM_AIF_IN("IN 12", NULL, 0, SND_SOC_NOPM, 0, 0),
269 SND_SOC_DAPM_AIF_IN("IN 13", NULL, 0, SND_SOC_NOPM, 0, 0),
270 SND_SOC_DAPM_AIF_IN("IN 14", NULL, 0, SND_SOC_NOPM, 0, 0),
271 SND_SOC_DAPM_AIF_IN("IN 15", NULL, 0, SND_SOC_NOPM, 0, 0),
274 static const struct snd_soc_dapm_route sm1_toddr_dapm_routes[] = {
275 { "Capture", NULL, "SRC SEL" },
276 { "SRC SEL", "IN 0", "IN 0" },
277 { "SRC SEL", "IN 1", "IN 1" },
278 { "SRC SEL", "IN 2", "IN 2" },
279 { "SRC SEL", "IN 3", "IN 3" },
280 { "SRC SEL", "IN 4", "IN 4" },
281 { "SRC SEL", "IN 5", "IN 5" },
282 { "SRC SEL", "IN 6", "IN 6" },
283 { "SRC SEL", "IN 7", "IN 7" },
284 { "SRC SEL", "IN 8", "IN 8" },
285 { "SRC SEL", "IN 9", "IN 9" },
286 { "SRC SEL", "IN 10", "IN 10" },
287 { "SRC SEL", "IN 11", "IN 11" },
288 { "SRC SEL", "IN 12", "IN 12" },
289 { "SRC SEL", "IN 13", "IN 13" },
290 { "SRC SEL", "IN 14", "IN 14" },
291 { "SRC SEL", "IN 15", "IN 15" },
294 static const struct snd_soc_component_driver sm1_toddr_component_drv = {
295 .dapm_widgets = sm1_toddr_dapm_widgets,
296 .num_dapm_widgets = ARRAY_SIZE(sm1_toddr_dapm_widgets),
297 .dapm_routes = sm1_toddr_dapm_routes,
298 .num_dapm_routes = ARRAY_SIZE(sm1_toddr_dapm_routes),
299 .ops = &g12a_fifo_pcm_ops
302 static const struct axg_fifo_match_data sm1_toddr_match_data = {
303 .field_threshold = REG_FIELD(FIFO_CTRL1, 12, 23),
304 .component_drv = &sm1_toddr_component_drv,
305 .dai_drv = &g12a_toddr_dai_drv
308 static const struct of_device_id axg_toddr_of_match[] = {
310 .compatible = "amlogic,axg-toddr",
311 .data = &axg_toddr_match_data,
313 .compatible = "amlogic,g12a-toddr",
314 .data = &g12a_toddr_match_data,
316 .compatible = "amlogic,sm1-toddr",
317 .data = &sm1_toddr_match_data,
320 MODULE_DEVICE_TABLE(of, axg_toddr_of_match);
322 static struct platform_driver axg_toddr_pdrv = {
323 .probe = axg_fifo_probe,
326 .of_match_table = axg_toddr_of_match,
329 module_platform_driver(axg_toddr_pdrv);
331 MODULE_DESCRIPTION("Amlogic AXG capture fifo driver");
332 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
333 MODULE_LICENSE("GPL v2");