1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mt8195-afe-clk.h -- Mediatek 8195 afe clock ctrl definition
5 * Copyright (c) 2021 MediaTek Inc.
6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7 * Trevor Wu <trevor.wu@mediatek.com>
10 #ifndef _MT8195_AFE_CLK_H_
11 #define _MT8195_AFE_CLK_H_
19 MT8195_CLK_TOP_APLL12_DIV0,
20 MT8195_CLK_TOP_APLL12_DIV1,
21 MT8195_CLK_TOP_APLL12_DIV2,
22 MT8195_CLK_TOP_APLL12_DIV3,
23 MT8195_CLK_TOP_APLL12_DIV9,
25 MT8195_CLK_TOP_A1SYS_HP_SEL,
26 MT8195_CLK_TOP_AUD_INTBUS_SEL,
27 MT8195_CLK_TOP_AUDIO_H_SEL,
28 MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
29 MT8195_CLK_TOP_DPTX_M_SEL,
30 MT8195_CLK_TOP_I2SO1_M_SEL,
31 MT8195_CLK_TOP_I2SO2_M_SEL,
32 MT8195_CLK_TOP_I2SI1_M_SEL,
33 MT8195_CLK_TOP_I2SI2_M_SEL,
35 MT8195_CLK_INFRA_AO_AUDIO_26M_B,
36 MT8195_CLK_SCP_ADSP_AUDIODSP,
38 MT8195_CLK_AUD_APLL1_TUNER,
39 MT8195_CLK_AUD_APLL2_TUNER,
44 MT8195_CLK_AUD_DAC_HIRES,
45 MT8195_CLK_AUD_A1SYS_HP,
46 MT8195_CLK_AUD_ADC_HIRES,
47 MT8195_CLK_AUD_ADDA6_ADC,
48 MT8195_CLK_AUD_ADDA6_ADC_HIRES,
50 MT8195_CLK_AUD_TDM_IN,
51 MT8195_CLK_AUD_I2S_OUT,
52 MT8195_CLK_AUD_TDM_OUT,
53 MT8195_CLK_AUD_HDMI_OUT,
54 MT8195_CLK_AUD_ASRC11,
55 MT8195_CLK_AUD_ASRC12,
59 MT8195_CLK_AUD_MEMIF_UL1,
60 MT8195_CLK_AUD_MEMIF_UL2,
61 MT8195_CLK_AUD_MEMIF_UL3,
62 MT8195_CLK_AUD_MEMIF_UL4,
63 MT8195_CLK_AUD_MEMIF_UL5,
64 MT8195_CLK_AUD_MEMIF_UL6,
65 MT8195_CLK_AUD_MEMIF_UL8,
66 MT8195_CLK_AUD_MEMIF_UL9,
67 MT8195_CLK_AUD_MEMIF_UL10,
68 MT8195_CLK_AUD_MEMIF_DL2,
69 MT8195_CLK_AUD_MEMIF_DL3,
70 MT8195_CLK_AUD_MEMIF_DL6,
71 MT8195_CLK_AUD_MEMIF_DL7,
72 MT8195_CLK_AUD_MEMIF_DL8,
73 MT8195_CLK_AUD_MEMIF_DL10,
74 MT8195_CLK_AUD_MEMIF_DL11,
85 MT8195_MCK_SEL_HDMIRX_APLL,
100 int mt8195_afe_get_mclk_source_clk_id(int sel);
101 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
102 int mt8195_afe_get_default_mclk_source_by_rate(int rate);
103 int mt8195_afe_init_clock(struct mtk_base_afe *afe);
104 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
105 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
106 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
107 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk);
108 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
109 void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
110 int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
112 int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
114 int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe);
115 int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe);
116 int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
117 int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);