1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mt8188-afe-clk.h -- MediaTek 8188 afe clock ctrl definition
5 * Copyright (c) 2022 MediaTek Inc.
6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7 * Trevor Wu <trevor.wu@mediatek.com>
8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
11 #ifndef _MT8188_AFE_CLK_H_
12 #define _MT8188_AFE_CLK_H_
15 #define APLL1_W_NAME "APLL1"
16 #define APLL2_W_NAME "APLL2"
22 MT8188_CLK_APMIXED_APLL1,
23 MT8188_CLK_APMIXED_APLL2,
25 MT8188_CLK_TOP_APLL1_D4,
26 MT8188_CLK_TOP_APLL2_D4,
27 MT8188_CLK_TOP_APLL12_DIV0,
28 MT8188_CLK_TOP_APLL12_DIV1,
29 MT8188_CLK_TOP_APLL12_DIV2,
30 MT8188_CLK_TOP_APLL12_DIV3,
31 MT8188_CLK_TOP_APLL12_DIV4,
32 MT8188_CLK_TOP_APLL12_DIV9,
34 MT8188_CLK_TOP_A1SYS_HP_SEL,
35 MT8188_CLK_TOP_A2SYS_SEL,
36 MT8188_CLK_TOP_AUD_IEC_SEL,
37 MT8188_CLK_TOP_AUD_INTBUS_SEL,
38 MT8188_CLK_TOP_AUDIO_H_SEL,
39 MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
40 MT8188_CLK_TOP_DPTX_M_SEL,
41 MT8188_CLK_TOP_I2SO1_M_SEL,
42 MT8188_CLK_TOP_I2SO2_M_SEL,
43 MT8188_CLK_TOP_I2SI1_M_SEL,
44 MT8188_CLK_TOP_I2SI2_M_SEL,
46 MT8188_CLK_ADSP_AUDIO_26M,
48 MT8188_CLK_AUD_APLL1_TUNER,
49 MT8188_CLK_AUD_APLL2_TUNER,
50 MT8188_CLK_AUD_TOP0_SPDF,
55 MT8188_CLK_AUD_DAC_HIRES,
56 MT8188_CLK_AUD_A1SYS_HP,
57 MT8188_CLK_AUD_ADC_HIRES,
59 MT8188_CLK_AUD_TDM_IN,
60 MT8188_CLK_AUD_I2S_OUT,
61 MT8188_CLK_AUD_TDM_OUT,
62 MT8188_CLK_AUD_HDMI_OUT,
63 MT8188_CLK_AUD_ASRC11,
64 MT8188_CLK_AUD_ASRC12,
68 MT8188_CLK_AUD_MEMIF_UL1,
69 MT8188_CLK_AUD_MEMIF_UL2,
70 MT8188_CLK_AUD_MEMIF_UL3,
71 MT8188_CLK_AUD_MEMIF_UL4,
72 MT8188_CLK_AUD_MEMIF_UL5,
73 MT8188_CLK_AUD_MEMIF_UL6,
74 MT8188_CLK_AUD_MEMIF_UL8,
75 MT8188_CLK_AUD_MEMIF_UL9,
76 MT8188_CLK_AUD_MEMIF_UL10,
77 MT8188_CLK_AUD_MEMIF_DL2,
78 MT8188_CLK_AUD_MEMIF_DL3,
79 MT8188_CLK_AUD_MEMIF_DL6,
80 MT8188_CLK_AUD_MEMIF_DL7,
81 MT8188_CLK_AUD_MEMIF_DL8,
82 MT8188_CLK_AUD_MEMIF_DL10,
83 MT8188_CLK_AUD_MEMIF_DL11,
100 MT8188_MCK_SEL_APLL3,
101 MT8188_MCK_SEL_APLL4,
102 MT8188_MCK_SEL_APLL5,
108 int mt8188_afe_get_mclk_source_clk_id(int sel);
109 int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
110 int mt8188_afe_get_default_mclk_source_by_rate(int rate);
111 int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
112 int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
113 int mt8188_afe_init_clock(struct mtk_base_afe *afe);
114 int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
115 void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
116 int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
118 int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
120 int mt8188_apll1_enable(struct mtk_base_afe *afe);
121 int mt8188_apll1_disable(struct mtk_base_afe *afe);
122 int mt8188_apll2_enable(struct mtk_base_afe *afe);
123 int mt8188_apll2_disable(struct mtk_base_afe *afe);
124 int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe);
125 int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe);
126 int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
127 int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);