1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-afe-common.h -- Mediatek 8186 audio driver definitions
5 * Copyright (c) 2022 MediaTek Inc.
6 * Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
9 #ifndef _MT_8186_AFE_COMMON_H_
10 #define _MT_8186_AFE_COMMON_H_
11 #include <sound/soc.h>
12 #include <linux/list.h>
13 #include <linux/regmap.h>
14 #include "mt8186-reg.h"
15 #include "../common/mtk-base-afe.h"
36 MT8186_DAI_ADDA = MT8186_MEMIF_NUM,
38 MT8186_DAI_CONNSYS_I2S,
49 MT8186_DAI_HOSTLESS_LPBK,
50 MT8186_DAI_HOSTLESS_FM,
51 MT8186_DAI_HOSTLESS_HW_GAIN_AAUDIO,
52 MT8186_DAI_HOSTLESS_SRC_AAUDIO,
53 MT8186_DAI_HOSTLESS_SRC_1,
54 MT8186_DAI_HOSTLESS_SRC_BARGEIN,
55 MT8186_DAI_HOSTLESS_UL1,
56 MT8186_DAI_HOSTLESS_UL2,
57 MT8186_DAI_HOSTLESS_UL3,
58 MT8186_DAI_HOSTLESS_UL5,
59 MT8186_DAI_HOSTLESS_UL6,
63 #define MT8186_RECORD_MEMIF MT8186_MEMIF_VUL12
64 #define MT8186_ECHO_REF_MEMIF MT8186_MEMIF_AWB
65 #define MT8186_PRIMARY_MEMIF MT8186_MEMIF_DL1
66 #define MT8186_FAST_MEMIF MT8186_MEMIF_DL2
67 #define MT8186_DEEP_MEMIF MT8186_MEMIF_DL3
68 #define MT8186_VOIP_MEMIF MT8186_MEMIF_DL12
69 #define MT8186_MMAP_DL_MEMIF MT8186_MEMIF_DL5
70 #define MT8186_MMAP_UL_MEMIF MT8186_MEMIF_VUL5
71 #define MT8186_BARGEIN_MEMIF MT8186_MEMIF_AWB
105 MT8186_AFE_IRQ_DIR_MCU = 0,
106 MT8186_AFE_IRQ_DIR_DSP,
107 MT8186_AFE_IRQ_DIR_BOTH,
111 MTKAIF_PROTOCOL_1 = 0,
113 MTKAIF_PROTOCOL_2_CLK_P2,
117 MTK_AFE_ADDA_DL_GAIN_MUTE = 0,
118 MTK_AFE_ADDA_DL_GAIN_NORMAL = 0xf74f,
119 /* SA suggest apply -0.3db to audio/speech path */
122 #define MTK_SPK_I2S_0_STR "MTK_SPK_I2S_0"
123 #define MTK_SPK_I2S_1_STR "MTK_SPK_I2S_1"
124 #define MTK_SPK_I2S_2_STR "MTK_SPK_I2S_2"
125 #define MTK_SPK_I2S_3_STR "MTK_SPK_I2S_3"
137 struct snd_pcm_substream;
138 struct mtk_base_irq_data;
141 struct mt8186_afe_private {
143 struct clk_lookup **lookup;
144 struct regmap *topckgen;
145 struct regmap *apmixedsys;
146 struct regmap *infracfg;
147 int irq_cnt[MT8186_MEMIF_NUM];
148 int stf_positive_gain_db;
149 int pm_runtime_bypass_reg_ctl;
155 int xrun_assert[MT8186_MEMIF_NUM];
158 bool dai_on[MT8186_DAI_NUM];
159 void *dai_priv[MT8186_DAI_NUM];
162 bool mtkaif_calibration_ok;
164 int mtkaif_chosen_phase[4];
165 int mtkaif_phase_cycle[4];
166 int mtkaif_calibration_num_phase;
172 int mck_rate[MT8186_MCK_NUM];
175 int mt8186_dai_adda_register(struct mtk_base_afe *afe);
176 int mt8186_dai_i2s_register(struct mtk_base_afe *afe);
177 int mt8186_dai_tdm_register(struct mtk_base_afe *afe);
178 int mt8186_dai_hw_gain_register(struct mtk_base_afe *afe);
179 int mt8186_dai_src_register(struct mtk_base_afe *afe);
180 int mt8186_dai_pcm_register(struct mtk_base_afe *afe);
181 int mt8186_dai_hostless_register(struct mtk_base_afe *afe);
183 int mt8186_add_misc_control(struct snd_soc_component *component);
185 unsigned int mt8186_general_rate_transform(struct device *dev,
187 unsigned int mt8186_rate_transform(struct device *dev,
188 unsigned int rate, int aud_blk);
189 unsigned int mt8186_tdm_relatch_rate_transform(struct device *dev,
192 int mt8186_dai_i2s_set_share(struct mtk_base_afe *afe, const char *main_i2s_name,
193 const char *secondary_i2s_name);
195 int mt8186_dai_set_priv(struct mtk_base_afe *afe, int id,
196 int priv_size, const void *priv_data);