1 // SPDX-License-Identifier: GPL-2.0
3 // MediaTek ALSA SoC Audio DAI ADDA Control
5 // Copyright (c) 2018 MediaTek Inc.
6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
8 #include <linux/regmap.h>
9 #include <linux/delay.h>
10 #include "mt8183-afe-common.h"
11 #include "mt8183-interconnection.h"
12 #include "mt8183-reg.h"
15 AUDIO_SDM_LEVEL_MUTE = 0,
16 AUDIO_SDM_LEVEL_NORMAL = 0x1d,
17 /* if you change level normal */
18 /* you need to change formula of hp impedance and dc trim too */
27 MTK_AFE_ADDA_DL_RATE_8K = 0,
28 MTK_AFE_ADDA_DL_RATE_11K = 1,
29 MTK_AFE_ADDA_DL_RATE_12K = 2,
30 MTK_AFE_ADDA_DL_RATE_16K = 3,
31 MTK_AFE_ADDA_DL_RATE_22K = 4,
32 MTK_AFE_ADDA_DL_RATE_24K = 5,
33 MTK_AFE_ADDA_DL_RATE_32K = 6,
34 MTK_AFE_ADDA_DL_RATE_44K = 7,
35 MTK_AFE_ADDA_DL_RATE_48K = 8,
36 MTK_AFE_ADDA_DL_RATE_96K = 9,
37 MTK_AFE_ADDA_DL_RATE_192K = 10,
41 MTK_AFE_ADDA_UL_RATE_8K = 0,
42 MTK_AFE_ADDA_UL_RATE_16K = 1,
43 MTK_AFE_ADDA_UL_RATE_32K = 2,
44 MTK_AFE_ADDA_UL_RATE_48K = 3,
45 MTK_AFE_ADDA_UL_RATE_96K = 4,
46 MTK_AFE_ADDA_UL_RATE_192K = 5,
47 MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
50 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
55 return MTK_AFE_ADDA_DL_RATE_8K;
57 return MTK_AFE_ADDA_DL_RATE_11K;
59 return MTK_AFE_ADDA_DL_RATE_12K;
61 return MTK_AFE_ADDA_DL_RATE_16K;
63 return MTK_AFE_ADDA_DL_RATE_22K;
65 return MTK_AFE_ADDA_DL_RATE_24K;
67 return MTK_AFE_ADDA_DL_RATE_32K;
69 return MTK_AFE_ADDA_DL_RATE_44K;
71 return MTK_AFE_ADDA_DL_RATE_48K;
73 return MTK_AFE_ADDA_DL_RATE_96K;
75 return MTK_AFE_ADDA_DL_RATE_192K;
77 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
79 return MTK_AFE_ADDA_DL_RATE_48K;
83 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
88 return MTK_AFE_ADDA_UL_RATE_8K;
90 return MTK_AFE_ADDA_UL_RATE_16K;
92 return MTK_AFE_ADDA_UL_RATE_32K;
94 return MTK_AFE_ADDA_UL_RATE_48K;
96 return MTK_AFE_ADDA_UL_RATE_96K;
98 return MTK_AFE_ADDA_UL_RATE_192K;
100 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
102 return MTK_AFE_ADDA_UL_RATE_48K;
107 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
108 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
109 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
110 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
111 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
112 I_ADDA_UL_CH2, 1, 0),
113 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
114 I_ADDA_UL_CH1, 1, 0),
115 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
116 I_PCM_1_CAP_CH1, 1, 0),
117 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
118 I_PCM_2_CAP_CH1, 1, 0),
121 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
122 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
123 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
124 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
125 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
126 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
127 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
128 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
129 I_ADDA_UL_CH2, 1, 0),
130 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
131 I_ADDA_UL_CH1, 1, 0),
132 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
133 I_PCM_1_CAP_CH1, 1, 0),
134 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
135 I_PCM_2_CAP_CH1, 1, 0),
136 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
137 I_PCM_1_CAP_CH2, 1, 0),
138 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
139 I_PCM_2_CAP_CH2, 1, 0),
142 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
143 struct snd_kcontrol *kcontrol,
146 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
147 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
148 struct mt8183_afe_private *afe_priv = afe->platform_priv;
150 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
151 __func__, w->name, event);
154 case SND_SOC_DAPM_PRE_PMU:
155 /* update setting to dmic */
156 if (afe_priv->mtkaif_dmic) {
157 /* mtkaif_rxif_data_mode = 1, dmic */
158 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
161 /* dmic mode, 3.25M*/
162 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
164 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
166 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
169 /* turn on dmic, ch1, ch2 */
170 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
172 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
173 0x3 << 21, 0x3 << 21);
176 case SND_SOC_DAPM_POST_PMD:
177 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
178 usleep_range(125, 135);
188 static const char * const mt8183_adda_off_on_str[] = {
192 static const struct soc_enum mt8183_adda_enum[] = {
193 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8183_adda_off_on_str),
194 mt8183_adda_off_on_str),
197 static int mt8183_adda_dmic_get(struct snd_kcontrol *kcontrol,
198 struct snd_ctl_elem_value *ucontrol)
200 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
201 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
202 struct mt8183_afe_private *afe_priv = afe->platform_priv;
204 ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
209 static int mt8183_adda_dmic_set(struct snd_kcontrol *kcontrol,
210 struct snd_ctl_elem_value *ucontrol)
212 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
213 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
214 struct mt8183_afe_private *afe_priv = afe->platform_priv;
215 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
217 if (ucontrol->value.enumerated.item[0] >= e->items)
220 afe_priv->mtkaif_dmic = ucontrol->value.integer.value[0];
222 dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_dmic %d\n",
223 __func__, kcontrol->id.name, afe_priv->mtkaif_dmic);
228 static const struct snd_kcontrol_new mtk_adda_controls[] = {
229 SOC_ENUM_EXT("MTKAIF_DMIC", mt8183_adda_enum[0],
230 mt8183_adda_dmic_get, mt8183_adda_dmic_set),
234 SUPPLY_SEQ_ADDA_AFE_ON,
235 SUPPLY_SEQ_ADDA_DL_ON,
236 SUPPLY_SEQ_ADDA_UL_ON,
239 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
241 SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
243 ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
244 SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
246 ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
248 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
249 AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
252 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
253 AFE_ADDA_DL_SRC2_CON0,
254 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
257 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
258 AFE_ADDA_UL_SRC_CON0,
259 UL_SRC_ON_TMP_CTL_SFT, 0,
261 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
263 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
264 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
265 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
266 SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
269 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
271 {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
272 {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
273 {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
275 {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
276 {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
277 {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
279 {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
280 {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
281 {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
283 {"ADDA Playback", NULL, "ADDA_DL_CH1"},
284 {"ADDA Playback", NULL, "ADDA_DL_CH2"},
287 {"ADDA Playback", NULL, "ADDA Enable"},
288 {"ADDA Playback", NULL, "ADDA Playback Enable"},
289 {"ADDA Capture", NULL, "ADDA Enable"},
290 {"ADDA Capture", NULL, "ADDA Capture Enable"},
293 {"ADDA Playback", NULL, "mtkaif_26m_clk"},
294 {"ADDA Playback", NULL, "aud_dac_clk"},
295 {"ADDA Playback", NULL, "aud_dac_predis_clk"},
297 {"ADDA Capture", NULL, "mtkaif_26m_clk"},
298 {"ADDA Capture", NULL, "aud_adc_clk"},
301 static int set_mtkaif_rx(struct mtk_base_afe *afe)
303 struct mt8183_afe_private *afe_priv = afe->platform_priv;
307 switch (afe_priv->mtkaif_protocol) {
308 case MT8183_MTKAIF_PROTOCOL_2_CLK_P2:
309 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38);
310 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39);
311 /* mtkaif_rxif_clkinv_adc inverse for calibration */
312 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
315 if (afe_priv->mtkaif_phase_cycle[0] >=
316 afe_priv->mtkaif_phase_cycle[1]) {
317 delay_data = DELAY_DATA_MISO1;
318 delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
319 afe_priv->mtkaif_phase_cycle[1];
321 delay_data = DELAY_DATA_MISO2;
322 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
323 afe_priv->mtkaif_phase_cycle[0];
326 regmap_update_bits(afe->regmap,
327 AFE_ADDA_MTKAIF_RX_CFG2,
328 MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
329 delay_data << MTKAIF_RXIF_DELAY_DATA_SFT);
331 regmap_update_bits(afe->regmap,
332 AFE_ADDA_MTKAIF_RX_CFG2,
333 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
334 delay_cycle << MTKAIF_RXIF_DELAY_CYCLE_SFT);
336 case MT8183_MTKAIF_PROTOCOL_2:
337 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
338 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
341 case MT8183_MTKAIF_PROTOCOL_1:
342 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
343 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0);
353 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
354 struct snd_pcm_hw_params *params,
355 struct snd_soc_dai *dai)
357 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
358 unsigned int rate = params_rate(params);
360 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
361 __func__, dai->id, substream->stream, rate);
363 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
364 unsigned int dl_src2_con0 = 0;
365 unsigned int dl_src2_con1 = 0;
367 /* clean predistortion */
368 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
369 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
371 /* set sampling rate */
372 dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28;
374 /* set output mode */
377 dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
378 dl_src2_con0 |= 1 << 14;
381 dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
382 dl_src2_con0 |= 1 << 14;
385 dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
389 /* turn off mute function */
390 dl_src2_con0 |= (0x03 << 11);
392 /* set voice input data if input sample rate is 8k or 16k */
393 if (rate == 8000 || rate == 16000)
394 dl_src2_con0 |= 0x01 << 5;
396 /* SA suggest apply -0.3db to audio/speech path */
397 dl_src2_con1 = 0xf74f0000;
399 /* turn on down-link gain */
400 dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
402 regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
403 regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
406 regmap_update_bits(afe->regmap,
407 AFE_ADDA_DL_SDM_DCCOMP_CON,
408 ATTGAIN_CTL_MASK_SFT,
409 AUDIO_SDM_LEVEL_NORMAL << ATTGAIN_CTL_SFT);
411 unsigned int voice_mode = 0;
412 unsigned int ul_src_con0 = 0; /* default value */
414 /* set mtkaif protocol */
417 /* Using Internal ADC */
418 regmap_update_bits(afe->regmap,
423 voice_mode = adda_ul_rate_transform(afe, rate);
425 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
428 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
429 UL_IIR_ON_TMP_CTL_MASK_SFT;
432 regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_02_01, 0x00000000);
433 regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_04_03, 0x00003FB8);
434 regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_06_05, 0x3FB80000);
435 regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_08_07, 0x3FB80000);
436 regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_10_09, 0x0000C048);
438 regmap_write(afe->regmap, AFE_ADDA_UL_SRC_CON0, ul_src_con0);
440 /* mtkaif_rxif_data_mode = 0, amic */
441 regmap_update_bits(afe->regmap,
442 AFE_ADDA_MTKAIF_RX_CFG0,
450 static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
451 .hw_params = mtk_dai_adda_hw_params,
455 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
456 SNDRV_PCM_RATE_96000 |\
457 SNDRV_PCM_RATE_192000)
459 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
460 SNDRV_PCM_RATE_16000 |\
461 SNDRV_PCM_RATE_32000 |\
462 SNDRV_PCM_RATE_48000)
464 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
465 SNDRV_PCM_FMTBIT_S24_LE |\
466 SNDRV_PCM_FMTBIT_S32_LE)
468 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
471 .id = MT8183_DAI_ADDA,
473 .stream_name = "ADDA Playback",
476 .rates = MTK_ADDA_PLAYBACK_RATES,
477 .formats = MTK_ADDA_FORMATS,
480 .stream_name = "ADDA Capture",
483 .rates = MTK_ADDA_CAPTURE_RATES,
484 .formats = MTK_ADDA_FORMATS,
486 .ops = &mtk_dai_adda_ops,
490 int mt8183_dai_adda_register(struct mtk_base_afe *afe)
492 struct mtk_base_afe_dai *dai;
494 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
498 list_add(&dai->list, &afe->sub_dais);
500 dai->dai_drivers = mtk_dai_adda_driver;
501 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
503 dai->controls = mtk_adda_controls;
504 dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
505 dai->dapm_widgets = mtk_dai_adda_widgets;
506 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
507 dai->dapm_routes = mtk_dai_adda_routes;
508 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);