1 // SPDX-License-Identifier: GPL-2.0
3 // Mediatek ALSA SoC AFE platform driver for 8183
5 // Copyright (c) 2018 MediaTek Inc.
6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
8 #include <linux/delay.h>
9 #include <linux/module.h>
10 #include <linux/mfd/syscon.h>
12 #include <linux/of_address.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
16 #include "mt8183-afe-common.h"
17 #include "mt8183-afe-clk.h"
18 #include "mt8183-interconnection.h"
19 #include "mt8183-reg.h"
20 #include "../common/mtk-afe-platform-driver.h"
21 #include "../common/mtk-afe-fe-dai.h"
27 MTK_AFE_RATE_384K = 3,
31 MTK_AFE_RATE_130K = 7,
34 MTK_AFE_RATE_48K = 10,
35 MTK_AFE_RATE_88K = 11,
36 MTK_AFE_RATE_96K = 12,
37 MTK_AFE_RATE_176K = 13,
38 MTK_AFE_RATE_192K = 14,
39 MTK_AFE_RATE_260K = 15,
43 MTK_AFE_DAI_MEMIF_RATE_8K = 0,
44 MTK_AFE_DAI_MEMIF_RATE_16K = 1,
45 MTK_AFE_DAI_MEMIF_RATE_32K = 2,
46 MTK_AFE_DAI_MEMIF_RATE_48K = 3,
50 MTK_AFE_PCM_RATE_8K = 0,
51 MTK_AFE_PCM_RATE_16K = 1,
52 MTK_AFE_PCM_RATE_32K = 2,
53 MTK_AFE_PCM_RATE_48K = 3,
56 unsigned int mt8183_general_rate_transform(struct device *dev,
61 return MTK_AFE_RATE_8K;
63 return MTK_AFE_RATE_11K;
65 return MTK_AFE_RATE_12K;
67 return MTK_AFE_RATE_16K;
69 return MTK_AFE_RATE_22K;
71 return MTK_AFE_RATE_24K;
73 return MTK_AFE_RATE_32K;
75 return MTK_AFE_RATE_44K;
77 return MTK_AFE_RATE_48K;
79 return MTK_AFE_RATE_88K;
81 return MTK_AFE_RATE_96K;
83 return MTK_AFE_RATE_130K;
85 return MTK_AFE_RATE_176K;
87 return MTK_AFE_RATE_192K;
89 return MTK_AFE_RATE_260K;
91 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
92 __func__, rate, MTK_AFE_RATE_48K);
93 return MTK_AFE_RATE_48K;
97 static unsigned int dai_memif_rate_transform(struct device *dev,
102 return MTK_AFE_DAI_MEMIF_RATE_8K;
104 return MTK_AFE_DAI_MEMIF_RATE_16K;
106 return MTK_AFE_DAI_MEMIF_RATE_32K;
108 return MTK_AFE_DAI_MEMIF_RATE_48K;
110 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
111 __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
112 return MTK_AFE_DAI_MEMIF_RATE_16K;
116 unsigned int mt8183_rate_transform(struct device *dev,
117 unsigned int rate, int aud_blk)
120 case MT8183_MEMIF_MOD_DAI:
121 return dai_memif_rate_transform(dev, rate);
123 return mt8183_general_rate_transform(dev, rate);
127 static const struct snd_pcm_hardware mt8183_afe_hardware = {
128 .info = SNDRV_PCM_INFO_MMAP |
129 SNDRV_PCM_INFO_INTERLEAVED |
130 SNDRV_PCM_INFO_MMAP_VALID,
131 .formats = SNDRV_PCM_FMTBIT_S16_LE |
132 SNDRV_PCM_FMTBIT_S24_LE |
133 SNDRV_PCM_FMTBIT_S32_LE,
134 .period_bytes_min = 256,
135 .period_bytes_max = 4 * 48 * 1024,
138 .buffer_bytes_max = 8 * 48 * 1024,
142 static int mt8183_memif_fs(struct snd_pcm_substream *substream,
145 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
146 struct snd_soc_component *component =
147 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
148 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
149 int id = asoc_rtd_to_cpu(rtd, 0)->id;
151 return mt8183_rate_transform(afe->dev, rate, id);
154 static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
156 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
157 struct snd_soc_component *component =
158 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
159 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
161 return mt8183_general_rate_transform(afe->dev, rate);
164 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
165 SNDRV_PCM_RATE_88200 |\
166 SNDRV_PCM_RATE_96000 |\
167 SNDRV_PCM_RATE_176400 |\
168 SNDRV_PCM_RATE_192000)
170 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
171 SNDRV_PCM_RATE_16000 |\
172 SNDRV_PCM_RATE_32000 |\
173 SNDRV_PCM_RATE_48000)
175 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
176 SNDRV_PCM_FMTBIT_S24_LE |\
177 SNDRV_PCM_FMTBIT_S32_LE)
179 static struct snd_soc_dai_driver mt8183_memif_dai_driver[] = {
180 /* FE DAIs: memory intefaces to CPU */
183 .id = MT8183_MEMIF_DL1,
185 .stream_name = "DL1",
188 .rates = MTK_PCM_RATES,
189 .formats = MTK_PCM_FORMATS,
191 .ops = &mtk_afe_fe_ops,
195 .id = MT8183_MEMIF_DL2,
197 .stream_name = "DL2",
200 .rates = MTK_PCM_RATES,
201 .formats = MTK_PCM_FORMATS,
203 .ops = &mtk_afe_fe_ops,
207 .id = MT8183_MEMIF_DL3,
209 .stream_name = "DL3",
212 .rates = MTK_PCM_RATES,
213 .formats = MTK_PCM_FORMATS,
215 .ops = &mtk_afe_fe_ops,
219 .id = MT8183_MEMIF_VUL12,
221 .stream_name = "UL1",
224 .rates = MTK_PCM_RATES,
225 .formats = MTK_PCM_FORMATS,
227 .ops = &mtk_afe_fe_ops,
231 .id = MT8183_MEMIF_AWB,
233 .stream_name = "UL2",
236 .rates = MTK_PCM_RATES,
237 .formats = MTK_PCM_FORMATS,
239 .ops = &mtk_afe_fe_ops,
243 .id = MT8183_MEMIF_VUL2,
245 .stream_name = "UL3",
248 .rates = MTK_PCM_RATES,
249 .formats = MTK_PCM_FORMATS,
251 .ops = &mtk_afe_fe_ops,
255 .id = MT8183_MEMIF_AWB2,
257 .stream_name = "UL4",
260 .rates = MTK_PCM_RATES,
261 .formats = MTK_PCM_FORMATS,
263 .ops = &mtk_afe_fe_ops,
267 .id = MT8183_MEMIF_MOD_DAI,
269 .stream_name = "UL_MONO_1",
272 .rates = MTK_PCM_DAI_RATES,
273 .formats = MTK_PCM_FORMATS,
275 .ops = &mtk_afe_fe_ops,
279 .id = MT8183_MEMIF_HDMI,
281 .stream_name = "HDMI",
284 .rates = MTK_PCM_RATES,
285 .formats = MTK_PCM_FORMATS,
287 .ops = &mtk_afe_fe_ops,
291 /* dma widget & routes*/
292 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
293 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
294 I_ADDA_UL_CH1, 1, 0),
295 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN21,
299 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
300 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
301 I_ADDA_UL_CH2, 1, 0),
302 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN21,
306 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
307 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
308 I_ADDA_UL_CH1, 1, 0),
309 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
311 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
313 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
315 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5,
319 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
320 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
321 I_ADDA_UL_CH2, 1, 0),
322 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
324 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
326 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
328 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6,
332 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
333 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN32,
334 I_ADDA_UL_CH1, 1, 0),
335 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN32,
339 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
340 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN33,
341 I_ADDA_UL_CH2, 1, 0),
342 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN33,
346 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
347 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,
348 I_ADDA_UL_CH1, 1, 0),
351 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
352 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,
353 I_ADDA_UL_CH2, 1, 0),
356 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
357 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
358 I_ADDA_UL_CH1, 1, 0),
359 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
360 I_ADDA_UL_CH2, 1, 0),
363 static const struct snd_soc_dapm_widget mt8183_memif_widgets[] = {
365 SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
366 memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
367 SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
368 memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
370 SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
371 memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
372 SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
373 memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
375 SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
376 memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
377 SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
378 memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
380 SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
381 memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
382 SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
383 memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
385 SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
387 ARRAY_SIZE(memif_ul_mono_1_mix)),
390 static const struct snd_soc_dapm_route mt8183_memif_routes[] = {
392 {"UL1", NULL, "UL1_CH1"},
393 {"UL1", NULL, "UL1_CH2"},
394 {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
395 {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
396 {"UL1_CH1", "I2S0_CH1", "I2S0"},
397 {"UL1_CH2", "I2S0_CH2", "I2S0"},
399 {"UL2", NULL, "UL2_CH1"},
400 {"UL2", NULL, "UL2_CH2"},
401 {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
402 {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
403 {"UL2_CH1", "I2S2_CH1", "I2S2"},
404 {"UL2_CH2", "I2S2_CH2", "I2S2"},
406 {"UL3", NULL, "UL3_CH1"},
407 {"UL3", NULL, "UL3_CH2"},
408 {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
409 {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
410 {"UL3_CH1", "I2S2_CH1", "I2S2"},
411 {"UL3_CH2", "I2S2_CH2", "I2S2"},
413 {"UL4", NULL, "UL4_CH1"},
414 {"UL4", NULL, "UL4_CH2"},
415 {"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"},
416 {"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"},
418 {"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
419 {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
420 {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
423 static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = {
424 .name = "mt8183-afe-pcm-dai",
427 static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
428 [MT8183_MEMIF_DL1] = {
430 .id = MT8183_MEMIF_DL1,
431 .reg_ofs_base = AFE_DL1_BASE,
432 .reg_ofs_cur = AFE_DL1_CUR,
433 .fs_reg = AFE_DAC_CON1,
434 .fs_shift = DL1_MODE_SFT,
435 .fs_maskbit = DL1_MODE_MASK,
436 .mono_reg = AFE_DAC_CON1,
437 .mono_shift = DL1_DATA_SFT,
438 .enable_reg = AFE_DAC_CON0,
439 .enable_shift = DL1_ON_SFT,
440 .hd_reg = AFE_MEMIF_HD_MODE,
441 .hd_align_reg = AFE_MEMIF_HDALIGN,
442 .hd_shift = DL1_HD_SFT,
443 .hd_align_mshift = DL1_HD_ALIGN_SFT,
444 .agent_disable_reg = -1,
445 .agent_disable_shift = -1,
449 [MT8183_MEMIF_DL2] = {
451 .id = MT8183_MEMIF_DL2,
452 .reg_ofs_base = AFE_DL2_BASE,
453 .reg_ofs_cur = AFE_DL2_CUR,
454 .fs_reg = AFE_DAC_CON1,
455 .fs_shift = DL2_MODE_SFT,
456 .fs_maskbit = DL2_MODE_MASK,
457 .mono_reg = AFE_DAC_CON1,
458 .mono_shift = DL2_DATA_SFT,
459 .enable_reg = AFE_DAC_CON0,
460 .enable_shift = DL2_ON_SFT,
461 .hd_reg = AFE_MEMIF_HD_MODE,
462 .hd_align_reg = AFE_MEMIF_HDALIGN,
463 .hd_shift = DL2_HD_SFT,
464 .hd_align_mshift = DL2_HD_ALIGN_SFT,
465 .agent_disable_reg = -1,
466 .agent_disable_shift = -1,
470 [MT8183_MEMIF_DL3] = {
472 .id = MT8183_MEMIF_DL3,
473 .reg_ofs_base = AFE_DL3_BASE,
474 .reg_ofs_cur = AFE_DL3_CUR,
475 .fs_reg = AFE_DAC_CON2,
476 .fs_shift = DL3_MODE_SFT,
477 .fs_maskbit = DL3_MODE_MASK,
478 .mono_reg = AFE_DAC_CON1,
479 .mono_shift = DL3_DATA_SFT,
480 .enable_reg = AFE_DAC_CON0,
481 .enable_shift = DL3_ON_SFT,
482 .hd_reg = AFE_MEMIF_HD_MODE,
483 .hd_align_reg = AFE_MEMIF_HDALIGN,
484 .hd_shift = DL3_HD_SFT,
485 .hd_align_mshift = DL3_HD_ALIGN_SFT,
486 .agent_disable_reg = -1,
487 .agent_disable_shift = -1,
491 [MT8183_MEMIF_VUL2] = {
493 .id = MT8183_MEMIF_VUL2,
494 .reg_ofs_base = AFE_VUL2_BASE,
495 .reg_ofs_cur = AFE_VUL2_CUR,
496 .fs_reg = AFE_DAC_CON2,
497 .fs_shift = VUL2_MODE_SFT,
498 .fs_maskbit = VUL2_MODE_MASK,
499 .mono_reg = AFE_DAC_CON2,
500 .mono_shift = VUL2_DATA_SFT,
501 .enable_reg = AFE_DAC_CON0,
502 .enable_shift = VUL2_ON_SFT,
503 .hd_reg = AFE_MEMIF_HD_MODE,
504 .hd_align_reg = AFE_MEMIF_HDALIGN,
505 .hd_shift = VUL2_HD_SFT,
506 .hd_align_mshift = VUL2_HD_ALIGN_SFT,
507 .agent_disable_reg = -1,
508 .agent_disable_shift = -1,
512 [MT8183_MEMIF_AWB] = {
514 .id = MT8183_MEMIF_AWB,
515 .reg_ofs_base = AFE_AWB_BASE,
516 .reg_ofs_cur = AFE_AWB_CUR,
517 .fs_reg = AFE_DAC_CON1,
518 .fs_shift = AWB_MODE_SFT,
519 .fs_maskbit = AWB_MODE_MASK,
520 .mono_reg = AFE_DAC_CON1,
521 .mono_shift = AWB_DATA_SFT,
522 .enable_reg = AFE_DAC_CON0,
523 .enable_shift = AWB_ON_SFT,
524 .hd_reg = AFE_MEMIF_HD_MODE,
525 .hd_align_reg = AFE_MEMIF_HDALIGN,
526 .hd_shift = AWB_HD_SFT,
527 .hd_align_mshift = AWB_HD_ALIGN_SFT,
528 .agent_disable_reg = -1,
529 .agent_disable_shift = -1,
533 [MT8183_MEMIF_AWB2] = {
535 .id = MT8183_MEMIF_AWB2,
536 .reg_ofs_base = AFE_AWB2_BASE,
537 .reg_ofs_cur = AFE_AWB2_CUR,
538 .fs_reg = AFE_DAC_CON2,
539 .fs_shift = AWB2_MODE_SFT,
540 .fs_maskbit = AWB2_MODE_MASK,
541 .mono_reg = AFE_DAC_CON2,
542 .mono_shift = AWB2_DATA_SFT,
543 .enable_reg = AFE_DAC_CON0,
544 .enable_shift = AWB2_ON_SFT,
545 .hd_reg = AFE_MEMIF_HD_MODE,
546 .hd_align_reg = AFE_MEMIF_HDALIGN,
547 .hd_shift = AWB2_HD_SFT,
548 .hd_align_mshift = AWB2_ALIGN_SFT,
549 .agent_disable_reg = -1,
550 .agent_disable_shift = -1,
554 [MT8183_MEMIF_VUL12] = {
556 .id = MT8183_MEMIF_VUL12,
557 .reg_ofs_base = AFE_VUL_D2_BASE,
558 .reg_ofs_cur = AFE_VUL_D2_CUR,
559 .fs_reg = AFE_DAC_CON0,
560 .fs_shift = VUL12_MODE_SFT,
561 .fs_maskbit = VUL12_MODE_MASK,
562 .mono_reg = AFE_DAC_CON0,
563 .mono_shift = VUL12_MONO_SFT,
564 .enable_reg = AFE_DAC_CON0,
565 .enable_shift = VUL12_ON_SFT,
566 .hd_reg = AFE_MEMIF_HD_MODE,
567 .hd_align_reg = AFE_MEMIF_HDALIGN,
568 .hd_shift = VUL12_HD_SFT,
569 .hd_align_mshift = VUL12_HD_ALIGN_SFT,
570 .agent_disable_reg = -1,
571 .agent_disable_shift = -1,
575 [MT8183_MEMIF_MOD_DAI] = {
577 .id = MT8183_MEMIF_MOD_DAI,
578 .reg_ofs_base = AFE_MOD_DAI_BASE,
579 .reg_ofs_cur = AFE_MOD_DAI_CUR,
580 .fs_reg = AFE_DAC_CON1,
581 .fs_shift = MOD_DAI_MODE_SFT,
582 .fs_maskbit = MOD_DAI_MODE_MASK,
585 .enable_reg = AFE_DAC_CON0,
586 .enable_shift = MOD_DAI_ON_SFT,
587 .hd_reg = AFE_MEMIF_HD_MODE,
588 .hd_align_reg = AFE_MEMIF_HDALIGN,
589 .hd_shift = MOD_DAI_HD_SFT,
590 .hd_align_mshift = MOD_DAI_HD_ALIGN_SFT,
591 .agent_disable_reg = -1,
592 .agent_disable_shift = -1,
596 [MT8183_MEMIF_HDMI] = {
598 .id = MT8183_MEMIF_HDMI,
599 .reg_ofs_base = AFE_HDMI_OUT_BASE,
600 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
606 .enable_reg = -1, /* control in tdm for sync start */
608 .hd_reg = AFE_MEMIF_HD_MODE,
609 .hd_align_reg = AFE_MEMIF_HDALIGN,
610 .hd_shift = HDMI_HD_SFT,
611 .hd_align_mshift = HDMI_HD_ALIGN_SFT,
612 .agent_disable_reg = -1,
613 .agent_disable_shift = -1,
619 static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
622 .irq_cnt_reg = AFE_IRQ_MCU_CNT0,
624 .irq_cnt_maskbit = 0x3ffff,
625 .irq_fs_reg = AFE_IRQ_MCU_CON1,
626 .irq_fs_shift = IRQ0_MCU_MODE_SFT,
627 .irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
628 .irq_en_reg = AFE_IRQ_MCU_CON0,
629 .irq_en_shift = IRQ0_MCU_ON_SFT,
630 .irq_clr_reg = AFE_IRQ_MCU_CLR,
631 .irq_clr_shift = IRQ0_MCU_CLR_SFT,
635 .irq_cnt_reg = AFE_IRQ_MCU_CNT1,
637 .irq_cnt_maskbit = 0x3ffff,
638 .irq_fs_reg = AFE_IRQ_MCU_CON1,
639 .irq_fs_shift = IRQ1_MCU_MODE_SFT,
640 .irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
641 .irq_en_reg = AFE_IRQ_MCU_CON0,
642 .irq_en_shift = IRQ1_MCU_ON_SFT,
643 .irq_clr_reg = AFE_IRQ_MCU_CLR,
644 .irq_clr_shift = IRQ1_MCU_CLR_SFT,
648 .irq_cnt_reg = AFE_IRQ_MCU_CNT2,
650 .irq_cnt_maskbit = 0x3ffff,
651 .irq_fs_reg = AFE_IRQ_MCU_CON1,
652 .irq_fs_shift = IRQ2_MCU_MODE_SFT,
653 .irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
654 .irq_en_reg = AFE_IRQ_MCU_CON0,
655 .irq_en_shift = IRQ2_MCU_ON_SFT,
656 .irq_clr_reg = AFE_IRQ_MCU_CLR,
657 .irq_clr_shift = IRQ2_MCU_CLR_SFT,
661 .irq_cnt_reg = AFE_IRQ_MCU_CNT3,
663 .irq_cnt_maskbit = 0x3ffff,
664 .irq_fs_reg = AFE_IRQ_MCU_CON1,
665 .irq_fs_shift = IRQ3_MCU_MODE_SFT,
666 .irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
667 .irq_en_reg = AFE_IRQ_MCU_CON0,
668 .irq_en_shift = IRQ3_MCU_ON_SFT,
669 .irq_clr_reg = AFE_IRQ_MCU_CLR,
670 .irq_clr_shift = IRQ3_MCU_CLR_SFT,
674 .irq_cnt_reg = AFE_IRQ_MCU_CNT4,
676 .irq_cnt_maskbit = 0x3ffff,
677 .irq_fs_reg = AFE_IRQ_MCU_CON1,
678 .irq_fs_shift = IRQ4_MCU_MODE_SFT,
679 .irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
680 .irq_en_reg = AFE_IRQ_MCU_CON0,
681 .irq_en_shift = IRQ4_MCU_ON_SFT,
682 .irq_clr_reg = AFE_IRQ_MCU_CLR,
683 .irq_clr_shift = IRQ4_MCU_CLR_SFT,
687 .irq_cnt_reg = AFE_IRQ_MCU_CNT5,
689 .irq_cnt_maskbit = 0x3ffff,
690 .irq_fs_reg = AFE_IRQ_MCU_CON1,
691 .irq_fs_shift = IRQ5_MCU_MODE_SFT,
692 .irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
693 .irq_en_reg = AFE_IRQ_MCU_CON0,
694 .irq_en_shift = IRQ5_MCU_ON_SFT,
695 .irq_clr_reg = AFE_IRQ_MCU_CLR,
696 .irq_clr_shift = IRQ5_MCU_CLR_SFT,
700 .irq_cnt_reg = AFE_IRQ_MCU_CNT6,
702 .irq_cnt_maskbit = 0x3ffff,
703 .irq_fs_reg = AFE_IRQ_MCU_CON1,
704 .irq_fs_shift = IRQ6_MCU_MODE_SFT,
705 .irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
706 .irq_en_reg = AFE_IRQ_MCU_CON0,
707 .irq_en_shift = IRQ6_MCU_ON_SFT,
708 .irq_clr_reg = AFE_IRQ_MCU_CLR,
709 .irq_clr_shift = IRQ6_MCU_CLR_SFT,
713 .irq_cnt_reg = AFE_IRQ_MCU_CNT7,
715 .irq_cnt_maskbit = 0x3ffff,
716 .irq_fs_reg = AFE_IRQ_MCU_CON1,
717 .irq_fs_shift = IRQ7_MCU_MODE_SFT,
718 .irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
719 .irq_en_reg = AFE_IRQ_MCU_CON0,
720 .irq_en_shift = IRQ7_MCU_ON_SFT,
721 .irq_clr_reg = AFE_IRQ_MCU_CLR,
722 .irq_clr_shift = IRQ7_MCU_CLR_SFT,
726 .irq_cnt_reg = AFE_IRQ_MCU_CNT8,
728 .irq_cnt_maskbit = 0x3ffff,
731 .irq_fs_maskbit = -1,
732 .irq_en_reg = AFE_IRQ_MCU_CON0,
733 .irq_en_shift = IRQ8_MCU_ON_SFT,
734 .irq_clr_reg = AFE_IRQ_MCU_CLR,
735 .irq_clr_shift = IRQ8_MCU_CLR_SFT,
739 .irq_cnt_reg = AFE_IRQ_MCU_CNT11,
741 .irq_cnt_maskbit = 0x3ffff,
742 .irq_fs_reg = AFE_IRQ_MCU_CON2,
743 .irq_fs_shift = IRQ11_MCU_MODE_SFT,
744 .irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
745 .irq_en_reg = AFE_IRQ_MCU_CON0,
746 .irq_en_shift = IRQ11_MCU_ON_SFT,
747 .irq_clr_reg = AFE_IRQ_MCU_CLR,
748 .irq_clr_shift = IRQ11_MCU_CLR_SFT,
752 .irq_cnt_reg = AFE_IRQ_MCU_CNT12,
754 .irq_cnt_maskbit = 0x3ffff,
755 .irq_fs_reg = AFE_IRQ_MCU_CON2,
756 .irq_fs_shift = IRQ12_MCU_MODE_SFT,
757 .irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
758 .irq_en_reg = AFE_IRQ_MCU_CON0,
759 .irq_en_shift = IRQ12_MCU_ON_SFT,
760 .irq_clr_reg = AFE_IRQ_MCU_CLR,
761 .irq_clr_shift = IRQ12_MCU_CLR_SFT,
765 static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
767 /* these auto-gen reg has read-only bit, so put it as volatile */
768 /* volatile reg cannot be cached, so cannot be set when power off */
770 case AUDIO_TOP_CON0: /* reg bit controlled by CCF */
771 case AUDIO_TOP_CON1: /* reg bit controlled by CCF */
791 case AFE_ADDA_SRC_DEBUG_MON0:
792 case AFE_ADDA_SRC_DEBUG_MON1:
793 case AFE_ADDA_UL_SRC_MON0:
794 case AFE_ADDA_UL_SRC_MON1:
795 case AFE_SIDETONE_MON:
796 case AFE_SIDETONE_CON0:
797 case AFE_SIDETONE_COEFF:
806 case AFE_IRQ0_MCU_CNT_MON:
807 case AFE_IRQ6_MCU_CNT_MON:
808 case AFE_MOD_DAI_END:
809 case AFE_MOD_DAI_CUR:
814 case AFE_HDMI_OUT_CON0:
815 case AFE_HDMI_OUT_CUR:
816 case AFE_HDMI_OUT_END:
817 case AFE_IRQ3_MCU_CNT_MON:
818 case AFE_IRQ4_MCU_CNT_MON:
819 case AFE_IRQ_MCU_STATUS:
820 case AFE_IRQ_MCU_CLR:
821 case AFE_IRQ_MCU_MON2:
822 case AFE_IRQ1_MCU_CNT_MON:
823 case AFE_IRQ2_MCU_CNT_MON:
824 case AFE_IRQ1_MCU_EN_CNT_MON:
825 case AFE_IRQ5_MCU_CNT_MON:
826 case AFE_IRQ7_MCU_CNT_MON:
829 case AFE_SRAM_DELSEL_CON0:
830 case AFE_SRAM_DELSEL_CON2:
831 case AFE_SRAM_DELSEL_CON3:
832 case AFE_ASRC_2CH_CON12:
833 case AFE_ASRC_2CH_CON13:
839 case AUDIO_TOP_DBG_MON0:
840 case AUDIO_TOP_DBG_MON1:
841 case AFE_IRQ8_MCU_CNT_MON:
842 case AFE_IRQ11_MCU_CNT_MON:
843 case AFE_IRQ12_MCU_CNT_MON:
845 case AFE_CBIP_SLV_MUX_MON0:
846 case AFE_CBIP_SLV_DECODER_MON0:
847 case AFE_ADDA6_SRC_DEBUG_MON0:
848 case AFE_ADD6A_UL_SRC_MON0:
849 case AFE_ADDA6_UL_SRC_MON1:
850 case AFE_DL1_CUR_MSB:
851 case AFE_DL2_CUR_MSB:
852 case AFE_AWB_CUR_MSB:
853 case AFE_VUL_CUR_MSB:
854 case AFE_VUL2_CUR_MSB:
855 case AFE_MOD_DAI_CUR_MSB:
856 case AFE_VUL_D2_CUR_MSB:
857 case AFE_DL3_CUR_MSB:
858 case AFE_HDMI_OUT_CUR_MSB:
861 case AFE_AWB2_CUR_MSB:
862 case AFE_ADDA_DL_SDM_FIFO_MON:
863 case AFE_ADDA_DL_SRC_LCH_MON:
864 case AFE_ADDA_DL_SRC_RCH_MON:
865 case AFE_ADDA_DL_SDM_OUT_MON:
866 case AFE_CONNSYS_I2S_MON:
867 case AFE_ASRC_2CH_CON0:
868 case AFE_ASRC_2CH_CON2:
869 case AFE_ASRC_2CH_CON3:
870 case AFE_ASRC_2CH_CON4:
871 case AFE_ASRC_2CH_CON5:
872 case AFE_ASRC_2CH_CON7:
873 case AFE_ASRC_2CH_CON8:
874 case AFE_MEMIF_MON12:
875 case AFE_MEMIF_MON13:
876 case AFE_MEMIF_MON14:
877 case AFE_MEMIF_MON15:
878 case AFE_MEMIF_MON16:
879 case AFE_MEMIF_MON17:
880 case AFE_MEMIF_MON18:
881 case AFE_MEMIF_MON19:
882 case AFE_MEMIF_MON20:
883 case AFE_MEMIF_MON21:
884 case AFE_MEMIF_MON22:
885 case AFE_MEMIF_MON23:
886 case AFE_MEMIF_MON24:
887 case AFE_ADDA_MTKAIF_MON0:
888 case AFE_ADDA_MTKAIF_MON1:
889 case AFE_AUD_PAD_TOP:
890 case AFE_GENERAL1_ASRC_2CH_CON0:
891 case AFE_GENERAL1_ASRC_2CH_CON2:
892 case AFE_GENERAL1_ASRC_2CH_CON3:
893 case AFE_GENERAL1_ASRC_2CH_CON4:
894 case AFE_GENERAL1_ASRC_2CH_CON5:
895 case AFE_GENERAL1_ASRC_2CH_CON7:
896 case AFE_GENERAL1_ASRC_2CH_CON8:
897 case AFE_GENERAL1_ASRC_2CH_CON12:
898 case AFE_GENERAL1_ASRC_2CH_CON13:
899 case AFE_GENERAL2_ASRC_2CH_CON0:
900 case AFE_GENERAL2_ASRC_2CH_CON2:
901 case AFE_GENERAL2_ASRC_2CH_CON3:
902 case AFE_GENERAL2_ASRC_2CH_CON4:
903 case AFE_GENERAL2_ASRC_2CH_CON5:
904 case AFE_GENERAL2_ASRC_2CH_CON7:
905 case AFE_GENERAL2_ASRC_2CH_CON8:
906 case AFE_GENERAL2_ASRC_2CH_CON12:
907 case AFE_GENERAL2_ASRC_2CH_CON13:
914 static const struct regmap_config mt8183_afe_regmap_config = {
919 .volatile_reg = mt8183_is_volatile_reg,
921 .max_register = AFE_MAX_REGISTER,
922 .num_reg_defaults_raw = AFE_MAX_REGISTER,
924 .cache_type = REGCACHE_FLAT,
927 static irqreturn_t mt8183_afe_irq_handler(int irq_id, void *dev)
929 struct mtk_base_afe *afe = dev;
930 struct mtk_base_afe_irq *irq;
932 unsigned int status_mcu;
936 irqreturn_t irq_ret = IRQ_HANDLED;
938 /* get irq that is sent to MCU */
939 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
941 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
942 /* only care IRQ which is sent to MCU */
943 status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
945 if (ret || status_mcu == 0) {
946 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
947 __func__, ret, status, mcu_en);
953 for (i = 0; i < MT8183_MEMIF_NUM; i++) {
954 struct mtk_base_afe_memif *memif = &afe->memif[i];
956 if (!memif->substream)
959 if (memif->irq_usage < 0)
962 irq = &afe->irqs[memif->irq_usage];
964 if (status_mcu & (1 << irq->irq_data->irq_en_shift))
965 snd_pcm_period_elapsed(memif->substream);
970 regmap_write(afe->regmap,
977 static int mt8183_afe_runtime_suspend(struct device *dev)
979 struct mtk_base_afe *afe = dev_get_drvdata(dev);
980 struct mt8183_afe_private *afe_priv = afe->platform_priv;
984 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
988 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
990 ret = regmap_read_poll_timeout(afe->regmap,
993 (value & AFE_ON_RETM_MASK_SFT) == 0,
997 dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
999 /* make sure all irq status are cleared, twice intended */
1000 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
1001 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
1004 regcache_cache_only(afe->regmap, true);
1005 regcache_mark_dirty(afe->regmap);
1008 return mt8183_afe_disable_clock(afe);
1011 static int mt8183_afe_runtime_resume(struct device *dev)
1013 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1014 struct mt8183_afe_private *afe_priv = afe->platform_priv;
1017 ret = mt8183_afe_enable_clock(afe);
1021 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
1024 regcache_cache_only(afe->regmap, false);
1025 regcache_sync(afe->regmap);
1027 /* enable audio sys DCM for power saving */
1028 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);
1030 /* force cpu use 8_24 format when writing 32bit data */
1031 regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
1032 CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
1034 /* set all output port to 24bit */
1035 regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
1036 regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
1039 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1045 static int mt8183_afe_component_probe(struct snd_soc_component *component)
1047 return mtk_afe_add_sub_dai_control(component);
1050 static const struct snd_soc_component_driver mt8183_afe_component = {
1051 .name = AFE_PCM_NAME,
1052 .probe = mt8183_afe_component_probe,
1053 .pointer = mtk_afe_pcm_pointer,
1054 .pcm_construct = mtk_afe_pcm_new,
1057 static int mt8183_dai_memif_register(struct mtk_base_afe *afe)
1059 struct mtk_base_afe_dai *dai;
1061 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
1065 list_add(&dai->list, &afe->sub_dais);
1067 dai->dai_drivers = mt8183_memif_dai_driver;
1068 dai->num_dai_drivers = ARRAY_SIZE(mt8183_memif_dai_driver);
1070 dai->dapm_widgets = mt8183_memif_widgets;
1071 dai->num_dapm_widgets = ARRAY_SIZE(mt8183_memif_widgets);
1072 dai->dapm_routes = mt8183_memif_routes;
1073 dai->num_dapm_routes = ARRAY_SIZE(mt8183_memif_routes);
1077 typedef int (*dai_register_cb)(struct mtk_base_afe *);
1078 static const dai_register_cb dai_register_cbs[] = {
1079 mt8183_dai_adda_register,
1080 mt8183_dai_i2s_register,
1081 mt8183_dai_pcm_register,
1082 mt8183_dai_tdm_register,
1083 mt8183_dai_hostless_register,
1084 mt8183_dai_memif_register,
1087 static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev)
1089 struct mtk_base_afe *afe;
1090 struct mt8183_afe_private *afe_priv;
1092 struct reset_control *rstc;
1095 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1098 platform_set_drvdata(pdev, afe);
1100 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1102 if (!afe->platform_priv)
1105 afe_priv = afe->platform_priv;
1106 afe->dev = &pdev->dev;
1109 /* initial audio related clock */
1110 ret = mt8183_init_clock(afe);
1112 dev_err(dev, "init clock error\n");
1116 pm_runtime_enable(dev);
1119 afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
1120 if (IS_ERR(afe->regmap)) {
1121 dev_err(dev, "could not get regmap from parent\n");
1122 ret = PTR_ERR(afe->regmap);
1123 goto err_pm_disable;
1125 ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config);
1127 dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
1128 goto err_pm_disable;
1131 rstc = devm_reset_control_get(dev, "audiosys");
1133 ret = PTR_ERR(rstc);
1134 dev_err(dev, "could not get audiosys reset:%d\n", ret);
1135 goto err_pm_disable;
1138 ret = reset_control_reset(rstc);
1140 dev_err(dev, "failed to trigger audio reset:%d\n", ret);
1141 goto err_pm_disable;
1144 /* enable clock for regcache get default value from hw */
1145 afe_priv->pm_runtime_bypass_reg_ctl = true;
1146 pm_runtime_get_sync(&pdev->dev);
1148 ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config);
1150 dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
1151 goto err_pm_disable;
1154 pm_runtime_put_sync(&pdev->dev);
1155 afe_priv->pm_runtime_bypass_reg_ctl = false;
1157 regcache_cache_only(afe->regmap, true);
1158 regcache_mark_dirty(afe->regmap);
1161 afe->memif_size = MT8183_MEMIF_NUM;
1162 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1166 goto err_pm_disable;
1169 for (i = 0; i < afe->memif_size; i++) {
1170 afe->memif[i].data = &memif_data[i];
1171 afe->memif[i].irq_usage = -1;
1174 afe->memif[MT8183_MEMIF_HDMI].irq_usage = MT8183_IRQ_8;
1175 afe->memif[MT8183_MEMIF_HDMI].const_irq = 1;
1177 mutex_init(&afe->irq_alloc_lock);
1180 /* irq initialize */
1181 afe->irqs_size = MT8183_IRQ_NUM;
1182 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1186 goto err_pm_disable;
1189 for (i = 0; i < afe->irqs_size; i++)
1190 afe->irqs[i].irq_data = &irq_data[i];
1193 irq_id = platform_get_irq(pdev, 0);
1196 goto err_pm_disable;
1199 ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler,
1200 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
1202 dev_err(dev, "could not request_irq for asys-isr\n");
1203 goto err_pm_disable;
1207 INIT_LIST_HEAD(&afe->sub_dais);
1209 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
1210 ret = dai_register_cbs[i](afe);
1212 dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
1214 goto err_pm_disable;
1218 /* init dai_driver and component_driver */
1219 ret = mtk_afe_combine_sub_dai(afe);
1221 dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
1223 goto err_pm_disable;
1226 afe->mtk_afe_hardware = &mt8183_afe_hardware;
1227 afe->memif_fs = mt8183_memif_fs;
1228 afe->irq_fs = mt8183_irq_fs;
1230 afe->runtime_resume = mt8183_afe_runtime_resume;
1231 afe->runtime_suspend = mt8183_afe_runtime_suspend;
1233 /* register component */
1234 ret = devm_snd_soc_register_component(&pdev->dev,
1235 &mt8183_afe_component,
1238 dev_warn(dev, "err_platform\n");
1239 goto err_pm_disable;
1242 ret = devm_snd_soc_register_component(afe->dev,
1243 &mt8183_afe_pcm_dai_component,
1245 afe->num_dai_drivers);
1247 dev_warn(dev, "err_dai_component\n");
1248 goto err_pm_disable;
1254 pm_runtime_disable(&pdev->dev);
1258 static int mt8183_afe_pcm_dev_remove(struct platform_device *pdev)
1260 pm_runtime_disable(&pdev->dev);
1261 if (!pm_runtime_status_suspended(&pdev->dev))
1262 mt8183_afe_runtime_suspend(&pdev->dev);
1267 static const struct of_device_id mt8183_afe_pcm_dt_match[] = {
1268 { .compatible = "mediatek,mt8183-audio", },
1271 MODULE_DEVICE_TABLE(of, mt8183_afe_pcm_dt_match);
1273 static const struct dev_pm_ops mt8183_afe_pm_ops = {
1274 SET_RUNTIME_PM_OPS(mt8183_afe_runtime_suspend,
1275 mt8183_afe_runtime_resume, NULL)
1278 static struct platform_driver mt8183_afe_pcm_driver = {
1280 .name = "mt8183-audio",
1281 .of_match_table = mt8183_afe_pcm_dt_match,
1282 .pm = &mt8183_afe_pm_ops,
1284 .probe = mt8183_afe_pcm_dev_probe,
1285 .remove = mt8183_afe_pcm_dev_remove,
1288 module_platform_driver(mt8183_afe_pcm_driver);
1290 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8183");
1291 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
1292 MODULE_LICENSE("GPL v2");