2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
15 #include <linux/init.h>
18 #include <linux/of_device.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
24 #include <linux/clk.h>
25 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <sound/initval.h>
34 #include <sound/dmaengine_pcm.h>
36 #include "jz4740-i2s.h"
38 #define JZ4740_DMA_TYPE_AIC_TRANSMIT 24
39 #define JZ4740_DMA_TYPE_AIC_RECEIVE 25
41 #define JZ_REG_AIC_CONF 0x00
42 #define JZ_REG_AIC_CTRL 0x04
43 #define JZ_REG_AIC_I2S_FMT 0x10
44 #define JZ_REG_AIC_FIFO_STATUS 0x14
45 #define JZ_REG_AIC_I2S_STATUS 0x1c
46 #define JZ_REG_AIC_CLK_DIV 0x30
47 #define JZ_REG_AIC_FIFO 0x34
49 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
50 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
51 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
52 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
53 #define JZ_AIC_CONF_I2S BIT(4)
54 #define JZ_AIC_CONF_RESET BIT(3)
55 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
56 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
57 #define JZ_AIC_CONF_ENABLE BIT(0)
59 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
60 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
61 #define JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24
62 #define JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16
63 #define JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_MASK \
64 (0xf << JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET)
65 #define JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_MASK \
66 (0x1f << JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET)
68 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
69 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
70 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
71 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
72 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
73 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
74 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
75 #define JZ_AIC_CTRL_FLUSH BIT(8)
76 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
77 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
78 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
79 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
80 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
81 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
82 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
84 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
85 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
87 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
88 #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13)
89 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
90 #define JZ_AIC_I2S_FMT_MSB BIT(0)
92 #define JZ_AIC_I2S_STATUS_BUSY BIT(2)
94 #define JZ_AIC_CLK_DIV_MASK 0xf
95 #define I2SDIV_DV_SHIFT 0
96 #define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
97 #define I2SDIV_IDV_SHIFT 8
98 #define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT)
100 enum jz47xx_i2s_version {
106 struct resource *mem;
108 dma_addr_t phys_base;
113 struct snd_dmaengine_dai_dma_data playback_dma_data;
114 struct snd_dmaengine_dai_dma_data capture_dma_data;
116 enum jz47xx_i2s_version version;
119 static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
122 return readl(i2s->base + reg);
125 static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
126 unsigned int reg, uint32_t value)
128 writel(value, i2s->base + reg);
131 static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
132 struct snd_soc_dai *dai)
134 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
141 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
142 ctrl |= JZ_AIC_CTRL_FLUSH;
143 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
145 ret = clk_prepare_enable(i2s->clk_i2s);
149 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
150 conf |= JZ_AIC_CONF_ENABLE;
151 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
156 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
157 struct snd_soc_dai *dai)
159 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
165 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
166 conf &= ~JZ_AIC_CONF_ENABLE;
167 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
169 clk_disable_unprepare(i2s->clk_i2s);
172 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
173 struct snd_soc_dai *dai)
175 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
180 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
181 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
183 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
185 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
188 case SNDRV_PCM_TRIGGER_START:
189 case SNDRV_PCM_TRIGGER_RESUME:
190 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
193 case SNDRV_PCM_TRIGGER_STOP:
194 case SNDRV_PCM_TRIGGER_SUSPEND:
195 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
202 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
207 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
209 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
214 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
216 conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
218 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
219 case SND_SOC_DAIFMT_CBS_CFS:
220 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
221 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
223 case SND_SOC_DAIFMT_CBM_CFS:
224 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
226 case SND_SOC_DAIFMT_CBS_CFM:
227 conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
229 case SND_SOC_DAIFMT_CBM_CFM:
235 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
236 case SND_SOC_DAIFMT_MSB:
237 format |= JZ_AIC_I2S_FMT_MSB;
239 case SND_SOC_DAIFMT_I2S:
245 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
246 case SND_SOC_DAIFMT_NB_NF:
252 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
253 jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
258 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
259 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
261 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
262 unsigned int sample_size;
263 uint32_t ctrl, div_reg;
266 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
268 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
269 div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
271 switch (params_format(params)) {
272 case SNDRV_PCM_FORMAT_S8:
275 case SNDRV_PCM_FORMAT_S16:
282 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
283 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
284 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
285 if (params_channels(params) == 1)
286 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
288 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
290 div_reg &= ~I2SDIV_DV_MASK;
291 div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
293 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
294 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
296 if (i2s->version >= JZ_I2S_JZ4780) {
297 div_reg &= ~I2SDIV_IDV_MASK;
298 div_reg |= (div - 1) << I2SDIV_IDV_SHIFT;
300 div_reg &= ~I2SDIV_DV_MASK;
301 div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
305 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
306 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);
311 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
312 unsigned int freq, int dir)
314 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
319 case JZ4740_I2S_CLKSRC_EXT:
320 parent = clk_get(NULL, "ext");
322 return PTR_ERR(parent);
323 clk_set_parent(i2s->clk_i2s, parent);
325 case JZ4740_I2S_CLKSRC_PLL:
326 parent = clk_get(NULL, "pll half");
328 return PTR_ERR(parent);
329 clk_set_parent(i2s->clk_i2s, parent);
330 ret = clk_set_rate(i2s->clk_i2s, freq);
340 static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
342 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
346 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
347 conf &= ~JZ_AIC_CONF_ENABLE;
348 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
350 clk_disable_unprepare(i2s->clk_i2s);
353 clk_disable_unprepare(i2s->clk_aic);
358 static int jz4740_i2s_resume(struct snd_soc_dai *dai)
360 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
364 ret = clk_prepare_enable(i2s->clk_aic);
369 ret = clk_prepare_enable(i2s->clk_i2s);
371 clk_disable_unprepare(i2s->clk_aic);
375 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
376 conf |= JZ_AIC_CONF_ENABLE;
377 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
383 static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
385 struct snd_dmaengine_dai_dma_data *dma_data;
388 dma_data = &i2s->playback_dma_data;
389 dma_data->maxburst = 16;
390 dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT;
391 dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
394 dma_data = &i2s->capture_dma_data;
395 dma_data->maxburst = 16;
396 dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE;
397 dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
400 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
402 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
406 ret = clk_prepare_enable(i2s->clk_aic);
410 jz4740_i2c_init_pcm_config(i2s);
411 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
412 &i2s->capture_dma_data);
414 if (i2s->version >= JZ_I2S_JZ4780) {
415 conf = (7 << JZ4780_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
416 (8 << JZ4780_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
417 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
419 JZ_AIC_CONF_INTERNAL_CODEC;
421 conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
422 (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
423 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
425 JZ_AIC_CONF_INTERNAL_CODEC;
428 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
429 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
434 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
436 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
438 clk_disable_unprepare(i2s->clk_aic);
442 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
443 .startup = jz4740_i2s_startup,
444 .shutdown = jz4740_i2s_shutdown,
445 .trigger = jz4740_i2s_trigger,
446 .hw_params = jz4740_i2s_hw_params,
447 .set_fmt = jz4740_i2s_set_fmt,
448 .set_sysclk = jz4740_i2s_set_sysclk,
451 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
452 SNDRV_PCM_FMTBIT_S16_LE)
454 static struct snd_soc_dai_driver jz4740_i2s_dai = {
455 .probe = jz4740_i2s_dai_probe,
456 .remove = jz4740_i2s_dai_remove,
460 .rates = SNDRV_PCM_RATE_8000_48000,
461 .formats = JZ4740_I2S_FMTS,
466 .rates = SNDRV_PCM_RATE_8000_48000,
467 .formats = JZ4740_I2S_FMTS,
469 .symmetric_rates = 1,
470 .ops = &jz4740_i2s_dai_ops,
471 .suspend = jz4740_i2s_suspend,
472 .resume = jz4740_i2s_resume,
475 static struct snd_soc_dai_driver jz4780_i2s_dai = {
476 .probe = jz4740_i2s_dai_probe,
477 .remove = jz4740_i2s_dai_remove,
481 .rates = SNDRV_PCM_RATE_8000_48000,
482 .formats = JZ4740_I2S_FMTS,
487 .rates = SNDRV_PCM_RATE_8000_48000,
488 .formats = JZ4740_I2S_FMTS,
490 .ops = &jz4740_i2s_dai_ops,
491 .suspend = jz4740_i2s_suspend,
492 .resume = jz4740_i2s_resume,
495 static const struct snd_soc_component_driver jz4740_i2s_component = {
496 .name = "jz4740-i2s",
500 static const struct of_device_id jz4740_of_matches[] = {
501 { .compatible = "ingenic,jz4740-i2s", .data = (void *)JZ_I2S_JZ4740 },
502 { .compatible = "ingenic,jz4780-i2s", .data = (void *)JZ_I2S_JZ4780 },
505 MODULE_DEVICE_TABLE(of, jz4740_of_matches);
508 static int jz4740_i2s_dev_probe(struct platform_device *pdev)
510 struct jz4740_i2s *i2s;
511 struct resource *mem;
513 const struct of_device_id *match;
515 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
519 match = of_match_device(jz4740_of_matches, &pdev->dev);
521 i2s->version = (enum jz47xx_i2s_version)match->data;
523 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
524 i2s->base = devm_ioremap_resource(&pdev->dev, mem);
525 if (IS_ERR(i2s->base))
526 return PTR_ERR(i2s->base);
528 i2s->phys_base = mem->start;
530 i2s->clk_aic = devm_clk_get(&pdev->dev, "aic");
531 if (IS_ERR(i2s->clk_aic))
532 return PTR_ERR(i2s->clk_aic);
534 i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s");
535 if (IS_ERR(i2s->clk_i2s))
536 return PTR_ERR(i2s->clk_i2s);
538 platform_set_drvdata(pdev, i2s);
540 if (i2s->version == JZ_I2S_JZ4780)
541 ret = devm_snd_soc_register_component(&pdev->dev,
542 &jz4740_i2s_component, &jz4780_i2s_dai, 1);
544 ret = devm_snd_soc_register_component(&pdev->dev,
545 &jz4740_i2s_component, &jz4740_i2s_dai, 1);
550 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
551 SND_DMAENGINE_PCM_FLAG_COMPAT);
554 static struct platform_driver jz4740_i2s_driver = {
555 .probe = jz4740_i2s_dev_probe,
557 .name = "jz4740-i2s",
558 .of_match_table = of_match_ptr(jz4740_of_matches)
562 module_platform_driver(jz4740_i2s_driver);
564 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
565 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
566 MODULE_LICENSE("GPL");
567 MODULE_ALIAS("platform:jz4740-i2s");