2 * skl-tplg-interface.h - Intel DSP FW private data interface
4 * Copyright (C) 2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 * Nilofer, Samreen <samreen.nilofer@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
19 #ifndef __HDA_TPLG_INTERFACE_H__
20 #define __HDA_TPLG_INTERFACE_H__
23 * Default types range from 0~12. type can range from 0 to 0xff
24 * SST types start at higher to avoid any overlapping in future
26 #define SKL_CONTROL_TYPE_BYTE_TLV 0x100
27 #define SKL_CONTROL_TYPE_MIC_SELECT 0x102
29 #define HDA_SST_CFG_MAX 900 /* size of copier cfg*/
30 #define MAX_IN_QUEUE 8
31 #define MAX_OUT_QUEUE 8
33 #define SKL_UUID_STR_SZ 40
34 /* Event types goes here */
35 /* Reserve event type 0 for no event handlers */
36 enum skl_event_types {
45 * enum skl_ch_cfg - channel configuration
47 * @SKL_CH_CFG_MONO: One channel only
48 * @SKL_CH_CFG_STEREO: L & R
49 * @SKL_CH_CFG_2_1: L, R & LFE
50 * @SKL_CH_CFG_3_0: L, C & R
51 * @SKL_CH_CFG_3_1: L, C, R & LFE
52 * @SKL_CH_CFG_QUATRO: L, R, Ls & Rs
53 * @SKL_CH_CFG_4_0: L, C, R & Cs
54 * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs
55 * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE
56 * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
57 * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
58 * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
59 * @SKL_CH_CFG_INVALID: Invalid
63 SKL_CH_CFG_STEREO = 1,
67 SKL_CH_CFG_QUATRO = 5,
71 SKL_CH_CFG_DUAL_MONO = 9,
72 SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
73 SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
75 SKL_CH_CFG_4_CHANNEL = SKL_CH_CFG_7_1,
79 enum skl_module_type {
80 SKL_MODULE_TYPE_MIXER = 0,
81 SKL_MODULE_TYPE_COPIER,
82 SKL_MODULE_TYPE_UPDWMIX,
83 SKL_MODULE_TYPE_SRCINT,
85 SKL_MODULE_TYPE_BASE_OUTFMT,
87 SKL_MODULE_TYPE_MIC_SELECT,
90 enum skl_core_affinity {
91 SKL_AFFINITY_CORE_0 = 0,
96 enum skl_pipe_conn_type {
97 SKL_PIPE_CONN_TYPE_NONE = 0,
98 SKL_PIPE_CONN_TYPE_FE,
102 enum skl_hw_conn_type {
110 SKL_DEVICE_DMIC = 0x1,
111 SKL_DEVICE_I2S = 0x2,
112 SKL_DEVICE_SLIMBUS = 0x3,
113 SKL_DEVICE_HDALINK = 0x4,
114 SKL_DEVICE_HDAHOST = 0x5,
119 * enum skl_interleaving - interleaving style
121 * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN]
122 * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN]
124 enum skl_interleaving {
125 SKL_INTERLEAVING_PER_CHANNEL = 0,
126 SKL_INTERLEAVING_PER_SAMPLE = 1,
129 enum skl_sample_type {
130 SKL_SAMPLE_TYPE_INT_MSB = 0,
131 SKL_SAMPLE_TYPE_INT_LSB = 1,
132 SKL_SAMPLE_TYPE_INT_SIGNED = 2,
133 SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
134 SKL_SAMPLE_TYPE_FLOAT = 4
137 enum module_pin_type {
138 /* All pins of the module takes same PCM inputs or outputs
141 SKL_PIN_TYPE_HOMOGENEOUS,
142 /* All pins of the module takes different PCM inputs or outputs
145 SKL_PIN_TYPE_HETEROGENEOUS,
148 enum skl_module_param_type {
149 SKL_PARAM_DEFAULT = 0,
155 struct skl_dfw_algo_data {
168 enum skl_tuple_type {