1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * skl_topology.h - Intel HDA Platform topology header file
5 * Copyright (C) 2014-15 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12 #ifndef __SKL_TOPOLOGY_H__
13 #define __SKL_TOPOLOGY_H__
15 #include <linux/types.h>
17 #include <sound/hdaudio_ext.h>
18 #include <sound/soc.h>
19 #include <uapi/sound/skl-tplg-interface.h>
22 #define BITS_PER_BYTE 8
23 #define MAX_TS_GROUPS 8
24 #define MAX_DMIC_TS_GROUPS 4
25 #define MAX_FIXED_DMIC_PARAMS_SIZE 727
27 /* Maximum number of coefficients up down mixer module */
28 #define UP_DOWN_MIXER_MAX_COEFF 8
30 #define MODULE_MAX_IN_PINS 8
31 #define MODULE_MAX_OUT_PINS 8
33 #define SKL_MIC_CH_SUPPORT 4
34 #define SKL_MIC_MAX_CH_SUPPORT 8
35 #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF
36 #define SKL_MIC_SEL_SWITCH 0x3
38 #define SKL_OUTPUT_PIN 0
39 #define SKL_INPUT_PIN 1
40 #define SKL_MAX_PATH_CONFIGS 8
41 #define SKL_MAX_MODULES_IN_PIPE 8
42 #define SKL_MAX_MODULE_FORMATS 32
43 #define SKL_MAX_MODULE_RESOURCES 32
45 enum skl_channel_index {
47 SKL_CHANNEL_RIGHT = 1,
48 SKL_CHANNEL_CENTER = 2,
49 SKL_CHANNEL_LEFT_SURROUND = 3,
50 SKL_CHANNEL_CENTER_SURROUND = 3,
51 SKL_CHANNEL_RIGHT_SURROUND = 4,
53 SKL_CHANNEL_INVALID = 0xF,
78 SKL_FS_128000 = 128000,
79 SKL_FS_176400 = 176400,
80 SKL_FS_192000 = 192000,
84 #define SKL_MAX_PARAMS_TYPES 4
86 enum skl_widget_type {
87 SKL_WIDGET_VMIXER = 1,
93 struct skl_audio_data_format {
94 enum skl_s_freq s_freq;
95 enum skl_bitdepth bit_depth;
97 enum skl_ch_cfg ch_cfg;
98 enum skl_interleaving interleaving;
99 u8 number_of_channels;
105 struct skl_base_cfg {
110 struct skl_audio_data_format audio_fmt;
113 struct skl_cpr_gtw_cfg {
117 /* not mandatory; required only for DMIC/I2S */
124 struct skl_dma_control {
131 struct skl_base_cfg base_cfg;
132 struct skl_audio_data_format out_fmt;
133 u32 cpr_feature_mask;
134 struct skl_cpr_gtw_cfg gtw_cfg;
137 struct skl_cpr_pin_fmt {
139 struct skl_audio_data_format src_fmt;
140 struct skl_audio_data_format dst_fmt;
143 struct skl_src_module_cfg {
144 struct skl_base_cfg base_cfg;
145 enum skl_s_freq src_cfg;
148 struct skl_up_down_mixer_cfg {
149 struct skl_base_cfg base_cfg;
150 enum skl_ch_cfg out_ch_cfg;
151 /* This should be set to 1 if user coefficients are required */
153 /* Pass the user coeff in this array */
154 s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
158 struct skl_pin_format {
161 struct skl_audio_data_format audio_fmt;
164 struct skl_base_cfg_ext {
168 u32 priv_param_length;
169 /* Input pin formats followed by output ones. */
170 struct skl_pin_format pins_fmt[];
173 struct skl_algo_cfg {
174 struct skl_base_cfg base_cfg;
178 struct skl_base_outfmt_cfg {
179 struct skl_base_cfg base_cfg;
180 struct skl_audio_data_format out_fmt;
184 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
185 SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
186 SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
187 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
188 SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
189 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
190 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
191 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
192 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
195 union skl_ssp_dma_node {
198 u8 time_slot_index:4;
203 union skl_connector_node_id {
212 struct skl_module_fmt {
218 u32 interleaving_style;
223 struct skl_module_cfg;
225 struct skl_mod_inst_map {
230 struct skl_uuid_inst_map {
236 struct skl_kpb_params {
239 DECLARE_FLEX_ARRAY(struct skl_mod_inst_map, map);
240 DECLARE_FLEX_ARRAY(struct skl_uuid_inst_map, map_uuid);
244 struct skl_module_inst_id {
251 enum skl_module_pin_state {
253 SKL_PIN_BIND_DONE = 1,
256 struct skl_module_pin {
257 struct skl_module_inst_id id;
260 enum skl_module_pin_state pin_state;
261 struct skl_module_cfg *tgt_mcfg;
264 struct skl_specific_cfg {
271 enum skl_pipe_state {
272 SKL_PIPE_INVALID = 0,
273 SKL_PIPE_CREATED = 1,
275 SKL_PIPE_STARTED = 3,
279 struct skl_pipe_module {
280 struct snd_soc_dapm_widget *w;
281 struct list_head node;
284 struct skl_pipe_params {
292 snd_pcm_format_t format;
295 unsigned int host_bps;
296 unsigned int link_bps;
299 struct skl_pipe_fmt {
305 struct skl_pipe_mcfg {
310 struct skl_path_config {
312 struct skl_pipe_fmt in_fmt;
313 struct skl_pipe_fmt out_fmt;
322 struct skl_pipe_params *p_params;
323 enum skl_pipe_state state;
327 struct skl_path_config configs[SKL_MAX_PATH_CONFIGS];
328 struct list_head w_list;
332 enum skl_module_state {
333 SKL_MODULE_UNINIT = 0,
334 SKL_MODULE_INIT_DONE = 1,
335 SKL_MODULE_BIND_DONE = 2,
338 enum d0i3_capability {
340 SKL_D0I3_STREAMING = 1,
341 SKL_D0I3_NON_STREAMING = 2,
344 struct skl_module_pin_fmt {
346 struct skl_module_fmt fmt;
349 struct skl_module_iface {
353 struct skl_module_pin_fmt inputs[MAX_IN_QUEUE];
354 struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE];
357 struct skl_module_pin_resources {
362 struct skl_module_res {
371 struct skl_module_pin_resources input[MAX_IN_QUEUE];
372 struct skl_module_pin_resources output[MAX_OUT_QUEUE];
384 struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES];
385 struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS];
388 struct skl_module_cfg {
390 struct skl_module_inst_id id;
391 struct skl_module *module;
396 bool homogenous_inputs;
397 bool homogenous_outputs;
398 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
399 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
411 u8 dmic_ch_combo_index;
417 enum d0i3_capability d0i3_caps;
418 u32 dma_buffer_size; /* in milli seconds */
419 struct skl_module_pin *m_in_pin;
420 struct skl_module_pin *m_out_pin;
421 enum skl_module_type m_type;
422 enum skl_hw_conn_type hw_conn_type;
423 enum skl_module_state m_state;
424 struct skl_pipe *pipe;
425 struct skl_specific_cfg formats_config[SKL_MAX_PARAMS_TYPES];
426 struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE];
429 struct skl_algo_data {
437 struct skl_pipeline {
438 struct skl_pipe *pipe;
439 struct list_head node;
442 struct skl_module_deferred_bind {
443 struct skl_module_cfg *src;
444 struct skl_module_cfg *dst;
445 struct list_head node;
448 struct skl_mic_sel_config {
451 u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT];
461 static inline struct skl_dev *get_skl_ctx(struct device *dev)
463 struct hdac_bus *bus = dev_get_drvdata(dev);
465 return bus_to_skl(bus);
468 int skl_tplg_be_update_params(struct snd_soc_dai *dai,
469 struct skl_pipe_params *params);
470 int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps,
471 u32 caps_size, u32 node_id);
472 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
473 struct skl_pipe_params *params, int stream);
474 int skl_tplg_init(struct snd_soc_component *component,
475 struct hdac_bus *bus);
476 void skl_tplg_exit(struct snd_soc_component *component,
477 struct hdac_bus *bus);
478 struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
479 struct snd_soc_dai *dai, int stream);
480 int skl_tplg_update_pipe_params(struct device *dev,
481 struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
483 void skl_tplg_d0i3_get(struct skl_dev *skl, enum d0i3_capability caps);
484 void skl_tplg_d0i3_put(struct skl_dev *skl, enum d0i3_capability caps);
486 int skl_create_pipeline(struct skl_dev *skl, struct skl_pipe *pipe);
488 int skl_run_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
490 int skl_pause_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
492 int skl_delete_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
494 int skl_stop_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
496 int skl_reset_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
498 int skl_init_module(struct skl_dev *skl, struct skl_module_cfg *mconfig);
500 int skl_bind_modules(struct skl_dev *skl, struct skl_module_cfg
501 *src_mcfg, struct skl_module_cfg *dst_mcfg);
503 int skl_unbind_modules(struct skl_dev *skl, struct skl_module_cfg
504 *src_mcfg, struct skl_module_cfg *dst_mcfg);
506 int skl_set_module_params(struct skl_dev *skl, u32 *params, int size,
507 u32 param_id, struct skl_module_cfg *mcfg);
508 int skl_get_module_params(struct skl_dev *skl, u32 *params, int size,
509 u32 param_id, struct skl_module_cfg *mcfg);
511 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
513 enum skl_bitdepth skl_get_bit_depth(int params);
514 int skl_pcm_host_dma_prepare(struct device *dev,
515 struct skl_pipe_params *params);
516 int skl_pcm_link_dma_prepare(struct device *dev,
517 struct skl_pipe_params *params);
519 int skl_dai_load(struct snd_soc_component *cmp, int index,
520 struct snd_soc_dai_driver *dai_drv,
521 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai);
522 void skl_tplg_add_moduleid_in_bind_params(struct skl_dev *skl,
523 struct snd_soc_dapm_widget *w);