2 * skl_topology.h - Intel HDA Platform topology header file
4 * Copyright (C) 2014-15 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 #ifndef __SKL_TOPOLOGY_H__
22 #define __SKL_TOPOLOGY_H__
24 #include <linux/types.h>
26 #include <sound/hdaudio_ext.h>
27 #include <sound/soc.h>
28 #include <uapi/sound/skl-tplg-interface.h>
31 #define BITS_PER_BYTE 8
32 #define MAX_TS_GROUPS 8
33 #define MAX_DMIC_TS_GROUPS 4
34 #define MAX_FIXED_DMIC_PARAMS_SIZE 727
36 /* Maximum number of coefficients up down mixer module */
37 #define UP_DOWN_MIXER_MAX_COEFF 8
39 #define MODULE_MAX_IN_PINS 8
40 #define MODULE_MAX_OUT_PINS 8
42 #define SKL_MIC_CH_SUPPORT 4
43 #define SKL_MIC_MAX_CH_SUPPORT 8
44 #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF
45 #define SKL_MIC_SEL_SWITCH 0x3
47 #define SKL_OUTPUT_PIN 0
48 #define SKL_INPUT_PIN 1
49 #define SKL_MAX_PATH_CONFIGS 8
50 #define SKL_MAX_MODULES_IN_PIPE 8
51 #define SKL_MAX_MODULE_FORMATS 32
52 #define SKL_MAX_MODULE_RESOURCES 32
54 enum skl_channel_index {
56 SKL_CHANNEL_RIGHT = 1,
57 SKL_CHANNEL_CENTER = 2,
58 SKL_CHANNEL_LEFT_SURROUND = 3,
59 SKL_CHANNEL_CENTER_SURROUND = 3,
60 SKL_CHANNEL_RIGHT_SURROUND = 4,
62 SKL_CHANNEL_INVALID = 0xF,
87 SKL_FS_128000 = 128000,
88 SKL_FS_176400 = 176400,
89 SKL_FS_192000 = 192000,
93 enum skl_widget_type {
94 SKL_WIDGET_VMIXER = 1,
100 struct skl_audio_data_format {
101 enum skl_s_freq s_freq;
102 enum skl_bitdepth bit_depth;
104 enum skl_ch_cfg ch_cfg;
105 enum skl_interleaving interleaving;
106 u8 number_of_channels;
112 struct skl_base_cfg {
117 struct skl_audio_data_format audio_fmt;
120 struct skl_cpr_gtw_cfg {
124 /* not mandatory; required only for DMIC/I2S */
128 struct skl_dma_control {
135 struct skl_base_cfg base_cfg;
136 struct skl_audio_data_format out_fmt;
137 u32 cpr_feature_mask;
138 struct skl_cpr_gtw_cfg gtw_cfg;
141 struct skl_cpr_pin_fmt {
143 struct skl_audio_data_format src_fmt;
144 struct skl_audio_data_format dst_fmt;
147 struct skl_src_module_cfg {
148 struct skl_base_cfg base_cfg;
149 enum skl_s_freq src_cfg;
152 struct notification_mask {
157 struct skl_up_down_mixer_cfg {
158 struct skl_base_cfg base_cfg;
159 enum skl_ch_cfg out_ch_cfg;
160 /* This should be set to 1 if user coefficients are required */
162 /* Pass the user coeff in this array */
163 s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
167 struct skl_algo_cfg {
168 struct skl_base_cfg base_cfg;
172 struct skl_base_outfmt_cfg {
173 struct skl_base_cfg base_cfg;
174 struct skl_audio_data_format out_fmt;
178 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
179 SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
180 SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
181 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
182 SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
183 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
184 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
185 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
186 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
189 union skl_ssp_dma_node {
192 u8 time_slot_index:4;
197 union skl_connector_node_id {
206 struct skl_module_fmt {
212 u32 interleaving_style;
217 struct skl_module_cfg;
219 struct skl_mod_inst_map {
224 struct skl_uuid_inst_map {
230 struct skl_kpb_params {
233 struct skl_mod_inst_map map[0];
234 struct skl_uuid_inst_map map_uuid[0];
238 struct skl_module_inst_id {
245 enum skl_module_pin_state {
247 SKL_PIN_BIND_DONE = 1,
250 struct skl_module_pin {
251 struct skl_module_inst_id id;
254 enum skl_module_pin_state pin_state;
255 struct skl_module_cfg *tgt_mcfg;
258 struct skl_specific_cfg {
265 enum skl_pipe_state {
266 SKL_PIPE_INVALID = 0,
267 SKL_PIPE_CREATED = 1,
269 SKL_PIPE_STARTED = 3,
273 struct skl_pipe_module {
274 struct snd_soc_dapm_widget *w;
275 struct list_head node;
278 struct skl_pipe_params {
285 snd_pcm_format_t format;
288 unsigned int host_bps;
289 unsigned int link_bps;
292 struct skl_pipe_fmt {
298 struct skl_pipe_mcfg {
303 struct skl_path_config {
305 struct skl_pipe_fmt in_fmt;
306 struct skl_pipe_fmt out_fmt;
315 struct skl_pipe_params *p_params;
316 enum skl_pipe_state state;
320 struct skl_path_config configs[SKL_MAX_PATH_CONFIGS];
321 struct list_head w_list;
325 enum skl_module_state {
326 SKL_MODULE_UNINIT = 0,
327 SKL_MODULE_LOADED = 1,
328 SKL_MODULE_INIT_DONE = 2,
329 SKL_MODULE_BIND_DONE = 3,
330 SKL_MODULE_UNLOADED = 4,
333 enum d0i3_capability {
335 SKL_D0I3_STREAMING = 1,
336 SKL_D0I3_NON_STREAMING = 2,
339 struct skl_module_pin_fmt {
341 struct skl_module_fmt fmt;
344 struct skl_module_iface {
348 struct skl_module_pin_fmt inputs[MAX_IN_QUEUE];
349 struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE];
352 struct skl_module_pin_resources {
357 struct skl_module_res {
367 struct skl_module_pin_resources input[MAX_IN_QUEUE];
368 struct skl_module_pin_resources output[MAX_OUT_QUEUE];
380 struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES];
381 struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS];
384 struct skl_module_cfg {
386 struct skl_module_inst_id id;
387 struct skl_module *module;
391 bool homogenous_inputs;
392 bool homogenous_outputs;
393 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
394 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
409 u8 dmic_ch_combo_index;
415 enum d0i3_capability d0i3_caps;
416 u32 dma_buffer_size; /* in milli seconds */
417 struct skl_module_pin *m_in_pin;
418 struct skl_module_pin *m_out_pin;
419 enum skl_module_type m_type;
420 enum skl_hw_conn_type hw_conn_type;
421 enum skl_module_state m_state;
422 struct skl_pipe *pipe;
423 struct skl_specific_cfg formats_config;
424 struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE];
427 struct skl_algo_data {
435 struct skl_pipeline {
436 struct skl_pipe *pipe;
437 struct list_head node;
440 struct skl_module_deferred_bind {
441 struct skl_module_cfg *src;
442 struct skl_module_cfg *dst;
443 struct list_head node;
446 struct skl_mic_sel_config {
449 u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT];
459 static inline struct skl *get_skl_ctx(struct device *dev)
461 struct hdac_bus *bus = dev_get_drvdata(dev);
463 return bus_to_skl(bus);
466 int skl_tplg_be_update_params(struct snd_soc_dai *dai,
467 struct skl_pipe_params *params);
468 int skl_dsp_set_dma_control(struct skl_sst *ctx, u32 *caps,
469 u32 caps_size, u32 node_id);
470 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
471 struct skl_pipe_params *params, int stream);
472 int skl_tplg_init(struct snd_soc_component *component,
473 struct hdac_bus *ebus);
474 struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
475 struct snd_soc_dai *dai, int stream);
476 int skl_tplg_update_pipe_params(struct device *dev,
477 struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
479 void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps);
480 void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps);
482 int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe);
484 int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
486 int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
488 int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
490 int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
492 int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
494 int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config);
496 int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg
497 *src_module, struct skl_module_cfg *dst_module);
499 int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg
500 *src_module, struct skl_module_cfg *dst_module);
502 int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
503 u32 param_id, struct skl_module_cfg *mcfg);
504 int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size,
505 u32 param_id, struct skl_module_cfg *mcfg);
507 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
509 enum skl_bitdepth skl_get_bit_depth(int params);
510 int skl_pcm_host_dma_prepare(struct device *dev,
511 struct skl_pipe_params *params);
512 int skl_pcm_link_dma_prepare(struct device *dev,
513 struct skl_pipe_params *params);
515 int skl_dai_load(struct snd_soc_component *cmp, int index,
516 struct snd_soc_dai_driver *dai_drv,
517 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai);
518 void skl_tplg_add_moduleid_in_bind_params(struct skl *skl,
519 struct snd_soc_dapm_widget *w);