2 * skl-sst.c - HDA DSP library functions for SKL platform
4 * Copyright (C) 2014-15, Intel Corporation.
5 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
6 * Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/delay.h>
21 #include <linux/device.h>
22 #include "../common/sst-dsp.h"
23 #include "../common/sst-dsp-priv.h"
24 #include "../common/sst-ipc.h"
25 #include "skl-sst-ipc.h"
27 #define SKL_BASEFW_TIMEOUT 300
28 #define SKL_INIT_TIMEOUT 1000
30 /* Intel HD Audio SRAM Window 0*/
31 #define SKL_ADSP_SRAM0_BASE 0x8000
33 /* Firmware status window */
34 #define SKL_ADSP_FW_STATUS SKL_ADSP_SRAM0_BASE
35 #define SKL_ADSP_ERROR_CODE (SKL_ADSP_FW_STATUS + 0x4)
37 #define SKL_INSTANCE_ID 0
38 #define SKL_BASE_FW_MODULE_ID 0
40 static bool skl_check_fw_status(struct sst_dsp *ctx, u32 status)
44 cur_sts = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS) & SKL_FW_STS_MASK;
46 return (cur_sts == status);
49 static int skl_transfer_firmware(struct sst_dsp *ctx,
50 const void *basefw, u32 base_fw_size)
54 ret = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, basefw, base_fw_size);
58 ret = sst_dsp_register_poll(ctx,
65 ctx->cl_dev.ops.cl_stop_dma(ctx);
70 static int skl_load_base_firmware(struct sst_dsp *ctx)
73 struct skl_sst *skl = ctx->thread_context;
76 skl->boot_complete = false;
77 init_waitqueue_head(&skl->boot_wait);
79 if (ctx->fw == NULL) {
80 ret = reject_firmware(&ctx->fw, "/*(DEBLOBBED)*/", ctx->dev);
82 dev_err(ctx->dev, "Request firmware failed %d\n", ret);
83 skl_dsp_disable_core(ctx);
88 ret = skl_dsp_boot(ctx);
90 dev_err(ctx->dev, "Boot dsp core failed ret: %d", ret);
91 goto skl_load_base_firmware_failed;
94 ret = skl_cldma_prepare(ctx);
96 dev_err(ctx->dev, "CL dma prepare failed : %d", ret);
97 goto skl_load_base_firmware_failed;
100 /* enable Interrupt */
101 skl_ipc_int_enable(ctx);
102 skl_ipc_op_int_enable(ctx);
104 /* check ROM Status */
105 for (i = SKL_INIT_TIMEOUT; i > 0; --i) {
106 if (skl_check_fw_status(ctx, SKL_FW_INIT)) {
108 "ROM loaded, we can continue with FW loading\n");
114 reg = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS);
116 "Timeout waiting for ROM init done, reg:0x%x\n", reg);
118 goto skl_load_base_firmware_failed;
121 ret = skl_transfer_firmware(ctx, ctx->fw->data, ctx->fw->size);
123 dev_err(ctx->dev, "Transfer firmware failed%d\n", ret);
124 goto skl_load_base_firmware_failed;
126 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
127 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
129 dev_err(ctx->dev, "DSP boot failed, FW Ready timed-out\n");
131 goto skl_load_base_firmware_failed;
134 dev_dbg(ctx->dev, "Download firmware successful%d\n", ret);
135 skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
139 skl_load_base_firmware_failed:
140 skl_dsp_disable_core(ctx);
141 release_firmware(ctx->fw);
146 static int skl_set_dsp_D0(struct sst_dsp *ctx)
150 ret = skl_load_base_firmware(ctx);
152 dev_err(ctx->dev, "unable to load firmware\n");
156 skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
161 static int skl_set_dsp_D3(struct sst_dsp *ctx)
164 struct skl_ipc_dxstate_info dx;
165 struct skl_sst *skl = ctx->thread_context;
167 dev_dbg(ctx->dev, "In %s:\n", __func__);
168 mutex_lock(&ctx->mutex);
169 if (!is_skl_dsp_running(ctx)) {
170 mutex_unlock(&ctx->mutex);
173 mutex_unlock(&ctx->mutex);
175 dx.core_mask = SKL_DSP_CORE0_MASK;
176 dx.dx_mask = SKL_IPC_D3_MASK;
177 ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID, SKL_BASE_FW_MODULE_ID, &dx);
179 dev_err(ctx->dev, "Failed to set DSP to D3 state\n");
183 ret = skl_dsp_disable_core(ctx);
185 dev_err(ctx->dev, "disable dsp core failed ret: %d\n", ret);
188 skl_dsp_set_state_locked(ctx, SKL_DSP_RESET);
190 /* disable Interrupt */
191 ctx->cl_dev.ops.cl_cleanup_controller(ctx);
192 skl_cldma_int_disable(ctx);
193 skl_ipc_op_int_disable(ctx);
194 skl_ipc_int_disable(ctx);
199 static unsigned int skl_get_errorcode(struct sst_dsp *ctx)
201 return sst_dsp_shim_read(ctx, SKL_ADSP_ERROR_CODE);
204 static struct skl_dsp_fw_ops skl_fw_ops = {
205 .set_state_D0 = skl_set_dsp_D0,
206 .set_state_D3 = skl_set_dsp_D3,
207 .load_fw = skl_load_base_firmware,
208 .get_fw_errcode = skl_get_errorcode,
211 static struct sst_ops skl_ops = {
212 .irq_handler = skl_dsp_sst_interrupt,
213 .write = sst_shim32_write,
214 .read = sst_shim32_read,
215 .ram_read = sst_memcpy_fromio_32,
216 .ram_write = sst_memcpy_toio_32,
217 .free = skl_dsp_free,
220 static struct sst_dsp_device skl_dev = {
221 .thread = skl_dsp_irq_thread_handler,
225 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
226 struct skl_dsp_loader_ops dsp_ops, struct skl_sst **dsp)
232 skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL);
237 skl_dev.thread_context = skl;
239 skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq);
241 dev_err(skl->dev, "%s: no device\n", __func__);
247 sst->addr.lpe = mmio_base;
248 sst->addr.shim = mmio_base;
249 sst_dsp_mailbox_init(sst, (SKL_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
250 SKL_ADSP_W0_UP_SZ, SKL_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
252 sst->dsp_ops = dsp_ops;
253 sst->fw_ops = skl_fw_ops;
255 ret = skl_ipc_init(dev, skl);
259 ret = sst->fw_ops.load_fw(sst);
261 dev_err(dev, "Load base fw failed : %d", ret);
270 skl_ipc_free(&skl->ipc);
273 EXPORT_SYMBOL_GPL(skl_sst_dsp_init);
275 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
277 skl_ipc_free(&ctx->ipc);
278 ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);
279 ctx->dsp->ops->free(ctx->dsp);
281 EXPORT_SYMBOL_GPL(skl_sst_dsp_cleanup);
283 MODULE_LICENSE("GPL v2");
284 MODULE_DESCRIPTION("Intel Skylake IPC driver");