sound/soc/intel/skylake/skl-pcm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
   4  *
   5  *  Copyright (C) 2014-2015 Intel Corp
   6  *  Author:  Jeeja KP <jeeja.kp@intel.com>
   7  *
   8  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   9  *
  10  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/delay.h>
  16 #include <sound/hdaudio.h>
  17 #include <sound/pcm_params.h>
  18 #include <sound/soc.h>
  19 #include "skl.h"
  20 #include "skl-topology.h"
  21 #include "skl-sst-dsp.h"
  22 #include "skl-sst-ipc.h"
  23
  24 #define HDA_MONO 1
  25 #define HDA_STEREO 2
  26 #define HDA_QUAD 4
  27 #define HDA_MAX 8
  28
  29 static const struct snd_pcm_hardware azx_pcm_hw = {
  30         .info =                 (SNDRV_PCM_INFO_MMAP |
  31                                  SNDRV_PCM_INFO_INTERLEAVED |
  32                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
  33                                  SNDRV_PCM_INFO_MMAP_VALID |
  34                                  SNDRV_PCM_INFO_PAUSE |
  35                                  SNDRV_PCM_INFO_RESUME |
  36                                  SNDRV_PCM_INFO_SYNC_START |
  37                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
  38                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
  39                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
  40         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
  41                                 SNDRV_PCM_FMTBIT_S32_LE |
  42                                 SNDRV_PCM_FMTBIT_S24_LE,
  43         .rates =                SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
  44                                 SNDRV_PCM_RATE_8000,
  45         .rate_min =             8000,
  46         .rate_max =             48000,
  47         .channels_min =         1,
  48         .channels_max =         8,
  49         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
  50         .period_bytes_min =     128,
  51         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
  52         .periods_min =          2,
  53         .periods_max =          AZX_MAX_FRAG,
  54         .fifo_size =            0,
  55 };
  56
  57 static inline
  58 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
  59 {
  60         return substream->runtime->private_data;
  61 }
  62
  63 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
  64 {
  65         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  66         struct hdac_stream *hstream = hdac_stream(stream);
  67         struct hdac_bus *bus = hstream->bus;
  68         return bus;
  69 }
  70
  71 static int skl_substream_alloc_pages(struct hdac_bus *bus,
  72                                  struct snd_pcm_substream *substream,
  73                                  size_t size)
  74 {
  75         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  76
  77         hdac_stream(stream)->bufsize = 0;
  78         hdac_stream(stream)->period_bytes = 0;
  79         hdac_stream(stream)->format_val = 0;
  80
  81         return 0;
  82 }
  83
  84 static void skl_set_pcm_constrains(struct hdac_bus *bus,
  85                                  struct snd_pcm_runtime *runtime)
  86 {
  87         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
  88
  89         /* avoid wrap-around with wall-clock */
  90         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
  91                                      20, 178000000);
  92 }
  93
  94 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
  95 {
  96         if (bus->ppcap)
  97                 return HDAC_EXT_STREAM_TYPE_HOST;
  98         else
  99                 return HDAC_EXT_STREAM_TYPE_COUPLED;
 100 }
 101
 102 /*
 103  * check if the stream opened is marked as ignore_suspend by machine, if so
 104  * then enable suspend_active refcount
 105  *
 106  * The count supend_active does not need lock as it is used in open/close
 107  * and suspend context
 108  */
 109 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
 110                                          struct snd_soc_dai *dai, bool enable)
 111 {
 112         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 113         struct snd_soc_dapm_widget *w;
 114         struct skl_dev *skl = bus_to_skl(bus);
 115
 116         w = snd_soc_dai_get_widget(dai, substream->stream);
 117
 118         if (w->ignore_suspend && enable)
 119                 skl->supend_active++;
 120         else if (w->ignore_suspend && !enable)
 121                 skl->supend_active--;
 122 }
 123
 124 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 125 {
 126         struct hdac_bus *bus = dev_get_drvdata(dev);
 127         unsigned int format_val;
 128         struct hdac_stream *hstream;
 129         struct hdac_ext_stream *stream;
 130         int err;
 131
 132         hstream = snd_hdac_get_stream(bus, params->stream,
 133                                         params->host_dma_id + 1);
 134         if (!hstream)
 135                 return -EINVAL;
 136
 137         stream = stream_to_hdac_ext_stream(hstream);
 138         snd_hdac_ext_stream_decouple(bus, stream, true);
 139
 140         format_val = snd_hdac_calc_stream_format(params->s_freq,
 141                         params->ch, params->format, params->host_bps, 0);
 142
 143         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 144                 format_val, params->s_freq, params->ch, params->format);
 145
 146         snd_hdac_stream_reset(hdac_stream(stream));
 147         err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
 148         if (err < 0)
 149                 return err;
 150
 151         err = snd_hdac_ext_host_stream_setup(stream, false);
 152         if (err < 0)
 153                 return err;
 154
 155         hdac_stream(stream)->prepared = 1;
 156
 157         return 0;
 158 }
 159
 160 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 161 {
 162         struct hdac_bus *bus = dev_get_drvdata(dev);
 163         unsigned int format_val;
 164         struct hdac_stream *hstream;
 165         struct hdac_ext_stream *stream;
 166         struct hdac_ext_link *link;
 167         unsigned char stream_tag;
 168
 169         hstream = snd_hdac_get_stream(bus, params->stream,
 170                                         params->link_dma_id + 1);
 171         if (!hstream)
 172                 return -EINVAL;
 173
 174         stream = stream_to_hdac_ext_stream(hstream);
 175         snd_hdac_ext_stream_decouple(bus, stream, true);
 176         format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
 177                                         params->format, params->link_bps, 0);
 178
 179         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 180                 format_val, params->s_freq, params->ch, params->format);
 181
 182         snd_hdac_ext_stream_reset(stream);
 183
 184         snd_hdac_ext_stream_setup(stream, format_val);
 185
 186         stream_tag = hstream->stream_tag;
 187         if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
 188                 list_for_each_entry(link, &bus->hlink_list, list) {
 189                         if (link->index == params->link_index)
 190                                 snd_hdac_ext_bus_link_set_stream_id(link,
 191                                                                     stream_tag);
 192                 }
 193         }
 194
 195         stream->link_prepared = 1;
 196
 197         return 0;
 198 }
 199
 200 static int skl_pcm_open(struct snd_pcm_substream *substream,
 201                 struct snd_soc_dai *dai)
 202 {
 203         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 204         struct hdac_ext_stream *stream;
 205         struct snd_pcm_runtime *runtime = substream->runtime;
 206         struct skl_dma_params *dma_params;
 207         struct skl_dev *skl = get_skl_ctx(dai->dev);
 208         struct skl_module_cfg *mconfig;
 209
 210         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 211
 212         stream = snd_hdac_ext_stream_assign(bus, substream,
 213                                         skl_get_host_stream_type(bus));
 214         if (stream == NULL)
 215                 return -EBUSY;
 216
 217         skl_set_pcm_constrains(bus, runtime);
 218
 219         /*
 220          * disable WALLCLOCK timestamps for capture streams
 221          * until we figure out how to handle digital inputs
 222          */
 223         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 224                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 225                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 226         }
 227
 228         runtime->private_data = stream;
 229
 230         dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
 231         if (!dma_params)
 232                 return -ENOMEM;
 233
 234         dma_params->stream_tag = hdac_stream(stream)->stream_tag;
 235         snd_soc_dai_set_dma_data(dai, substream, dma_params);
 236
 237         dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
 238                                  dma_params->stream_tag);
 239         skl_set_suspend_active(substream, dai, true);
 240         snd_pcm_set_sync(substream);
 241
 242         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 243         if (!mconfig) {
 244                 kfree(dma_params);
 245                 return -EINVAL;
 246         }
 247
 248         skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
 249
 250         return 0;
 251 }
 252
 253 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
 254                 struct snd_soc_dai *dai)
 255 {
 256         struct skl_dev *skl = get_skl_ctx(dai->dev);
 257         struct skl_module_cfg *mconfig;
 258         int ret;
 259
 260         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 261
 262         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 263
 264         /*
 265          * In case of XRUN recovery or in the case when the application
 266          * calls prepare another time, reset the FW pipe to clean state
 267          */
 268         if (mconfig &&
 269                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN ||
 270                  mconfig->pipe->state == SKL_PIPE_CREATED ||
 271                  mconfig->pipe->state == SKL_PIPE_PAUSED)) {
 272
 273                 ret = skl_reset_pipe(skl, mconfig->pipe);
 274
 275                 if (ret < 0)
 276                         return ret;
 277
 278                 ret = skl_pcm_host_dma_prepare(dai->dev,
 279                                         mconfig->pipe->p_params);
 280                 if (ret < 0)
 281                         return ret;
 282         }
 283
 284         return 0;
 285 }
 286
 287 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
 288                                 struct snd_pcm_hw_params *params,
 289                                 struct snd_soc_dai *dai)
 290 {
 291         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 292         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 293         struct snd_pcm_runtime *runtime = substream->runtime;
 294         struct skl_pipe_params p_params = {0};
 295         struct skl_module_cfg *m_cfg;
 296         int ret, dma_id;
 297
 298         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 299         ret = skl_substream_alloc_pages(bus, substream,
 300                                           params_buffer_bytes(params));
 301         if (ret < 0)
 302                 return ret;
 303
 304         dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
 305                         runtime->rate, runtime->channels, runtime->format);
 306
 307         dma_id = hdac_stream(stream)->stream_tag - 1;
 308         dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
 309
 310         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 311         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 312         p_params.ch = params_channels(params);
 313         p_params.s_freq = params_rate(params);
 314         p_params.host_dma_id = dma_id;
 315         p_params.stream = substream->stream;
 316         p_params.format = params_format(params);
 317         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 318                 p_params.host_bps = dai->driver->playback.sig_bits;
 319         else
 320                 p_params.host_bps = dai->driver->capture.sig_bits;
 321
 322
 323         m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
 324         if (m_cfg)
 325                 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
 326
 327         return 0;
 328 }
 329
 330 static void skl_pcm_close(struct snd_pcm_substream *substream,
 331                 struct snd_soc_dai *dai)
 332 {
 333         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 334         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 335         struct skl_dma_params *dma_params = NULL;
 336         struct skl_dev *skl = bus_to_skl(bus);
 337         struct skl_module_cfg *mconfig;
 338
 339         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 340
 341         snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
 342
 343         dma_params = snd_soc_dai_get_dma_data(dai, substream);
 344         /*
 345          * now we should set this to NULL as we are freeing by the
 346          * dma_params
 347          */
 348         snd_soc_dai_set_dma_data(dai, substream, NULL);
 349         skl_set_suspend_active(substream, dai, false);
 350
 351         /*
 352          * check if close is for "Reference Pin" and set back the
 353          * CGCTL.MISCBDCGE if disabled by driver
 354          */
 355         if (!strncmp(dai->name, "Reference Pin", 13) &&
 356                         skl->miscbdcg_disabled) {
 357                 skl->enable_miscbdcge(dai->dev, true);
 358                 skl->miscbdcg_disabled = false;
 359         }
 360
 361         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 362         if (mconfig)
 363                 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
 364
 365         kfree(dma_params);
 366 }
 367
 368 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
 369                 struct snd_soc_dai *dai)
 370 {
 371         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 372         struct skl_dev *skl = get_skl_ctx(dai->dev);
 373         struct skl_module_cfg *mconfig;
 374         int ret;
 375
 376         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 377
 378         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 379
 380         if (mconfig) {
 381                 ret = skl_reset_pipe(skl, mconfig->pipe);
 382                 if (ret < 0)
 383                         dev_err(dai->dev, "%s:Reset failed ret =%d",
 384                                                 __func__, ret);
 385         }
 386
 387         snd_hdac_stream_cleanup(hdac_stream(stream));
 388         hdac_stream(stream)->prepared = 0;
 389
 390         return 0;
 391 }
 392
 393 static int skl_be_hw_params(struct snd_pcm_substream *substream,
 394                                 struct snd_pcm_hw_params *params,
 395                                 struct snd_soc_dai *dai)
 396 {
 397         struct skl_pipe_params p_params = {0};
 398
 399         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 400         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 401         p_params.ch = params_channels(params);
 402         p_params.s_freq = params_rate(params);
 403         p_params.stream = substream->stream;
 404
 405         return skl_tplg_be_update_params(dai, &p_params);
 406 }
 407
 408 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
 409                 int cmd)
 410 {
 411         struct hdac_bus *bus = get_bus_ctx(substream);
 412         struct hdac_ext_stream *stream;
 413         int start;
 414         unsigned long cookie;
 415         struct hdac_stream *hstr;
 416
 417         stream = get_hdac_ext_stream(substream);
 418         hstr = hdac_stream(stream);
 419
 420         if (!hstr->prepared)
 421                 return -EPIPE;
 422
 423         switch (cmd) {
 424         case SNDRV_PCM_TRIGGER_START:
 425         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 426         case SNDRV_PCM_TRIGGER_RESUME:
 427                 start = 1;
 428                 break;
 429
 430         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 431         case SNDRV_PCM_TRIGGER_SUSPEND:
 432         case SNDRV_PCM_TRIGGER_STOP:
 433                 start = 0;
 434                 break;
 435
 436         default:
 437                 return -EINVAL;
 438         }
 439
 440         spin_lock_irqsave(&bus->reg_lock, cookie);
 441
 442         if (start) {
 443                 snd_hdac_stream_start(hdac_stream(stream));
 444                 snd_hdac_stream_timecounter_init(hstr, 0);
 445         } else {
 446                 snd_hdac_stream_stop(hdac_stream(stream));
 447         }
 448
 449         spin_unlock_irqrestore(&bus->reg_lock, cookie);
 450
 451         return 0;
 452 }
 453
 454 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 455                 struct snd_soc_dai *dai)
 456 {
 457         struct skl_dev *skl = get_skl_ctx(dai->dev);
 458         struct skl_module_cfg *mconfig;
 459         struct hdac_bus *bus = get_bus_ctx(substream);
 460         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 461         struct hdac_stream *hstream = hdac_stream(stream);
 462         struct snd_soc_dapm_widget *w;
 463         int ret;
 464
 465         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 466         if (!mconfig)
 467                 return -EIO;
 468
 469         w = snd_soc_dai_get_widget(dai, substream->stream);
 470
 471         switch (cmd) {
 472         case SNDRV_PCM_TRIGGER_RESUME:
 473                 if (!w->ignore_suspend) {
 474                         /*
 475                          * enable DMA Resume enable bit for the stream, set the
 476                          * dpib & lpib position to resume before starting the
 477                          * DMA
 478                          */
 479                         snd_hdac_stream_drsm_enable(bus, true, hstream->index);
 480                         snd_hdac_stream_set_dpibr(bus, hstream, hstream->lpib);
 481                         snd_hdac_stream_set_lpib(hstream, hstream->lpib);
 482                 }
 483                 fallthrough;
 484
 485         case SNDRV_PCM_TRIGGER_START:
 486         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 487                 /*
 488                  * Start HOST DMA and Start FE Pipe.This is to make sure that
 489                  * there are no underrun/overrun in the case when the FE
 490                  * pipeline is started but there is a delay in starting the
 491                  * DMA channel on the host.
 492                  */
 493                 ret = skl_decoupled_trigger(substream, cmd);
 494                 if (ret < 0)
 495                         return ret;
 496                 return skl_run_pipe(skl, mconfig->pipe);
 497
 498         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 499         case SNDRV_PCM_TRIGGER_SUSPEND:
 500         case SNDRV_PCM_TRIGGER_STOP:
 501                 /*
 502                  * Stop FE Pipe first and stop DMA. This is to make sure that
 503                  * there are no underrun/overrun in the case if there is a delay
 504                  * between the two operations.
 505                  */
 506                 ret = skl_stop_pipe(skl, mconfig->pipe);
 507                 if (ret < 0)
 508                         return ret;
 509
 510                 ret = skl_decoupled_trigger(substream, cmd);
 511                 if (ret < 0)
 512                         return ret;
 513
 514                 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
 515                         /* save the dpib and lpib positions */
 516                         hstream->dpib = readl(bus->remap_addr +
 517                                         AZX_REG_VS_SDXDPIB_XBASE +
 518                                         (AZX_REG_VS_SDXDPIB_XINTERVAL *
 519                                         hstream->index));
 520
 521                         hstream->lpib = snd_hdac_stream_get_pos_lpib(hstream);
 522
 523                         snd_hdac_ext_stream_decouple(bus, stream, false);
 524                 }
 525                 break;
 526
 527         default:
 528                 return -EINVAL;
 529         }
 530
 531         return 0;
 532 }
 533
 534
 535 static int skl_link_hw_params(struct snd_pcm_substream *substream,
 536                                 struct snd_pcm_hw_params *params,
 537                                 struct snd_soc_dai *dai)
 538 {
 539         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 540         struct hdac_ext_stream *link_dev;
 541         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 542         struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
 543         struct skl_pipe_params p_params = {0};
 544         struct hdac_ext_link *link;
 545         int stream_tag;
 546
 547         link_dev = snd_hdac_ext_stream_assign(bus, substream,
 548                                         HDAC_EXT_STREAM_TYPE_LINK);
 549         if (!link_dev)
 550                 return -EBUSY;
 551
 552         snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
 553
 554         link = snd_hdac_ext_bus_get_hlink_by_name(bus, codec_dai->component->name);
 555         if (!link)
 556                 return -EINVAL;
 557
 558         stream_tag = hdac_stream(link_dev)->stream_tag;
 559
 560         /* set the hdac_stream in the codec dai */
 561         snd_soc_dai_set_stream(codec_dai, hdac_stream(link_dev), substream->stream);
 562
 563         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 564         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 565         p_params.ch = params_channels(params);
 566         p_params.s_freq = params_rate(params);
 567         p_params.stream = substream->stream;
 568         p_params.link_dma_id = stream_tag - 1;
 569         p_params.link_index = link->index;
 570         p_params.format = params_format(params);
 571
 572         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 573                 p_params.link_bps = codec_dai->driver->playback.sig_bits;
 574         else
 575                 p_params.link_bps = codec_dai->driver->capture.sig_bits;
 576
 577         return skl_tplg_be_update_params(dai, &p_params);
 578 }
 579
 580 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
 581                 struct snd_soc_dai *dai)
 582 {
 583         struct skl_dev *skl = get_skl_ctx(dai->dev);
 584         struct skl_module_cfg *mconfig = NULL;
 585
 586         /* In case of XRUN recovery, reset the FW pipe to clean state */
 587         mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
 588         if (mconfig && !mconfig->pipe->passthru &&
 589                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN))
 590                 skl_reset_pipe(skl, mconfig->pipe);
 591
 592         return 0;
 593 }
 594
 595 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
 596         int cmd, struct snd_soc_dai *dai)
 597 {
 598         struct hdac_ext_stream *link_dev =
 599                                 snd_soc_dai_get_dma_data(dai, substream);
 600         struct hdac_bus *bus = get_bus_ctx(substream);
 601         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 602
 603         dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
 604         switch (cmd) {
 605         case SNDRV_PCM_TRIGGER_RESUME:
 606         case SNDRV_PCM_TRIGGER_START:
 607         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 608                 snd_hdac_ext_stream_start(link_dev);
 609                 break;
 610
 611         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 612         case SNDRV_PCM_TRIGGER_SUSPEND:
 613         case SNDRV_PCM_TRIGGER_STOP:
 614                 snd_hdac_ext_stream_clear(link_dev);
 615                 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
 616                         snd_hdac_ext_stream_decouple(bus, stream, false);
 617                 break;
 618
 619         default:
 620                 return -EINVAL;
 621         }
 622         return 0;
 623 }
 624
 625 static int skl_link_hw_free(struct snd_pcm_substream *substream,
 626                 struct snd_soc_dai *dai)
 627 {
 628         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 629         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 630         struct hdac_ext_stream *link_dev =
 631                                 snd_soc_dai_get_dma_data(dai, substream);
 632         struct hdac_ext_link *link;
 633         unsigned char stream_tag;
 634
 635         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 636
 637         link_dev->link_prepared = 0;
 638
 639         link = snd_hdac_ext_bus_get_hlink_by_name(bus, snd_soc_rtd_to_codec(rtd, 0)->component->name);
 640         if (!link)
 641                 return -EINVAL;
 642
 643         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 644                 stream_tag = hdac_stream(link_dev)->stream_tag;
 645                 snd_hdac_ext_bus_link_clear_stream_id(link, stream_tag);
 646         }
 647
 648         snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
 649         return 0;
 650 }
 651
 652 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
 653         .startup = skl_pcm_open,
 654         .shutdown = skl_pcm_close,
 655         .prepare = skl_pcm_prepare,
 656         .hw_params = skl_pcm_hw_params,
 657         .hw_free = skl_pcm_hw_free,
 658         .trigger = skl_pcm_trigger,
 659 };
 660
 661 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
 662         .hw_params = skl_be_hw_params,
 663 };
 664
 665 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
 666         .hw_params = skl_be_hw_params,
 667 };
 668
 669 static const struct snd_soc_dai_ops skl_link_dai_ops = {
 670         .prepare = skl_link_pcm_prepare,
 671         .hw_params = skl_link_hw_params,
 672         .hw_free = skl_link_hw_free,
 673         .trigger = skl_link_pcm_trigger,
 674 };
 675
 676 static struct snd_soc_dai_driver skl_fe_dai[] = {
 677 {
 678         .name = "System Pin",
 679         .ops = &skl_pcm_dai_ops,
 680         .playback = {
 681                 .stream_name = "System Playback",
 682                 .channels_min = HDA_MONO,
 683                 .channels_max = HDA_STEREO,
 684                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
 685                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 686                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 687                 .sig_bits = 32,
 688         },
 689         .capture = {
 690                 .stream_name = "System Capture",
 691                 .channels_min = HDA_MONO,
 692                 .channels_max = HDA_STEREO,
 693                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 694                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 695                 .sig_bits = 32,
 696         },
 697 },
 698 {
 699         .name = "System Pin2",
 700         .ops = &skl_pcm_dai_ops,
 701         .playback = {
 702                 .stream_name = "Headset Playback",
 703                 .channels_min = HDA_MONO,
 704                 .channels_max = HDA_STEREO,
 705                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 706                         SNDRV_PCM_RATE_8000,
 707                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 708                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 709         },
 710 },
 711 {
 712         .name = "Echoref Pin",
 713         .ops = &skl_pcm_dai_ops,
 714         .capture = {
 715                 .stream_name = "Echoreference Capture",
 716                 .channels_min = HDA_STEREO,
 717                 .channels_max = HDA_STEREO,
 718                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 719                         SNDRV_PCM_RATE_8000,
 720                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 721                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 722         },
 723 },
 724 {
 725         .name = "Reference Pin",
 726         .ops = &skl_pcm_dai_ops,
 727         .capture = {
 728                 .stream_name = "Reference Capture",
 729                 .channels_min = HDA_MONO,
 730                 .channels_max = HDA_QUAD,
 731                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 732                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 733                 .sig_bits = 32,
 734         },
 735 },
 736 {
 737         .name = "Deepbuffer Pin",
 738         .ops = &skl_pcm_dai_ops,
 739         .playback = {
 740                 .stream_name = "Deepbuffer Playback",
 741                 .channels_min = HDA_STEREO,
 742                 .channels_max = HDA_STEREO,
 743                 .rates = SNDRV_PCM_RATE_48000,
 744                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 745                 .sig_bits = 32,
 746         },
 747 },
 748 {
 749         .name = "LowLatency Pin",
 750         .ops = &skl_pcm_dai_ops,
 751         .playback = {
 752                 .stream_name = "Low Latency Playback",
 753                 .channels_min = HDA_STEREO,
 754                 .channels_max = HDA_STEREO,
 755                 .rates = SNDRV_PCM_RATE_48000,
 756                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 757                 .sig_bits = 32,
 758         },
 759 },
 760 {
 761         .name = "DMIC Pin",
 762         .ops = &skl_pcm_dai_ops,
 763         .capture = {
 764                 .stream_name = "DMIC Capture",
 765                 .channels_min = HDA_MONO,
 766                 .channels_max = HDA_QUAD,
 767                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 768                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 769                 .sig_bits = 32,
 770         },
 771 },
 772 {
 773         .name = "HDMI1 Pin",
 774         .ops = &skl_pcm_dai_ops,
 775         .playback = {
 776                 .stream_name = "HDMI1 Playback",
 777                 .channels_min = HDA_STEREO,
 778                 .channels_max = 8,
 779                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 780                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 781                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 782                         SNDRV_PCM_RATE_192000,
 783                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 784                         SNDRV_PCM_FMTBIT_S32_LE,
 785                 .sig_bits = 32,
 786         },
 787 },
 788 {
 789         .name = "HDMI2 Pin",
 790         .ops = &skl_pcm_dai_ops,
 791         .playback = {
 792                 .stream_name = "HDMI2 Playback",
 793                 .channels_min = HDA_STEREO,
 794                 .channels_max = 8,
 795                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 796                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 797                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 798                         SNDRV_PCM_RATE_192000,
 799                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 800                         SNDRV_PCM_FMTBIT_S32_LE,
 801                 .sig_bits = 32,
 802         },
 803 },
 804 {
 805         .name = "HDMI3 Pin",
 806         .ops = &skl_pcm_dai_ops,
 807         .playback = {
 808                 .stream_name = "HDMI3 Playback",
 809                 .channels_min = HDA_STEREO,
 810                 .channels_max = 8,
 811                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 812                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 813                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 814                         SNDRV_PCM_RATE_192000,
 815                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 816                         SNDRV_PCM_FMTBIT_S32_LE,
 817                 .sig_bits = 32,
 818         },
 819 },
 820 };
 821
 822 /* BE CPU  Dais */
 823 static struct snd_soc_dai_driver skl_platform_dai[] = {
 824 {
 825         .name = "SSP0 Pin",
 826         .ops = &skl_be_ssp_dai_ops,
 827         .playback = {
 828                 .stream_name = "ssp0 Tx",
 829                 .channels_min = HDA_STEREO,
 830                 .channels_max = HDA_STEREO,
 831                 .rates = SNDRV_PCM_RATE_48000,
 832                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 833         },
 834         .capture = {
 835                 .stream_name = "ssp0 Rx",
 836                 .channels_min = HDA_STEREO,
 837                 .channels_max = HDA_STEREO,
 838                 .rates = SNDRV_PCM_RATE_48000,
 839                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 840         },
 841 },
 842 {
 843         .name = "SSP1 Pin",
 844         .ops = &skl_be_ssp_dai_ops,
 845         .playback = {
 846                 .stream_name = "ssp1 Tx",
 847                 .channels_min = HDA_STEREO,
 848                 .channels_max = HDA_STEREO,
 849                 .rates = SNDRV_PCM_RATE_48000,
 850                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 851         },
 852         .capture = {
 853                 .stream_name = "ssp1 Rx",
 854                 .channels_min = HDA_STEREO,
 855                 .channels_max = HDA_STEREO,
 856                 .rates = SNDRV_PCM_RATE_48000,
 857                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 858         },
 859 },
 860 {
 861         .name = "SSP2 Pin",
 862         .ops = &skl_be_ssp_dai_ops,
 863         .playback = {
 864                 .stream_name = "ssp2 Tx",
 865                 .channels_min = HDA_STEREO,
 866                 .channels_max = HDA_STEREO,
 867                 .rates = SNDRV_PCM_RATE_48000,
 868                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 869         },
 870         .capture = {
 871                 .stream_name = "ssp2 Rx",
 872                 .channels_min = HDA_STEREO,
 873                 .channels_max = HDA_STEREO,
 874                 .rates = SNDRV_PCM_RATE_48000,
 875                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 876         },
 877 },
 878 {
 879         .name = "SSP3 Pin",
 880         .ops = &skl_be_ssp_dai_ops,
 881         .playback = {
 882                 .stream_name = "ssp3 Tx",
 883                 .channels_min = HDA_STEREO,
 884                 .channels_max = HDA_STEREO,
 885                 .rates = SNDRV_PCM_RATE_48000,
 886                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 887         },
 888         .capture = {
 889                 .stream_name = "ssp3 Rx",
 890                 .channels_min = HDA_STEREO,
 891                 .channels_max = HDA_STEREO,
 892                 .rates = SNDRV_PCM_RATE_48000,
 893                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 894         },
 895 },
 896 {
 897         .name = "SSP4 Pin",
 898         .ops = &skl_be_ssp_dai_ops,
 899         .playback = {
 900                 .stream_name = "ssp4 Tx",
 901                 .channels_min = HDA_STEREO,
 902                 .channels_max = HDA_STEREO,
 903                 .rates = SNDRV_PCM_RATE_48000,
 904                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 905         },
 906         .capture = {
 907                 .stream_name = "ssp4 Rx",
 908                 .channels_min = HDA_STEREO,
 909                 .channels_max = HDA_STEREO,
 910                 .rates = SNDRV_PCM_RATE_48000,
 911                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 912         },
 913 },
 914 {
 915         .name = "SSP5 Pin",
 916         .ops = &skl_be_ssp_dai_ops,
 917         .playback = {
 918                 .stream_name = "ssp5 Tx",
 919                 .channels_min = HDA_STEREO,
 920                 .channels_max = HDA_STEREO,
 921                 .rates = SNDRV_PCM_RATE_48000,
 922                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 923         },
 924         .capture = {
 925                 .stream_name = "ssp5 Rx",
 926                 .channels_min = HDA_STEREO,
 927                 .channels_max = HDA_STEREO,
 928                 .rates = SNDRV_PCM_RATE_48000,
 929                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 930         },
 931 },
 932 {
 933         .name = "iDisp1 Pin",
 934         .ops = &skl_link_dai_ops,
 935         .playback = {
 936                 .stream_name = "iDisp1 Tx",
 937                 .channels_min = HDA_STEREO,
 938                 .channels_max = 8,
 939                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
 940                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 941                         SNDRV_PCM_FMTBIT_S24_LE,
 942         },
 943 },
 944 {
 945         .name = "iDisp2 Pin",
 946         .ops = &skl_link_dai_ops,
 947         .playback = {
 948                 .stream_name = "iDisp2 Tx",
 949                 .channels_min = HDA_STEREO,
 950                 .channels_max = 8,
 951                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 952                         SNDRV_PCM_RATE_48000,
 953                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 954                         SNDRV_PCM_FMTBIT_S24_LE,
 955         },
 956 },
 957 {
 958         .name = "iDisp3 Pin",
 959         .ops = &skl_link_dai_ops,
 960         .playback = {
 961                 .stream_name = "iDisp3 Tx",
 962                 .channels_min = HDA_STEREO,
 963                 .channels_max = 8,
 964                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 965                         SNDRV_PCM_RATE_48000,
 966                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 967                         SNDRV_PCM_FMTBIT_S24_LE,
 968         },
 969 },
 970 {
 971         .name = "DMIC01 Pin",
 972         .ops = &skl_dmic_dai_ops,
 973         .capture = {
 974                 .stream_name = "DMIC01 Rx",
 975                 .channels_min = HDA_MONO,
 976                 .channels_max = HDA_QUAD,
 977                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 978                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 979         },
 980 },
 981 {
 982         .name = "DMIC16k Pin",
 983         .ops = &skl_dmic_dai_ops,
 984         .capture = {
 985                 .stream_name = "DMIC16k Rx",
 986                 .channels_min = HDA_MONO,
 987                 .channels_max = HDA_QUAD,
 988                 .rates = SNDRV_PCM_RATE_16000,
 989                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 990         },
 991 },
 992 {
 993         .name = "Analog CPU DAI",
 994         .ops = &skl_link_dai_ops,
 995         .playback = {
 996                 .stream_name = "Analog CPU Playback",
 997                 .channels_min = HDA_MONO,
 998                 .channels_max = HDA_MAX,
 999                 .rates = SNDRV_PCM_RATE_8000_192000,
1000                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1001                         SNDRV_PCM_FMTBIT_S32_LE,
1002         },
1003         .capture = {
1004                 .stream_name = "Analog CPU Capture",
1005                 .channels_min = HDA_MONO,
1006                 .channels_max = HDA_MAX,
1007                 .rates = SNDRV_PCM_RATE_8000_192000,
1008                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1009                         SNDRV_PCM_FMTBIT_S32_LE,
1010         },
1011 },
1012 {
1013         .name = "Alt Analog CPU DAI",
1014         .ops = &skl_link_dai_ops,
1015         .playback = {
1016                 .stream_name = "Alt Analog CPU Playback",
1017                 .channels_min = HDA_MONO,
1018                 .channels_max = HDA_MAX,
1019                 .rates = SNDRV_PCM_RATE_8000_192000,
1020                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1021                         SNDRV_PCM_FMTBIT_S32_LE,
1022         },
1023         .capture = {
1024                 .stream_name = "Alt Analog CPU Capture",
1025                 .channels_min = HDA_MONO,
1026                 .channels_max = HDA_MAX,
1027                 .rates = SNDRV_PCM_RATE_8000_192000,
1028                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1029                         SNDRV_PCM_FMTBIT_S32_LE,
1030         },
1031 },
1032 {
1033         .name = "Digital CPU DAI",
1034         .ops = &skl_link_dai_ops,
1035         .playback = {
1036                 .stream_name = "Digital CPU Playback",
1037                 .channels_min = HDA_MONO,
1038                 .channels_max = HDA_MAX,
1039                 .rates = SNDRV_PCM_RATE_8000_192000,
1040                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1041                         SNDRV_PCM_FMTBIT_S32_LE,
1042         },
1043         .capture = {
1044                 .stream_name = "Digital CPU Capture",
1045                 .channels_min = HDA_MONO,
1046                 .channels_max = HDA_MAX,
1047                 .rates = SNDRV_PCM_RATE_8000_192000,
1048                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1049                         SNDRV_PCM_FMTBIT_S32_LE,
1050         },
1051 },
1052 };
1053
1054 int skl_dai_load(struct snd_soc_component *cmp, int index,
1055                         struct snd_soc_dai_driver *dai_drv,
1056                         struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1057 {
1058         dai_drv->ops = &skl_pcm_dai_ops;
1059
1060         return 0;
1061 }
1062
1063 static int skl_platform_soc_open(struct snd_soc_component *component,
1064                                  struct snd_pcm_substream *substream)
1065 {
1066         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1067         struct snd_soc_dai_link *dai_link = rtd->dai_link;
1068
1069         dev_dbg(snd_soc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__,
1070                                         dai_link->cpus->dai_name);
1071
1072         snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1073
1074         return 0;
1075 }
1076
1077 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1078                                         int cmd)
1079 {
1080         struct hdac_bus *bus = get_bus_ctx(substream);
1081         struct hdac_ext_stream *stream;
1082         struct snd_pcm_substream *s;
1083         bool start;
1084         int sbits = 0;
1085         unsigned long cookie;
1086         struct hdac_stream *hstr;
1087
1088         stream = get_hdac_ext_stream(substream);
1089         hstr = hdac_stream(stream);
1090
1091         dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1092
1093         if (!hstr->prepared)
1094                 return -EPIPE;
1095
1096         switch (cmd) {
1097         case SNDRV_PCM_TRIGGER_START:
1098         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1099         case SNDRV_PCM_TRIGGER_RESUME:
1100                 start = true;
1101                 break;
1102
1103         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1104         case SNDRV_PCM_TRIGGER_SUSPEND:
1105         case SNDRV_PCM_TRIGGER_STOP:
1106                 start = false;
1107                 break;
1108
1109         default:
1110                 return -EINVAL;
1111         }
1112
1113         snd_pcm_group_for_each_entry(s, substream) {
1114                 if (s->pcm->card != substream->pcm->card)
1115                         continue;
1116                 stream = get_hdac_ext_stream(s);
1117                 sbits |= 1 << hdac_stream(stream)->index;
1118                 snd_pcm_trigger_done(s, substream);
1119         }
1120
1121         spin_lock_irqsave(&bus->reg_lock, cookie);
1122
1123         /* first, set SYNC bits of corresponding streams */
1124         snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1125
1126         snd_pcm_group_for_each_entry(s, substream) {
1127                 if (s->pcm->card != substream->pcm->card)
1128                         continue;
1129                 stream = get_hdac_ext_stream(s);
1130                 if (start)
1131                         snd_hdac_stream_start(hdac_stream(stream));
1132                 else
1133                         snd_hdac_stream_stop(hdac_stream(stream));
1134         }
1135         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1136
1137         snd_hdac_stream_sync(hstr, start, sbits);
1138
1139         spin_lock_irqsave(&bus->reg_lock, cookie);
1140
1141         /* reset SYNC bits */
1142         snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1143         if (start)
1144                 snd_hdac_stream_timecounter_init(hstr, sbits);
1145         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1146
1147         return 0;
1148 }
1149
1150 static int skl_platform_soc_trigger(struct snd_soc_component *component,
1151                                     struct snd_pcm_substream *substream,
1152                                     int cmd)
1153 {
1154         struct hdac_bus *bus = get_bus_ctx(substream);
1155
1156         if (!bus->ppcap)
1157                 return skl_coupled_trigger(substream, cmd);
1158
1159         return 0;
1160 }
1161
1162 static snd_pcm_uframes_t skl_platform_soc_pointer(
1163         struct snd_soc_component *component,
1164         struct snd_pcm_substream *substream)
1165 {
1166         struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1167         struct hdac_bus *bus = get_bus_ctx(substream);
1168         unsigned int pos;
1169
1170         /*
1171          * Use DPIB for Playback stream as the periodic DMA Position-in-
1172          * Buffer Writes may be scheduled at the same time or later than
1173          * the MSI and does not guarantee to reflect the Position of the
1174          * last buffer that was transferred. Whereas DPIB register in
1175          * HAD space reflects the actual data that is transferred.
1176          * Use the position buffer for capture, as DPIB write gets
1177          * completed earlier than the actual data written to the DDR.
1178          *
1179          * For capture stream following workaround is required to fix the
1180          * incorrect position reporting.
1181          *
1182          * 1. Wait for 20us before reading the DMA position in buffer once
1183          * the interrupt is generated for stream completion as update happens
1184          * on the HDA frame boundary i.e. 20.833uSec.
1185          * 2. Read DPIB register to flush the DMA position value. This dummy
1186          * read is required to flush DMA position value.
1187          * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1188          * or greater than period boundary.
1189          */
1190
1191         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1192                 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1193                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1194                                 hdac_stream(hstream)->index));
1195         } else {
1196                 udelay(20);
1197                 readl(bus->remap_addr +
1198                                 AZX_REG_VS_SDXDPIB_XBASE +
1199                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1200                                  hdac_stream(hstream)->index));
1201                 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1202         }
1203
1204         if (pos >= hdac_stream(hstream)->bufsize)
1205                 pos = 0;
1206
1207         return bytes_to_frames(substream->runtime, pos);
1208 }
1209
1210 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1211                                 u64 nsec)
1212 {
1213         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1214         struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
1215         u64 codec_frames, codec_nsecs;
1216
1217         if (!codec_dai->driver->ops->delay)
1218                 return nsec;
1219
1220         codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1221         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1222                               substream->runtime->rate);
1223
1224         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1225                 return nsec + codec_nsecs;
1226
1227         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1228 }
1229
1230 static int skl_platform_soc_get_time_info(
1231                         struct snd_soc_component *component,
1232                         struct snd_pcm_substream *substream,
1233                         struct timespec64 *system_ts, struct timespec64 *audio_ts,
1234                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1235                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1236 {
1237         struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1238         struct hdac_stream *hstr = hdac_stream(sstream);
1239         u64 nsec;
1240
1241         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1242                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1243
1244                 snd_pcm_gettime(substream->runtime, system_ts);
1245
1246                 nsec = timecounter_read(&hstr->tc);
1247                 if (audio_tstamp_config->report_delay)
1248                         nsec = skl_adjust_codec_delay(substream, nsec);
1249
1250                 *audio_ts = ns_to_timespec64(nsec);
1251
1252                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1253                 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1254                 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1255
1256         } else {
1257                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1258         }
1259
1260         return 0;
1261 }
1262
1263 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
1264
1265 static int skl_platform_soc_new(struct snd_soc_component *component,
1266                                 struct snd_soc_pcm_runtime *rtd)
1267 {
1268         struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0);
1269         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1270         struct snd_pcm *pcm = rtd->pcm;
1271         unsigned int size;
1272         struct skl_dev *skl = bus_to_skl(bus);
1273
1274         if (dai->driver->playback.channels_min ||
1275                 dai->driver->capture.channels_min) {
1276                 /* buffer pre-allocation */
1277                 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1278                 if (size > MAX_PREALLOC_SIZE)
1279                         size = MAX_PREALLOC_SIZE;
1280                 snd_pcm_set_managed_buffer_all(pcm,
1281                                                SNDRV_DMA_TYPE_DEV_SG,
1282                                                &skl->pci->dev,
1283                                                size, MAX_PREALLOC_SIZE);
1284         }
1285
1286         return 0;
1287 }
1288
1289 static int skl_get_module_info(struct skl_dev *skl,
1290                 struct skl_module_cfg *mconfig)
1291 {
1292         struct skl_module_inst_id *pin_id;
1293         guid_t *uuid_mod, *uuid_tplg;
1294         struct skl_module *skl_module;
1295         struct uuid_module *module;
1296         int i, ret = -EIO;
1297
1298         uuid_mod = (guid_t *)mconfig->guid;
1299
1300         if (list_empty(&skl->uuid_list)) {
1301                 dev_err(skl->dev, "Module list is empty\n");
1302                 return -EIO;
1303         }
1304
1305         for (i = 0; i < skl->nr_modules; i++) {
1306                 skl_module = skl->modules[i];
1307                 uuid_tplg = &skl_module->uuid;
1308                 if (guid_equal(uuid_mod, uuid_tplg)) {
1309                         mconfig->module = skl_module;
1310                         ret = 0;
1311                         break;
1312                 }
1313         }
1314
1315         if (skl->nr_modules && ret)
1316                 return ret;
1317
1318         ret = -EIO;
1319         list_for_each_entry(module, &skl->uuid_list, list) {
1320                 if (guid_equal(uuid_mod, &module->uuid)) {
1321                         mconfig->id.module_id = module->id;
1322                         mconfig->module->loadable = module->is_loadable;
1323                         ret = 0;
1324                 }
1325
1326                 for (i = 0; i < MAX_IN_QUEUE; i++) {
1327                         pin_id = &mconfig->m_in_pin[i].id;
1328                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1329                                 pin_id->module_id = module->id;
1330                 }
1331
1332                 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1333                         pin_id = &mconfig->m_out_pin[i].id;
1334                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1335                                 pin_id->module_id = module->id;
1336                 }
1337         }
1338
1339         return ret;
1340 }
1341
1342 static int skl_populate_modules(struct skl_dev *skl)
1343 {
1344         struct skl_pipeline *p;
1345         struct skl_pipe_module *m;
1346         struct snd_soc_dapm_widget *w;
1347         struct skl_module_cfg *mconfig;
1348         int ret = 0;
1349
1350         list_for_each_entry(p, &skl->ppl_list, node) {
1351                 list_for_each_entry(m, &p->pipe->w_list, node) {
1352                         w = m->w;
1353                         mconfig = w->priv;
1354
1355                         ret = skl_get_module_info(skl, mconfig);
1356                         if (ret < 0) {
1357                                 dev_err(skl->dev,
1358                                         "query module info failed\n");
1359                                 return ret;
1360                         }
1361
1362                         skl_tplg_add_moduleid_in_bind_params(skl, w);
1363                 }
1364         }
1365
1366         return ret;
1367 }
1368
1369 static int skl_platform_soc_probe(struct snd_soc_component *component)
1370 {
1371         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1372         struct skl_dev *skl = bus_to_skl(bus);
1373         const struct skl_dsp_ops *ops;
1374         int ret;
1375
1376         ret = pm_runtime_resume_and_get(component->dev);
1377         if (ret < 0 && ret != -EACCES)
1378                 return ret;
1379
1380         if (bus->ppcap) {
1381                 skl->component = component;
1382
1383                 /* init debugfs */
1384                 skl->debugfs = skl_debugfs_init(skl);
1385
1386                 ret = skl_tplg_init(component, bus);
1387                 if (ret < 0) {
1388                         dev_err(component->dev, "Failed to init topology!\n");
1389                         return ret;
1390                 }
1391
1392                 /* load the firmwares, since all is set */
1393                 ops = skl_get_dsp_ops(skl->pci->device);
1394                 if (!ops)
1395                         return -EIO;
1396
1397                 /*
1398                  * Disable dynamic clock and power gating during firmware
1399                  * and library download
1400                  */
1401                 skl->enable_miscbdcge(component->dev, false);
1402                 skl->clock_power_gating(component->dev, false);
1403
1404                 ret = ops->init_fw(component->dev, skl);
1405                 skl->enable_miscbdcge(component->dev, true);
1406                 skl->clock_power_gating(component->dev, true);
1407                 if (ret < 0) {
1408                         dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1409                         return ret;
1410                 }
1411                 skl_populate_modules(skl);
1412                 skl->update_d0i3c = skl_update_d0i3c;
1413
1414                 if (skl->cfg.astate_cfg != NULL) {
1415                         skl_dsp_set_astate_cfg(skl,
1416                                         skl->cfg.astate_cfg->count,
1417                                         skl->cfg.astate_cfg);
1418                 }
1419         }
1420         pm_runtime_mark_last_busy(component->dev);
1421         pm_runtime_put_autosuspend(component->dev);
1422
1423         return 0;
1424 }
1425
1426 static void skl_platform_soc_remove(struct snd_soc_component *component)
1427 {
1428         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1429         struct skl_dev *skl = bus_to_skl(bus);
1430
1431         skl_tplg_exit(component, bus);
1432
1433         skl_debugfs_exit(skl);
1434 }
1435
1436 static const struct snd_soc_component_driver skl_component  = {
1437         .name           = "pcm",
1438         .probe          = skl_platform_soc_probe,
1439         .remove         = skl_platform_soc_remove,
1440         .open           = skl_platform_soc_open,
1441         .trigger        = skl_platform_soc_trigger,
1442         .pointer        = skl_platform_soc_pointer,
1443         .get_time_info  = skl_platform_soc_get_time_info,
1444         .pcm_construct  = skl_platform_soc_new,
1445         .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
1446 };
1447
1448 int skl_platform_register(struct device *dev)
1449 {
1450         int ret;
1451         struct snd_soc_dai_driver *dais;
1452         int num_dais = ARRAY_SIZE(skl_platform_dai);
1453         struct hdac_bus *bus = dev_get_drvdata(dev);
1454         struct skl_dev *skl = bus_to_skl(bus);
1455
1456         skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1457                             GFP_KERNEL);
1458         if (!skl->dais) {
1459                 ret = -ENOMEM;
1460                 goto err;
1461         }
1462
1463         if (!skl->use_tplg_pcm) {
1464                 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1465                                 sizeof(skl_platform_dai), GFP_KERNEL);
1466                 if (!dais) {
1467                         kfree(skl->dais);
1468                         ret = -ENOMEM;
1469                         goto err;
1470                 }
1471
1472                 skl->dais = dais;
1473                 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1474                        sizeof(skl_fe_dai));
1475                 num_dais += ARRAY_SIZE(skl_fe_dai);
1476         }
1477
1478         ret = devm_snd_soc_register_component(dev, &skl_component,
1479                                          skl->dais, num_dais);
1480         if (ret) {
1481                 kfree(skl->dais);
1482                 dev_err(dev, "soc component registration failed %d\n", ret);
1483         }
1484 err:
1485         return ret;
1486 }
1487
1488 int skl_platform_unregister(struct device *dev)
1489 {
1490         struct hdac_bus *bus = dev_get_drvdata(dev);
1491         struct skl_dev *skl = bus_to_skl(bus);
1492         struct skl_module_deferred_bind *modules, *tmp;
1493
1494         list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1495                 list_del(&modules->node);
1496                 kfree(modules);
1497         }
1498
1499         kfree(skl->dais);
1500
1501         return 0;
1502 }