2 * cnl-sst.c - DSP library functions for CNL platform
4 * Copyright (C) 2016-17, Intel Corporation.
6 * Author: Guneshwor Singh <guneshwor.o.singh@intel.com>
9 * HDA DSP library functions for SKL platform
10 * Copyright (C) 2014-15, Intel Corporation.
12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as version 2, as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but
19 * WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * General Public License for more details.
23 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/firmware.h>
29 #include <linux/device.h>
31 #include "../common/sst-dsp.h"
32 #include "../common/sst-dsp-priv.h"
33 #include "../common/sst-ipc.h"
34 #include "cnl-sst-dsp.h"
35 #include "skl-sst-dsp.h"
36 #include "skl-sst-ipc.h"
38 #define CNL_FW_ROM_INIT 0x1
39 #define CNL_FW_INIT 0x5
40 #define CNL_IPC_PURGE 0x01004000
41 #define CNL_INIT_TIMEOUT 300
42 #define CNL_BASEFW_TIMEOUT 3000
44 #define CNL_ADSP_SRAM0_BASE 0x80000
46 /* Firmware status window */
47 #define CNL_ADSP_FW_STATUS CNL_ADSP_SRAM0_BASE
48 #define CNL_ADSP_ERROR_CODE (CNL_ADSP_FW_STATUS + 0x4)
50 #define CNL_INSTANCE_ID 0
51 #define CNL_BASE_FW_MODULE_ID 0
52 #define CNL_ADSP_FW_HDR_OFFSET 0x2000
53 #define CNL_ROM_CTRL_DMA_ID 0x9
55 static int cnl_prepare_fw(struct sst_dsp *ctx, const void *fwdata, u32 fwsize)
60 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
61 if (stream_tag <= 0) {
62 dev_err(ctx->dev, "dma prepare failed: 0%#x\n", stream_tag);
66 ctx->dsp_ops.stream_tag = stream_tag;
67 memcpy(ctx->dmab.area, fwdata, fwsize);
69 /* purge FW request */
70 sst_dsp_shim_write(ctx, CNL_ADSP_REG_HIPCIDR,
71 CNL_ADSP_REG_HIPCIDR_BUSY | (CNL_IPC_PURGE |
72 ((stream_tag - 1) << CNL_ROM_CTRL_DMA_ID)));
74 ret = cnl_dsp_enable_core(ctx, SKL_DSP_CORE0_MASK);
76 dev_err(ctx->dev, "dsp boot core failed ret: %d\n", ret);
78 goto base_fw_load_failed;
81 /* enable interrupt */
82 cnl_ipc_int_enable(ctx);
83 cnl_ipc_op_int_enable(ctx);
85 ret = sst_dsp_register_poll(ctx, CNL_ADSP_FW_STATUS, CNL_FW_STS_MASK,
86 CNL_FW_ROM_INIT, CNL_INIT_TIMEOUT,
89 dev_err(ctx->dev, "rom init timeout, ret: %d\n", ret);
90 goto base_fw_load_failed;
96 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
97 cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
102 static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
106 ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
107 ret = sst_dsp_register_poll(ctx, CNL_ADSP_FW_STATUS, CNL_FW_STS_MASK,
108 CNL_FW_INIT, CNL_BASEFW_TIMEOUT,
111 ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
112 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
117 static int cnl_load_base_firmware(struct sst_dsp *ctx)
119 struct firmware stripped_fw;
120 struct skl_sst *cnl = ctx->thread_context;
124 ret = reject_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
126 dev_err(ctx->dev, "request firmware failed: %d\n", ret);
127 goto cnl_load_base_firmware_failed;
131 /* parse uuids if first boot */
132 if (cnl->is_first_boot) {
133 ret = snd_skl_parse_uuids(ctx, ctx->fw,
134 CNL_ADSP_FW_HDR_OFFSET, 0);
136 goto cnl_load_base_firmware_failed;
139 stripped_fw.data = ctx->fw->data;
140 stripped_fw.size = ctx->fw->size;
141 skl_dsp_strip_extended_manifest(&stripped_fw);
143 ret = cnl_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
145 dev_err(ctx->dev, "prepare firmware failed: %d\n", ret);
146 goto cnl_load_base_firmware_failed;
149 ret = sst_transfer_fw_host_dma(ctx);
151 dev_err(ctx->dev, "transfer firmware failed: %d\n", ret);
152 cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
153 goto cnl_load_base_firmware_failed;
156 ret = wait_event_timeout(cnl->boot_wait, cnl->boot_complete,
157 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
159 dev_err(ctx->dev, "FW ready timed-out\n");
160 cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
162 goto cnl_load_base_firmware_failed;
165 cnl->fw_loaded = true;
169 cnl_load_base_firmware_failed:
170 release_firmware(ctx->fw);
176 static int cnl_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
178 struct skl_sst *cnl = ctx->thread_context;
179 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
180 struct skl_ipc_dxstate_info dx;
183 if (!cnl->fw_loaded) {
184 cnl->boot_complete = false;
185 ret = cnl_load_base_firmware(ctx);
187 dev_err(ctx->dev, "fw reload failed: %d\n", ret);
191 cnl->cores.state[core_id] = SKL_DSP_RUNNING;
195 ret = cnl_dsp_enable_core(ctx, core_mask);
197 dev_err(ctx->dev, "enable dsp core %d failed: %d\n",
202 if (core_id == SKL_DSP_CORE0_ID) {
203 /* enable interrupt */
204 cnl_ipc_int_enable(ctx);
205 cnl_ipc_op_int_enable(ctx);
206 cnl->boot_complete = false;
208 ret = wait_event_timeout(cnl->boot_wait, cnl->boot_complete,
209 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
212 "dsp boot timeout, status=%#x error=%#x\n",
213 sst_dsp_shim_read(ctx, CNL_ADSP_FW_STATUS),
214 sst_dsp_shim_read(ctx, CNL_ADSP_ERROR_CODE));
219 dx.core_mask = core_mask;
220 dx.dx_mask = core_mask;
222 ret = skl_ipc_set_dx(&cnl->ipc, CNL_INSTANCE_ID,
223 CNL_BASE_FW_MODULE_ID, &dx);
225 dev_err(ctx->dev, "set_dx failed, core: %d ret: %d\n",
230 cnl->cores.state[core_id] = SKL_DSP_RUNNING;
234 cnl_dsp_disable_core(ctx, core_mask);
239 static int cnl_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
241 struct skl_sst *cnl = ctx->thread_context;
242 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
243 struct skl_ipc_dxstate_info dx;
246 dx.core_mask = core_mask;
247 dx.dx_mask = SKL_IPC_D3_MASK;
249 ret = skl_ipc_set_dx(&cnl->ipc, CNL_INSTANCE_ID,
250 CNL_BASE_FW_MODULE_ID, &dx);
253 "dsp core %d to d3 failed; continue reset\n",
255 cnl->fw_loaded = false;
258 /* disable interrupts if core 0 */
259 if (core_id == SKL_DSP_CORE0_ID) {
260 skl_ipc_op_int_disable(ctx);
261 skl_ipc_int_disable(ctx);
264 ret = cnl_dsp_disable_core(ctx, core_mask);
266 dev_err(ctx->dev, "disable dsp core %d failed: %d\n",
271 cnl->cores.state[core_id] = SKL_DSP_RESET;
276 static unsigned int cnl_get_errno(struct sst_dsp *ctx)
278 return sst_dsp_shim_read(ctx, CNL_ADSP_ERROR_CODE);
281 static const struct skl_dsp_fw_ops cnl_fw_ops = {
282 .set_state_D0 = cnl_set_dsp_D0,
283 .set_state_D3 = cnl_set_dsp_D3,
284 .load_fw = cnl_load_base_firmware,
285 .get_fw_errcode = cnl_get_errno,
288 static struct sst_ops cnl_ops = {
289 .irq_handler = cnl_dsp_sst_interrupt,
290 .write = sst_shim32_write,
291 .read = sst_shim32_read,
292 .ram_read = sst_memcpy_fromio_32,
293 .ram_write = sst_memcpy_toio_32,
294 .free = cnl_dsp_free,
297 #define CNL_IPC_GLB_NOTIFY_RSP_SHIFT 29
298 #define CNL_IPC_GLB_NOTIFY_RSP_MASK 0x1
299 #define CNL_IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> CNL_IPC_GLB_NOTIFY_RSP_SHIFT) \
300 & CNL_IPC_GLB_NOTIFY_RSP_MASK)
302 static irqreturn_t cnl_dsp_irq_thread_handler(int irq, void *context)
304 struct sst_dsp *dsp = context;
305 struct skl_sst *cnl = sst_dsp_get_thread_context(dsp);
306 struct sst_generic_ipc *ipc = &cnl->ipc;
307 struct skl_ipc_header header = {0};
308 u32 hipcida, hipctdr, hipctdd;
311 /* here we handle ipc interrupts only */
312 if (!(dsp->intr_status & CNL_ADSPIS_IPC))
315 hipcida = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCIDA);
316 hipctdr = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDR);
318 /* reply message from dsp */
319 if (hipcida & CNL_ADSP_REG_HIPCIDA_DONE) {
320 sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL,
321 CNL_ADSP_REG_HIPCCTL_DONE, 0);
323 /* clear done bit - tell dsp operation is complete */
324 sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCIDA,
325 CNL_ADSP_REG_HIPCIDA_DONE, CNL_ADSP_REG_HIPCIDA_DONE);
329 /* unmask done interrupt */
330 sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL,
331 CNL_ADSP_REG_HIPCCTL_DONE, CNL_ADSP_REG_HIPCCTL_DONE);
334 /* new message from dsp */
335 if (hipctdr & CNL_ADSP_REG_HIPCTDR_BUSY) {
336 hipctdd = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDD);
337 header.primary = hipctdr;
338 header.extension = hipctdd;
339 dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x",
341 dev_dbg(dsp->dev, "IPC irq: Firmware respond extension:%x",
344 if (CNL_IPC_GLB_NOTIFY_RSP_TYPE(header.primary)) {
345 /* Handle Immediate reply from DSP Core */
346 skl_ipc_process_reply(ipc, header);
348 dev_dbg(dsp->dev, "IPC irq: Notification from firmware\n");
349 skl_ipc_process_notification(ipc, header);
351 /* clear busy interrupt */
352 sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCTDR,
353 CNL_ADSP_REG_HIPCTDR_BUSY, CNL_ADSP_REG_HIPCTDR_BUSY);
355 /* set done bit to ack dsp */
356 sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCTDA,
357 CNL_ADSP_REG_HIPCTDA_DONE, CNL_ADSP_REG_HIPCTDA_DONE);
364 cnl_ipc_int_enable(dsp);
366 /* continue to send any remaining messages */
367 schedule_work(&ipc->kwork);
372 static struct sst_dsp_device cnl_dev = {
373 .thread = cnl_dsp_irq_thread_handler,
377 static void cnl_ipc_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
379 struct skl_ipc_header *header = (struct skl_ipc_header *)(&msg->header);
382 sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
383 sst_dsp_shim_write_unlocked(ipc->dsp, CNL_ADSP_REG_HIPCIDD,
385 sst_dsp_shim_write_unlocked(ipc->dsp, CNL_ADSP_REG_HIPCIDR,
386 header->primary | CNL_ADSP_REG_HIPCIDR_BUSY);
389 static bool cnl_ipc_is_dsp_busy(struct sst_dsp *dsp)
393 hipcidr = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCIDR);
395 return (hipcidr & CNL_ADSP_REG_HIPCIDR_BUSY);
398 static int cnl_ipc_init(struct device *dev, struct skl_sst *cnl)
400 struct sst_generic_ipc *ipc;
407 ipc->tx_data_max_size = CNL_ADSP_W1_SZ;
408 ipc->rx_data_max_size = CNL_ADSP_W0_UP_SZ;
410 err = sst_ipc_init(ipc);
415 * overriding tx_msg and is_dsp_busy since
416 * ipc registers are different for cnl
418 ipc->ops.tx_msg = cnl_ipc_tx_msg;
419 ipc->ops.tx_data_copy = skl_ipc_tx_data_copy;
420 ipc->ops.is_dsp_busy = cnl_ipc_is_dsp_busy;
425 int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
426 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
427 struct skl_sst **dsp)
433 ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &cnl_dev);
435 dev_err(dev, "%s: no device\n", __func__);
441 sst->fw_ops = cnl_fw_ops;
442 sst->addr.lpe = mmio_base;
443 sst->addr.shim = mmio_base;
444 sst->addr.sram0_base = CNL_ADSP_SRAM0_BASE;
445 sst->addr.sram1_base = CNL_ADSP_SRAM1_BASE;
446 sst->addr.w0_stat_sz = CNL_ADSP_W0_STAT_SZ;
447 sst->addr.w0_up_sz = CNL_ADSP_W0_UP_SZ;
449 sst_dsp_mailbox_init(sst, (CNL_ADSP_SRAM0_BASE + CNL_ADSP_W0_STAT_SZ),
450 CNL_ADSP_W0_UP_SZ, CNL_ADSP_SRAM1_BASE,
453 ret = cnl_ipc_init(dev, cnl);
459 cnl->boot_complete = false;
460 init_waitqueue_head(&cnl->boot_wait);
462 return skl_dsp_acquire_irq(sst);
464 EXPORT_SYMBOL_GPL(cnl_sst_dsp_init);
466 int cnl_sst_init_fw(struct device *dev, struct skl_sst *ctx)
469 struct sst_dsp *sst = ctx->dsp;
471 ret = ctx->dsp->fw_ops.load_fw(sst);
473 dev_err(dev, "load base fw failed: %d", ret);
477 skl_dsp_init_core_state(sst);
479 ctx->is_first_boot = false;
483 EXPORT_SYMBOL_GPL(cnl_sst_init_fw);
485 void cnl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
488 release_firmware(ctx->dsp->fw);
490 skl_freeup_uuid_list(ctx);
491 cnl_ipc_free(&ctx->ipc);
493 ctx->dsp->ops->free(ctx->dsp);
495 EXPORT_SYMBOL_GPL(cnl_sst_dsp_cleanup);
497 MODULE_LICENSE("GPL v2");
498 MODULE_DESCRIPTION("Intel Cannonlake IPC driver");