1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
5 * Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 * Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
9 #ifndef __SOUND_SOC_INTEL_AVS_REGS_H
10 #define __SOUND_SOC_INTEL_AVS_REGS_H
12 #include <linux/sizes.h>
14 #define AZX_PCIREG_PGCTL 0x44
15 #define AZX_PCIREG_CGCTL 0x48
16 #define AZX_PGCTL_LSRMD_MASK BIT(4)
17 #define AZX_CGCTL_MISCBDCGE_MASK BIT(6)
18 #define AZX_VS_EM2_L1SEN BIT(13)
19 #define AZX_VS_EM2_DUM BIT(23)
21 /* Intel HD Audio General DSP Registers */
22 #define AVS_ADSP_GEN_BASE 0x0
23 #define AVS_ADSP_REG_ADSPCS (AVS_ADSP_GEN_BASE + 0x04)
24 #define AVS_ADSP_REG_ADSPIC (AVS_ADSP_GEN_BASE + 0x08)
25 #define AVS_ADSP_REG_ADSPIS (AVS_ADSP_GEN_BASE + 0x0C)
27 #define AVS_ADSP_ADSPIC_IPC BIT(0)
28 #define AVS_ADSP_ADSPIC_CLDMA BIT(1)
29 #define AVS_ADSP_ADSPIS_IPC BIT(0)
30 #define AVS_ADSP_ADSPIS_CLDMA BIT(1)
32 #define AVS_ADSPCS_CRST_MASK(cm) (cm)
33 #define AVS_ADSPCS_CSTALL_MASK(cm) ((cm) << 8)
34 #define AVS_ADSPCS_SPA_MASK(cm) ((cm) << 16)
35 #define AVS_ADSPCS_CPA_MASK(cm) ((cm) << 24)
36 #define AVS_MAIN_CORE_MASK BIT(0)
38 #define AVS_ADSP_HIPCCTL_BUSY BIT(0)
39 #define AVS_ADSP_HIPCCTL_DONE BIT(1)
41 /* SKL Intel HD Audio Inter-Processor Communication Registers */
42 #define SKL_ADSP_IPC_BASE 0x40
43 #define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00)
44 #define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04)
45 #define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08)
46 #define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C)
47 #define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10)
49 #define SKL_ADSP_HIPCI_BUSY BIT(31)
50 #define SKL_ADSP_HIPCIE_DONE BIT(30)
51 #define SKL_ADSP_HIPCT_BUSY BIT(31)
53 /* Intel HD Audio SRAM windows base addresses */
54 #define SKL_ADSP_SRAM_BASE_OFFSET 0x8000
55 #define SKL_ADSP_SRAM_WINDOW_SIZE 0x2000
56 #define APL_ADSP_SRAM_BASE_OFFSET 0x80000
57 #define APL_ADSP_SRAM_WINDOW_SIZE 0x20000
59 /* Constants used when accessing SRAM, space shared with firmware */
60 #define AVS_FW_REG_BASE(adev) ((adev)->spec->sram_base_offset)
61 #define AVS_FW_REG_STATUS(adev) (AVS_FW_REG_BASE(adev) + 0x0)
62 #define AVS_FW_REG_ERROR_CODE(adev) (AVS_FW_REG_BASE(adev) + 0x4)
64 #define AVS_WINDOW_CHUNK_SIZE SZ_4K
65 #define AVS_FW_REGS_SIZE AVS_WINDOW_CHUNK_SIZE
66 #define AVS_FW_REGS_WINDOW 0
67 /* DSP -> HOST communication window */
68 #define AVS_UPLINK_WINDOW AVS_FW_REGS_WINDOW
69 /* HOST -> DSP communication window */
70 #define AVS_DOWNLINK_WINDOW 1
71 #define AVS_DEBUG_WINDOW 2
73 /* registry I/O helpers */
74 #define avs_sram_offset(adev, window_idx) \
75 ((adev)->spec->sram_base_offset + \
76 (adev)->spec->sram_window_size * (window_idx))
78 #define avs_sram_addr(adev, window_idx) \
79 ((adev)->dsp_ba + avs_sram_offset(adev, window_idx))
81 #define avs_uplink_addr(adev) \
82 (avs_sram_addr(adev, AVS_UPLINK_WINDOW) + AVS_FW_REGS_SIZE)
83 #define avs_downlink_addr(adev) \
84 avs_sram_addr(adev, AVS_DOWNLINK_WINDOW)
86 #endif /* __SOUND_SOC_INTEL_AVS_REGS_H */