1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
9 #include <sound/hdaudio_ext.h>
11 #include "registers.h"
14 #define AVS_ADSPCS_INTERVAL_US 500
15 #define AVS_ADSPCS_TIMEOUT_US 50000
17 int avs_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power)
22 value = snd_hdac_adsp_readl(adev, AVS_ADSP_REG_ADSPCS);
23 trace_avs_dsp_core_op(value, core_mask, "power", power);
25 mask = AVS_ADSPCS_SPA_MASK(core_mask);
26 value = power ? mask : 0;
28 snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
30 mask = AVS_ADSPCS_CPA_MASK(core_mask);
31 value = power ? mask : 0;
33 ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
34 reg, (reg & mask) == value,
35 AVS_ADSPCS_INTERVAL_US,
36 AVS_ADSPCS_TIMEOUT_US);
38 dev_err(adev->dev, "core_mask %d power %s failed: %d\n",
39 core_mask, power ? "on" : "off", ret);
44 int avs_dsp_core_reset(struct avs_dev *adev, u32 core_mask, bool reset)
49 value = snd_hdac_adsp_readl(adev, AVS_ADSP_REG_ADSPCS);
50 trace_avs_dsp_core_op(value, core_mask, "reset", reset);
52 mask = AVS_ADSPCS_CRST_MASK(core_mask);
53 value = reset ? mask : 0;
55 snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
57 ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
58 reg, (reg & mask) == value,
59 AVS_ADSPCS_INTERVAL_US,
60 AVS_ADSPCS_TIMEOUT_US);
62 dev_err(adev->dev, "core_mask %d %s reset failed: %d\n",
63 core_mask, reset ? "enter" : "exit", ret);
68 int avs_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stall)
73 value = snd_hdac_adsp_readl(adev, AVS_ADSP_REG_ADSPCS);
74 trace_avs_dsp_core_op(value, core_mask, "stall", stall);
76 mask = AVS_ADSPCS_CSTALL_MASK(core_mask);
77 value = stall ? mask : 0;
79 snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
81 ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
82 reg, (reg & mask) == value,
83 AVS_ADSPCS_INTERVAL_US,
84 AVS_ADSPCS_TIMEOUT_US);
86 dev_err(adev->dev, "core_mask %d %sstall failed: %d\n",
87 core_mask, stall ? "" : "un", ret);
92 int avs_dsp_core_enable(struct avs_dev *adev, u32 core_mask)
96 ret = avs_dsp_op(adev, power, core_mask, true);
100 ret = avs_dsp_op(adev, reset, core_mask, false);
104 return avs_dsp_op(adev, stall, core_mask, false);
107 int avs_dsp_core_disable(struct avs_dev *adev, u32 core_mask)
109 /* No error checks to allow for complete DSP shutdown. */
110 avs_dsp_op(adev, stall, core_mask, true);
111 avs_dsp_op(adev, reset, core_mask, true);
113 return avs_dsp_op(adev, power, core_mask, false);
116 static int avs_dsp_enable(struct avs_dev *adev, u32 core_mask)
121 ret = avs_dsp_core_enable(adev, core_mask);
125 mask = core_mask & ~AVS_MAIN_CORE_MASK;
128 * without main core, fw is dead anyway
129 * so setting D0 for it is futile.
133 ret = avs_ipc_set_dx(adev, mask, true);
134 return AVS_IPC_RET(ret);
137 static int avs_dsp_disable(struct avs_dev *adev, u32 core_mask)
141 ret = avs_ipc_set_dx(adev, core_mask, false);
143 return AVS_IPC_RET(ret);
145 return avs_dsp_core_disable(adev, core_mask);
148 static int avs_dsp_get_core(struct avs_dev *adev, u32 core_id)
153 mask = BIT_MASK(core_id);
154 if (mask == AVS_MAIN_CORE_MASK)
155 /* nothing to do for main core */
157 if (core_id >= adev->hw_cfg.dsp_cores) {
162 adev->core_refs[core_id]++;
163 if (adev->core_refs[core_id] == 1) {
165 * No cores other than main-core can be running for DSP
166 * to achieve d0ix. Conscious SET_D0IX IPC failure is permitted,
167 * simply d0ix power state will no longer be attempted.
169 ret = avs_dsp_disable_d0ix(adev);
170 if (ret && ret != -AVS_EIPC)
171 goto err_disable_d0ix;
173 ret = avs_dsp_enable(adev, mask);
181 avs_dsp_enable_d0ix(adev);
183 adev->core_refs[core_id]--;
185 dev_err(adev->dev, "get core %d failed: %d\n", core_id, ret);
189 static int avs_dsp_put_core(struct avs_dev *adev, u32 core_id)
194 mask = BIT_MASK(core_id);
195 if (mask == AVS_MAIN_CORE_MASK)
196 /* nothing to do for main core */
198 if (core_id >= adev->hw_cfg.dsp_cores) {
203 adev->core_refs[core_id]--;
204 if (!adev->core_refs[core_id]) {
205 ret = avs_dsp_disable(adev, mask);
209 /* Match disable_d0ix in avs_dsp_get_core(). */
210 avs_dsp_enable_d0ix(adev);
215 dev_err(adev->dev, "put core %d failed: %d\n", core_id, ret);
219 int avs_dsp_init_module(struct avs_dev *adev, u16 module_id, u8 ppl_instance_id,
220 u8 core_id, u8 domain, void *param, u32 param_size,
223 struct avs_module_entry mentry;
224 bool was_loaded = false;
227 id = avs_module_id_alloc(adev, module_id);
231 ret = avs_get_module_id_entry(adev, module_id, &mentry);
235 ret = avs_dsp_get_core(adev, core_id);
239 /* Load code into memory if this is the first instance. */
240 if (!id && !avs_module_entry_is_loaded(&mentry)) {
241 ret = avs_dsp_op(adev, transfer_mods, true, &mentry, 1);
243 dev_err(adev->dev, "load modules failed: %d\n", ret);
249 ret = avs_ipc_init_instance(adev, module_id, id, ppl_instance_id,
250 core_id, domain, param, param_size);
252 ret = AVS_IPC_RET(ret);
261 avs_dsp_op(adev, transfer_mods, false, &mentry, 1);
262 avs_dsp_put_core(adev, core_id);
264 avs_module_id_free(adev, module_id, id);
268 void avs_dsp_delete_module(struct avs_dev *adev, u16 module_id, u16 instance_id,
269 u8 ppl_instance_id, u8 core_id)
271 struct avs_module_entry mentry;
274 /* Modules not owned by any pipeline need to be freed explicitly. */
275 if (ppl_instance_id == INVALID_PIPELINE_ID)
276 avs_ipc_delete_instance(adev, module_id, instance_id);
278 avs_module_id_free(adev, module_id, instance_id);
280 ret = avs_get_module_id_entry(adev, module_id, &mentry);
281 /* Unload occupied memory if this was the last instance. */
282 if (!ret && mentry.type.load_type == AVS_MODULE_LOAD_TYPE_LOADABLE) {
283 if (avs_is_module_ida_empty(adev, module_id)) {
284 ret = avs_dsp_op(adev, transfer_mods, false, &mentry, 1);
286 dev_err(adev->dev, "unload modules failed: %d\n", ret);
290 avs_dsp_put_core(adev, core_id);
293 int avs_dsp_create_pipeline(struct avs_dev *adev, u16 req_size, u8 priority,
294 bool lp, u16 attributes, u8 *instance_id)
296 struct avs_fw_cfg *fw_cfg = &adev->fw_cfg;
299 id = ida_alloc_max(&adev->ppl_ida, fw_cfg->max_ppl_count - 1, GFP_KERNEL);
303 ret = avs_ipc_create_pipeline(adev, req_size, priority, id, lp, attributes);
305 ida_free(&adev->ppl_ida, id);
306 return AVS_IPC_RET(ret);
313 int avs_dsp_delete_pipeline(struct avs_dev *adev, u8 instance_id)
317 ret = avs_ipc_delete_pipeline(adev, instance_id);
319 ret = AVS_IPC_RET(ret);
321 ida_free(&adev->ppl_ida, instance_id);