1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
9 #include <linux/devcoredump.h>
10 #include <linux/slab.h>
16 static int apl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
17 u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
19 struct apl_log_state_info *info;
20 u32 size, num_cores = adev->hw_cfg.dsp_cores;
23 if (fls_long(resource_mask) > num_cores)
25 size = struct_size(info, logs_core, num_cores);
26 info = kzalloc(size, GFP_KERNEL);
30 info->aging_timer_period = aging_period;
31 info->fifo_full_timer_period = fifo_full_period;
32 info->core_mask = resource_mask;
34 for_each_set_bit(i, &resource_mask, num_cores) {
35 info->logs_core[i].enable = enable;
36 info->logs_core[i].min_priority = *priorities++;
39 for_each_set_bit(i, &resource_mask, num_cores)
40 info->logs_core[i].enable = enable;
42 ret = avs_ipc_set_enable_logs(adev, (u8 *)info, size);
45 return AVS_IPC_RET(ret);
50 static int apl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
52 struct apl_log_buffer_layout layout;
54 void __iomem *addr, *buf;
56 addr = avs_log_buffer_addr(adev, msg->log.core);
60 memcpy_fromio(&layout, addr, sizeof(layout));
62 spin_lock_irqsave(&adev->dbg.trace_lock, flags);
63 if (!kfifo_initialized(&adev->dbg.trace_fifo))
64 /* consume the logs regardless of consumer presence */
67 buf = apl_log_payload_addr(addr);
69 if (layout.read_ptr > layout.write_ptr) {
70 __kfifo_fromio_locked(&adev->dbg.trace_fifo, buf + layout.read_ptr,
71 apl_log_payload_size(adev) - layout.read_ptr,
72 &adev->dbg.fifo_lock);
75 __kfifo_fromio_locked(&adev->dbg.trace_fifo, buf + layout.read_ptr,
76 layout.write_ptr - layout.read_ptr, &adev->dbg.fifo_lock);
78 wake_up(&adev->dbg.trace_waitq);
81 spin_unlock_irqrestore(&adev->dbg.trace_lock, flags);
82 writel(layout.write_ptr, addr);
86 static int apl_wait_log_entry(struct avs_dev *adev, u32 core, struct apl_log_buffer_layout *layout)
88 unsigned long timeout;
91 addr = avs_log_buffer_addr(adev, core);
95 timeout = jiffies + msecs_to_jiffies(10);
98 memcpy_fromio(layout, addr, sizeof(*layout));
99 if (layout->read_ptr != layout->write_ptr)
101 usleep_range(500, 1000);
102 } while (!time_after(jiffies, timeout));
107 /* reads log header and tests its type */
108 #define apl_is_entry_stackdump(addr) ((readl(addr) >> 30) & 0x1)
110 static int apl_coredump(struct avs_dev *adev, union avs_notify_msg *msg)
112 struct apl_log_buffer_layout layout;
113 void __iomem *addr, *buf;
118 dump_size = AVS_FW_REGS_SIZE + msg->ext.coredump.stack_dump_size;
119 dump = vzalloc(dump_size);
123 memcpy_fromio(dump, avs_sram_addr(adev, AVS_FW_REGS_WINDOW), AVS_FW_REGS_SIZE);
125 if (!msg->ext.coredump.stack_dump_size)
128 /* Dump the registers even if an external error prevents gathering the stack. */
129 addr = avs_log_buffer_addr(adev, msg->ext.coredump.core_id);
133 buf = apl_log_payload_addr(addr);
134 memcpy_fromio(&layout, addr, sizeof(layout));
135 if (!apl_is_entry_stackdump(buf + layout.read_ptr)) {
137 * DSP awaits the remaining logs to be
138 * gathered before dumping stack
140 msg->log.core = msg->ext.coredump.core_id;
141 avs_dsp_op(adev, log_buffer_status, msg);
144 pos = dump + AVS_FW_REGS_SIZE;
145 /* gather the stack */
149 if (apl_wait_log_entry(adev, msg->ext.coredump.core_id, &layout))
152 if (layout.read_ptr > layout.write_ptr) {
153 count = apl_log_payload_size(adev) - layout.read_ptr;
154 memcpy_fromio(pos + offset, buf + layout.read_ptr, count);
158 count = layout.write_ptr - layout.read_ptr;
159 memcpy_fromio(pos + offset, buf + layout.read_ptr, count);
162 /* update read pointer */
163 writel(layout.write_ptr, addr);
164 } while (offset < msg->ext.coredump.stack_dump_size);
167 dev_coredumpv(adev->dev, dump, dump_size, GFP_KERNEL);
172 static bool apl_lp_streaming(struct avs_dev *adev)
174 struct avs_path *path;
176 /* Any gateway without buffer allocated in LP area disqualifies D0IX. */
177 list_for_each_entry(path, &adev->path_list, node) {
178 struct avs_path_pipeline *ppl;
180 list_for_each_entry(ppl, &path->ppl_list, node) {
181 struct avs_path_module *mod;
183 list_for_each_entry(mod, &ppl->mod_list, node) {
184 struct avs_tplg_modcfg_ext *cfg;
186 cfg = mod->template->cfg_ext;
188 /* only copiers have gateway attributes */
189 if (!guid_equal(&cfg->type, &AVS_COPIER_MOD_UUID))
191 /* non-gateway copiers do not prevent PG */
192 if (cfg->copier.dma_type == INVALID_OBJECT_ID)
195 if (!mod->gtw_attrs.lp_buffer_alloc)
204 static bool apl_d0ix_toggle(struct avs_dev *adev, struct avs_ipc_msg *tx, bool wake)
206 /* wake in all cases */
211 * If no pipelines are running, allow for d0ix schedule.
212 * If all gateways have lp=1, allow for d0ix schedule.
213 * If any gateway with lp=0 is allocated, abort scheduling d0ix.
215 * Note: for cAVS 1.5+ and 1.8, D0IX is LP-firmware transition,
216 * not the power-gating mechanism known from cAVS 2.0.
218 return apl_lp_streaming(adev);
221 static int apl_set_d0ix(struct avs_dev *adev, bool enable)
223 bool streaming = false;
227 /* Either idle or all gateways with lp=1. */
228 streaming = !list_empty(&adev->path_list);
230 ret = avs_ipc_set_d0ix(adev, enable, streaming);
231 return AVS_IPC_RET(ret);
234 const struct avs_dsp_ops apl_dsp_ops = {
235 .power = avs_dsp_core_power,
236 .reset = avs_dsp_core_reset,
237 .stall = avs_dsp_core_stall,
238 .irq_handler = avs_dsp_irq_handler,
239 .irq_thread = avs_dsp_irq_thread,
240 .int_control = avs_dsp_interrupt_control,
241 .load_basefw = avs_hda_load_basefw,
242 .load_lib = avs_hda_load_library,
243 .transfer_mods = avs_hda_transfer_modules,
244 .enable_logs = apl_enable_logs,
245 .log_buffer_offset = skl_log_buffer_offset,
246 .log_buffer_status = apl_log_buffer_status,
247 .coredump = apl_coredump,
248 .d0ix_toggle = apl_d0ix_toggle,
249 .set_d0ix = apl_set_d0ix,