2 * IMG parallel output controller driver
4 * Copyright (C) 2015 Imagination Technologies Ltd.
6 * Author: Damien Horsley <Damien.Horsley@imgtec.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
13 #include <linux/clk.h>
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/reset.h>
22 #include <sound/core.h>
23 #include <sound/dmaengine_pcm.h>
24 #include <sound/initval.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
29 #define IMG_PRL_OUT_TX_FIFO 0
31 #define IMG_PRL_OUT_CTL 0x4
32 #define IMG_PRL_OUT_CTL_CH_MASK BIT(4)
33 #define IMG_PRL_OUT_CTL_PACKH_MASK BIT(3)
34 #define IMG_PRL_OUT_CTL_EDGE_MASK BIT(2)
35 #define IMG_PRL_OUT_CTL_ME_MASK BIT(1)
36 #define IMG_PRL_OUT_CTL_SRST_MASK BIT(0)
42 struct snd_dmaengine_dai_dma_data dma_data;
44 struct reset_control *rst;
47 static int img_prl_out_suspend(struct device *dev)
49 struct img_prl_out *prl = dev_get_drvdata(dev);
51 clk_disable_unprepare(prl->clk_ref);
56 static int img_prl_out_resume(struct device *dev)
58 struct img_prl_out *prl = dev_get_drvdata(dev);
61 ret = clk_prepare_enable(prl->clk_ref);
63 dev_err(dev, "clk_enable failed: %d\n", ret);
70 static inline void img_prl_out_writel(struct img_prl_out *prl,
73 writel(val, prl->base + reg);
76 static inline u32 img_prl_out_readl(struct img_prl_out *prl, u32 reg)
78 return readl(prl->base + reg);
81 static void img_prl_out_reset(struct img_prl_out *prl)
85 ctl = img_prl_out_readl(prl, IMG_PRL_OUT_CTL) &
86 ~IMG_PRL_OUT_CTL_ME_MASK;
88 reset_control_assert(prl->rst);
89 reset_control_deassert(prl->rst);
91 img_prl_out_writel(prl, ctl, IMG_PRL_OUT_CTL);
94 static int img_prl_out_trigger(struct snd_pcm_substream *substream, int cmd,
95 struct snd_soc_dai *dai)
97 struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
101 case SNDRV_PCM_TRIGGER_START:
102 case SNDRV_PCM_TRIGGER_RESUME:
103 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
104 reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
105 reg |= IMG_PRL_OUT_CTL_ME_MASK;
106 img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
108 case SNDRV_PCM_TRIGGER_STOP:
109 case SNDRV_PCM_TRIGGER_SUSPEND:
110 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
111 img_prl_out_reset(prl);
120 static int img_prl_out_hw_params(struct snd_pcm_substream *substream,
121 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
123 struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
124 unsigned int rate, channels;
125 u32 reg, control_set = 0;
127 rate = params_rate(params);
128 channels = params_channels(params);
130 switch (params_format(params)) {
131 case SNDRV_PCM_FORMAT_S32_LE:
132 control_set |= IMG_PRL_OUT_CTL_PACKH_MASK;
134 case SNDRV_PCM_FORMAT_S24_LE:
143 clk_set_rate(prl->clk_ref, rate * 256);
145 reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
146 reg = (reg & ~IMG_PRL_OUT_CTL_PACKH_MASK) | control_set;
147 img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
152 static int img_prl_out_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
154 struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
155 u32 reg, control_set = 0;
158 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
159 case SND_SOC_DAIFMT_NB_NF:
161 case SND_SOC_DAIFMT_NB_IF:
162 control_set |= IMG_PRL_OUT_CTL_EDGE_MASK;
168 ret = pm_runtime_get_sync(prl->dev);
170 pm_runtime_put_noidle(prl->dev);
174 reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
175 reg = (reg & ~IMG_PRL_OUT_CTL_EDGE_MASK) | control_set;
176 img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
177 pm_runtime_put(prl->dev);
182 static const struct snd_soc_dai_ops img_prl_out_dai_ops = {
183 .trigger = img_prl_out_trigger,
184 .hw_params = img_prl_out_hw_params,
185 .set_fmt = img_prl_out_set_fmt
188 static int img_prl_out_dai_probe(struct snd_soc_dai *dai)
190 struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
192 snd_soc_dai_init_dma_data(dai, &prl->dma_data, NULL);
197 static struct snd_soc_dai_driver img_prl_out_dai = {
198 .probe = img_prl_out_dai_probe,
202 .rates = SNDRV_PCM_RATE_8000_192000,
203 .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S24_LE
205 .ops = &img_prl_out_dai_ops
208 static const struct snd_soc_component_driver img_prl_out_component = {
209 .name = "img-prl-out"
212 static int img_prl_out_probe(struct platform_device *pdev)
214 struct img_prl_out *prl;
215 struct resource *res;
218 struct device *dev = &pdev->dev;
220 prl = devm_kzalloc(&pdev->dev, sizeof(*prl), GFP_KERNEL);
224 platform_set_drvdata(pdev, prl);
226 prl->dev = &pdev->dev;
228 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
229 base = devm_ioremap_resource(&pdev->dev, res);
231 return PTR_ERR(base);
235 prl->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
236 if (IS_ERR(prl->rst)) {
237 if (PTR_ERR(prl->rst) != -EPROBE_DEFER)
238 dev_err(&pdev->dev, "No top level reset found\n");
239 return PTR_ERR(prl->rst);
242 prl->clk_sys = devm_clk_get(&pdev->dev, "sys");
243 if (IS_ERR(prl->clk_sys)) {
244 if (PTR_ERR(prl->clk_sys) != -EPROBE_DEFER)
245 dev_err(dev, "Failed to acquire clock 'sys'\n");
246 return PTR_ERR(prl->clk_sys);
249 prl->clk_ref = devm_clk_get(&pdev->dev, "ref");
250 if (IS_ERR(prl->clk_ref)) {
251 if (PTR_ERR(prl->clk_ref) != -EPROBE_DEFER)
252 dev_err(dev, "Failed to acquire clock 'ref'\n");
253 return PTR_ERR(prl->clk_ref);
256 ret = clk_prepare_enable(prl->clk_sys);
260 img_prl_out_writel(prl, IMG_PRL_OUT_CTL_EDGE_MASK, IMG_PRL_OUT_CTL);
261 img_prl_out_reset(prl);
263 pm_runtime_enable(&pdev->dev);
264 if (!pm_runtime_enabled(&pdev->dev)) {
265 ret = img_prl_out_resume(&pdev->dev);
270 prl->dma_data.addr = res->start + IMG_PRL_OUT_TX_FIFO;
271 prl->dma_data.addr_width = 4;
272 prl->dma_data.maxburst = 4;
274 ret = devm_snd_soc_register_component(&pdev->dev,
275 &img_prl_out_component,
276 &img_prl_out_dai, 1);
280 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
287 if (!pm_runtime_status_suspended(&pdev->dev))
288 img_prl_out_suspend(&pdev->dev);
290 pm_runtime_disable(&pdev->dev);
291 clk_disable_unprepare(prl->clk_sys);
296 static int img_prl_out_dev_remove(struct platform_device *pdev)
298 struct img_prl_out *prl = platform_get_drvdata(pdev);
300 pm_runtime_disable(&pdev->dev);
301 if (!pm_runtime_status_suspended(&pdev->dev))
302 img_prl_out_suspend(&pdev->dev);
304 clk_disable_unprepare(prl->clk_sys);
309 static const struct of_device_id img_prl_out_of_match[] = {
310 { .compatible = "img,parallel-out" },
313 MODULE_DEVICE_TABLE(of, img_prl_out_of_match);
315 static const struct dev_pm_ops img_prl_out_pm_ops = {
316 SET_RUNTIME_PM_OPS(img_prl_out_suspend,
317 img_prl_out_resume, NULL)
320 static struct platform_driver img_prl_out_driver = {
322 .name = "img-parallel-out",
323 .of_match_table = img_prl_out_of_match,
324 .pm = &img_prl_out_pm_ops
326 .probe = img_prl_out_probe,
327 .remove = img_prl_out_dev_remove
329 module_platform_driver(img_prl_out_driver);
331 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
332 MODULE_DESCRIPTION("IMG Parallel Output Driver");
333 MODULE_LICENSE("GPL v2");