sound/soc/hisilicon/hi6210-i2s.c

   1 /*
   2  * linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
   3  *
   4  * Copyright (C) 2015 Linaro, Ltd
   5  * Author: Andy Green <andy.green@linaro.org>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * This driver only deals with S2 interface (BT)
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21 #include <linux/device.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/io.h>
  26 #include <linux/gpio.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/dmaengine_pcm.h>
  31 #include <sound/initval.h>
  32 #include <sound/soc.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/reset.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/mfd/syscon.h>
  38 #include <linux/reset-controller.h>
  39
  40 #include "hi6210-i2s.h"
  41
  42 struct hi6210_i2s {
  43         struct device *dev;
  44         struct reset_control *rc;
  45         struct clk *clk[8];
  46         int clocks;
  47         struct snd_soc_dai_driver dai;
  48         void __iomem *base;
  49         struct regmap *sysctrl;
  50         phys_addr_t base_phys;
  51         struct snd_dmaengine_dai_dma_data dma_data[2];
  52         int clk_rate;
  53         spinlock_t lock;
  54         int rate;
  55         int format;
  56         u8 bits;
  57         u8 channels;
  58         u8 id;
  59         u8 channel_length;
  60         u8 use;
  61         u32 master:1;
  62         u32 status:1;
  63 };
  64
  65 #define SC_PERIPH_CLKEN1        0x210
  66 #define SC_PERIPH_CLKDIS1       0x214
  67
  68 #define SC_PERIPH_CLKEN3        0x230
  69 #define SC_PERIPH_CLKDIS3       0x234
  70
  71 #define SC_PERIPH_CLKEN12       0x270
  72 #define SC_PERIPH_CLKDIS12      0x274
  73
  74 #define SC_PERIPH_RSTEN1        0x310
  75 #define SC_PERIPH_RSTDIS1       0x314
  76 #define SC_PERIPH_RSTSTAT1      0x318
  77
  78 #define SC_PERIPH_RSTEN2        0x320
  79 #define SC_PERIPH_RSTDIS2       0x324
  80 #define SC_PERIPH_RSTSTAT2      0x328
  81
  82 #define SOC_PMCTRL_BBPPLLALIAS  0x48
  83
  84 enum {
  85         CLK_DACODEC,
  86         CLK_I2S_BASE,
  87 };
  88
  89 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)
  90 {
  91         writel(val, i2s->base + reg);
  92 }
  93
  94 static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)
  95 {
  96         return readl(i2s->base + reg);
  97 }
  98
  99 static int hi6210_i2s_startup(struct snd_pcm_substream *substream,
 100                               struct snd_soc_dai *cpu_dai)
 101 {
 102         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 103         int ret, n;
 104         u32 val;
 105
 106         /* deassert reset on ABB */
 107         regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
 108         if (val & BIT(4))
 109                 regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));
 110
 111         for (n = 0; n < i2s->clocks; n++) {
 112                 ret = clk_prepare_enable(i2s->clk[n]);
 113                 if (ret)
 114                         goto err_unprepare_clk;
 115         }
 116
 117         ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);
 118         if (ret) {
 119                 dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",
 120                         __func__, ret);
 121                 goto err_unprepare_clk;
 122         }
 123
 124         /* enable clock before frequency division */
 125         regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));
 126
 127         /* enable codec working clock / == "codec bus clock" */
 128         regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));
 129
 130         /* deassert reset on codec / interface clock / working clock */
 131         regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
 132         regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));
 133
 134         /* not interested in i2s irqs */
 135         val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
 136         val |= 0x3f;
 137         hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
 138
 139
 140         /* reset the stereo downlink fifo */
 141         val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
 142         val |= (BIT(5) | BIT(4));
 143         hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
 144
 145         val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
 146         val &= ~(BIT(5) | BIT(4));
 147         hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
 148
 149
 150         val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
 151         val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK <<
 152                         HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
 153         val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
 154         hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
 155
 156         val = hi6210_read_reg(i2s, HII2S_MISC_CFG);
 157         /* mux 11/12 = APB not i2s */
 158         val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL;
 159         /* BT R ch  0 = mixer op of DACR ch */
 160         val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
 161         val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
 162
 163         val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
 164         /* BT L ch = 1 = mux 7 = "mixer output of DACL */
 165         val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
 166         hi6210_write_reg(i2s, HII2S_MISC_CFG, val);
 167
 168         val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
 169         val |= HII2S_SW_RST_N__SW_RST_N;
 170         hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
 171
 172         return 0;
 173
 174 err_unprepare_clk:
 175         while (n--)
 176                 clk_disable_unprepare(i2s->clk[n]);
 177         return ret;
 178 }
 179
 180 static void hi6210_i2s_shutdown(struct snd_pcm_substream *substream,
 181                                 struct snd_soc_dai *cpu_dai)
 182 {
 183         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 184         int n;
 185
 186         for (n = 0; n < i2s->clocks; n++)
 187                 clk_disable_unprepare(i2s->clk[n]);
 188
 189         regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
 190 }
 191
 192 static void hi6210_i2s_txctrl(struct snd_soc_dai *cpu_dai, int on)
 193 {
 194         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 195         u32 val;
 196
 197         spin_lock(&i2s->lock);
 198         if (on) {
 199                 /* enable S2 TX */
 200                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 201                 val |= HII2S_I2S_CFG__S2_IF_TX_EN;
 202                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 203         } else {
 204                 /* disable S2 TX */
 205                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 206                 val &= ~HII2S_I2S_CFG__S2_IF_TX_EN;
 207                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 208         }
 209         spin_unlock(&i2s->lock);
 210 }
 211
 212 static void hi6210_i2s_rxctrl(struct snd_soc_dai *cpu_dai, int on)
 213 {
 214         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 215         u32 val;
 216
 217         spin_lock(&i2s->lock);
 218         if (on) {
 219                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 220                 val |= HII2S_I2S_CFG__S2_IF_RX_EN;
 221                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 222         } else {
 223                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 224                 val &= ~HII2S_I2S_CFG__S2_IF_RX_EN;
 225                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 226         }
 227         spin_unlock(&i2s->lock);
 228 }
 229
 230 static int hi6210_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 231 {
 232         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 233
 234         /*
 235          * We don't actually set the hardware until the hw_params
 236          * call, but we need to validate the user input here.
 237          */
 238         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 239         case SND_SOC_DAIFMT_CBM_CFM:
 240         case SND_SOC_DAIFMT_CBS_CFS:
 241                 break;
 242         default:
 243                 return -EINVAL;
 244         }
 245
 246         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 247         case SND_SOC_DAIFMT_I2S:
 248         case SND_SOC_DAIFMT_LEFT_J:
 249         case SND_SOC_DAIFMT_RIGHT_J:
 250                 break;
 251         default:
 252                 return -EINVAL;
 253         }
 254
 255         i2s->format = fmt;
 256         i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
 257                       SND_SOC_DAIFMT_CBS_CFS;
 258
 259         return 0;
 260 }
 261
 262 static int hi6210_i2s_hw_params(struct snd_pcm_substream *substream,
 263                             struct snd_pcm_hw_params *params,
 264                             struct snd_soc_dai *cpu_dai)
 265 {
 266         struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
 267         u32 bits = 0, rate = 0, signed_data = 0, fmt = 0;
 268         u32 val;
 269         struct snd_dmaengine_dai_dma_data *dma_data;
 270
 271         switch (params_format(params)) {
 272         case SNDRV_PCM_FORMAT_U16_LE:
 273                 signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
 274                 /* fallthru */
 275         case SNDRV_PCM_FORMAT_S16_LE:
 276                 bits = HII2S_BITS_16;
 277                 break;
 278         case SNDRV_PCM_FORMAT_U24_LE:
 279                 signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
 280                 /* fallthru */
 281         case SNDRV_PCM_FORMAT_S24_LE:
 282                 bits = HII2S_BITS_24;
 283                 break;
 284         default:
 285                 dev_err(cpu_dai->dev, "Bad format\n");
 286                 return -EINVAL;
 287         }
 288
 289
 290         switch (params_rate(params)) {
 291         case 8000:
 292                 rate = HII2S_FS_RATE_8KHZ;
 293                 break;
 294         case 16000:
 295                 rate = HII2S_FS_RATE_16KHZ;
 296                 break;
 297         case 32000:
 298                 rate = HII2S_FS_RATE_32KHZ;
 299                 break;
 300         case 48000:
 301                 rate = HII2S_FS_RATE_48KHZ;
 302                 break;
 303         case 96000:
 304                 rate = HII2S_FS_RATE_96KHZ;
 305                 break;
 306         case 192000:
 307                 rate = HII2S_FS_RATE_192KHZ;
 308                 break;
 309         default:
 310                 dev_err(cpu_dai->dev, "Bad rate: %d\n", params_rate(params));
 311                 return -EINVAL;
 312         }
 313
 314         if (!(params_channels(params))) {
 315                 dev_err(cpu_dai->dev, "Bad channels\n");
 316                 return -EINVAL;
 317         }
 318
 319         dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
 320
 321         switch (bits) {
 322         case HII2S_BITS_24:
 323                 i2s->bits = 32;
 324                 dma_data->addr_width = 3;
 325                 break;
 326         default:
 327                 i2s->bits = 16;
 328                 dma_data->addr_width = 2;
 329                 break;
 330         }
 331         i2s->rate = params_rate(params);
 332         i2s->channels = params_channels(params);
 333         i2s->channel_length = i2s->channels * i2s->bits;
 334
 335         val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);
 336         val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK <<
 337                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
 338                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK <<
 339                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
 340                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK <<
 341                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
 342                 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK <<
 343                         HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
 344         val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
 345                 (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
 346                 (16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
 347                 (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
 348         hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);
 349
 350
 351         val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);
 352         val |= (BIT(19) | BIT(18) | BIT(17) |
 353                 HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN |
 354                 HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN |
 355                 HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN |
 356                 HII2S_IF_CLK_EN_CFG__ST_DL_R_EN |
 357                 HII2S_IF_CLK_EN_CFG__ST_DL_L_EN);
 358         hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);
 359
 360
 361         val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);
 362         val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN |
 363                  HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN |
 364                  HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN |
 365                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN |
 366                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN |
 367                  HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN);
 368         val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN |
 369                 HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN);
 370         hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);
 371
 372
 373         val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);
 374         val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE |
 375                  HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE);
 376         hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);
 377
 378         val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);
 379         val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE |
 380                  HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE |
 381                  HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE |
 382                  HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE);
 383         hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);
 384
 385
 386         switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
 387         case SND_SOC_DAIFMT_CBM_CFM:
 388                 i2s->master = false;
 389                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 390                 val |= HII2S_I2S_CFG__S2_MST_SLV;
 391                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 392                 break;
 393         case SND_SOC_DAIFMT_CBS_CFS:
 394                 i2s->master = true;
 395                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 396                 val &= ~HII2S_I2S_CFG__S2_MST_SLV;
 397                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 398                 break;
 399         default:
 400                 WARN_ONCE(1, "Invalid i2s->fmt MASTER_MASK. This shouldn't happen\n");
 401                 return -EINVAL;
 402         }
 403
 404         switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
 405         case SND_SOC_DAIFMT_I2S:
 406                 fmt = HII2S_FORMAT_I2S;
 407                 break;
 408         case SND_SOC_DAIFMT_LEFT_J:
 409                 fmt = HII2S_FORMAT_LEFT_JUST;
 410                 break;
 411         case SND_SOC_DAIFMT_RIGHT_J:
 412                 fmt = HII2S_FORMAT_RIGHT_JUST;
 413                 break;
 414         default:
 415                 WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");
 416                 return -EINVAL;
 417         }
 418
 419         val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 420         val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK <<
 421                         HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT);
 422         val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT;
 423         hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 424
 425
 426         val = hi6210_read_reg(i2s, HII2S_CLK_SEL);
 427         val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */
 428                         HII2S_CLK_SEL__EXT_12_288MHZ_SEL);
 429         hi6210_write_reg(i2s, HII2S_CLK_SEL, val);
 430
 431         dma_data->maxburst = 2;
 432
 433         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 434                 dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;
 435         else
 436                 dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;
 437
 438         switch (i2s->channels) {
 439         case 1:
 440                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 441                 val |= HII2S_I2S_CFG__S2_FRAME_MODE;
 442                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 443                 break;
 444         default:
 445                 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 446                 val &= ~HII2S_I2S_CFG__S2_FRAME_MODE;
 447                 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 448                 break;
 449         }
 450
 451         /* clear loopback, set signed type and word length */
 452         val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
 453         val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
 454         val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK <<
 455                         HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
 456         val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK <<
 457                         HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT);
 458         val |= signed_data;
 459         val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
 460         hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
 461
 462
 463         if (!i2s->master)
 464                 return 0;
 465
 466         /* set DAC and related units to correct rate */
 467         val = hi6210_read_reg(i2s, HII2S_FS_CFG);
 468         val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT);
 469         val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT);
 470         val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK <<
 471                                         HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
 472         val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK <<
 473                                         HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
 474         val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT);
 475         val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT);
 476         val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
 477         val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
 478         hi6210_write_reg(i2s, HII2S_FS_CFG, val);
 479
 480         return 0;
 481 }
 482
 483 static int hi6210_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 484                           struct snd_soc_dai *cpu_dai)
 485 {
 486         pr_debug("%s\n", __func__);
 487         switch (cmd) {
 488         case SNDRV_PCM_TRIGGER_START:
 489         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 490                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 491                         hi6210_i2s_rxctrl(cpu_dai, 1);
 492                 else
 493                         hi6210_i2s_txctrl(cpu_dai, 1);
 494                 break;
 495         case SNDRV_PCM_TRIGGER_STOP:
 496         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 497                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 498                         hi6210_i2s_rxctrl(cpu_dai, 0);
 499                 else
 500                         hi6210_i2s_txctrl(cpu_dai, 0);
 501                 break;
 502         default:
 503                 dev_err(cpu_dai->dev, "unknown cmd\n");
 504                 return -EINVAL;
 505         }
 506         return 0;
 507 }
 508
 509 static int hi6210_i2s_dai_probe(struct snd_soc_dai *dai)
 510 {
 511         struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 512
 513         snd_soc_dai_init_dma_data(dai,
 514                                   &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
 515                                   &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
 516
 517         return 0;
 518 }
 519
 520
 521 static const struct snd_soc_dai_ops hi6210_i2s_dai_ops = {
 522         .trigger        = hi6210_i2s_trigger,
 523         .hw_params      = hi6210_i2s_hw_params,
 524         .set_fmt        = hi6210_i2s_set_fmt,
 525         .startup        = hi6210_i2s_startup,
 526         .shutdown       = hi6210_i2s_shutdown,
 527 };
 528
 529 static const struct snd_soc_dai_driver hi6210_i2s_dai_init = {
 530         .probe          = hi6210_i2s_dai_probe,
 531         .playback = {
 532                 .channels_min = 2,
 533                 .channels_max = 2,
 534                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 535                            SNDRV_PCM_FMTBIT_U16_LE,
 536                 .rates = SNDRV_PCM_RATE_48000,
 537         },
 538         .capture = {
 539                 .channels_min = 2,
 540                 .channels_max = 2,
 541                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 542                            SNDRV_PCM_FMTBIT_U16_LE,
 543                 .rates = SNDRV_PCM_RATE_48000,
 544         },
 545         .ops = &hi6210_i2s_dai_ops,
 546 };
 547
 548 static const struct snd_soc_component_driver hi6210_i2s_i2s_comp = {
 549         .name = "hi6210_i2s-i2s",
 550 };
 551
 552 static int hi6210_i2s_probe(struct platform_device *pdev)
 553 {
 554         struct device_node *node = pdev->dev.of_node;
 555         struct device *dev = &pdev->dev;
 556         struct hi6210_i2s *i2s;
 557         struct resource *res;
 558         int ret;
 559
 560         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 561         if (!i2s)
 562                 return -ENOMEM;
 563
 564         i2s->dev = dev;
 565         spin_lock_init(&i2s->lock);
 566
 567         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 568         i2s->base = devm_ioremap_resource(dev, res);
 569         if (IS_ERR(i2s->base))
 570                 return PTR_ERR(i2s->base);
 571
 572         i2s->base_phys = (phys_addr_t)res->start;
 573         i2s->dai = hi6210_i2s_dai_init;
 574
 575         dev_set_drvdata(&pdev->dev, i2s);
 576
 577         i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,
 578                                                 "hisilicon,sysctrl-syscon");
 579         if (IS_ERR(i2s->sysctrl))
 580                 return PTR_ERR(i2s->sysctrl);
 581
 582         i2s->clk[CLK_DACODEC] = devm_clk_get(&pdev->dev, "dacodec");
 583         if (IS_ERR_OR_NULL(i2s->clk[CLK_DACODEC]))
 584                 return PTR_ERR(i2s->clk[CLK_DACODEC]);
 585         i2s->clocks++;
 586
 587         i2s->clk[CLK_I2S_BASE] = devm_clk_get(&pdev->dev, "i2s-base");
 588         if (IS_ERR_OR_NULL(i2s->clk[CLK_I2S_BASE]))
 589                 return PTR_ERR(i2s->clk[CLK_I2S_BASE]);
 590         i2s->clocks++;
 591
 592         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 593         if (ret)
 594                 return ret;
 595
 596         ret = devm_snd_soc_register_component(&pdev->dev, &hi6210_i2s_i2s_comp,
 597                                          &i2s->dai, 1);
 598         return ret;
 599 }
 600
 601 static const struct of_device_id hi6210_i2s_dt_ids[] = {
 602         { .compatible = "hisilicon,hi6210-i2s" },
 603         { /* sentinel */ }
 604 };
 605
 606 MODULE_DEVICE_TABLE(of, hi6210_i2s_dt_ids);
 607
 608 static struct platform_driver hi6210_i2s_driver = {
 609         .probe = hi6210_i2s_probe,
 610         .driver = {
 611                 .name = "hi6210_i2s",
 612                 .of_match_table = hi6210_i2s_dt_ids,
 613         },
 614 };
 615
 616 module_platform_driver(hi6210_i2s_driver);
 617
 618 MODULE_DESCRIPTION("Hisilicon HI6210 I2S driver");
 619 MODULE_AUTHOR("Andy Green <andy.green@linaro.org>");
 620 MODULE_LICENSE("GPL");