1 // SPDX-License-Identifier: GPL-2.0+
3 // imx-ssi.c -- ALSA Soc Audio Layer
5 // Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
7 // This code is based on code copyrighted by Freescale,
8 // Liam Girdwood, Javier Martin and probably others.
10 // The i.MX SSI core has some nasty limitations in AC97 mode. While most
11 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
12 // one FIFO which combines all valid receive slots. We cannot even select
13 // which slots we want to receive. The WM9712 with which this driver
14 // was developed with always sends GPIO status data in slot 12 which
15 // we receive in our (PCM-) data stream. The only chance we have is to
16 // manually skip this data in the FIQ handler. With sampling rates different
17 // from 48000Hz not every frame has valid receive data, so the ratio
18 // between pcm data and GPIO status data changes. Our FIQ handler is not
19 // able to handle this, hence this driver only works with 48000Hz sampling
21 // Reading and writing AC97 registers is another challenge. The core
22 // provides us status bits when the read register is updated with *another*
23 // value. When we read the same register two times (and the register still
24 // contains the same value) these status bits are not set. We work
25 // around this by not polling these bits but only wait a fixed delay.
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
33 #include <linux/module.h>
34 #include <linux/platform_device.h>
35 #include <linux/slab.h>
37 #include <sound/core.h>
38 #include <sound/initval.h>
39 #include <sound/pcm.h>
40 #include <sound/pcm_params.h>
41 #include <sound/soc.h>
43 #include <linux/platform_data/asoc-imx-ssi.h>
46 #include "fsl_utils.h"
48 #define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
51 * SSI Network Mode or TDM slots configuration.
52 * Should only be called when port is inactive (i.e. SSIEN = 0).
54 static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
55 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
57 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
60 sccr = readl(ssi->base + SSI_STCCR);
61 sccr &= ~SSI_STCCR_DC_MASK;
62 sccr |= SSI_STCCR_DC(slots - 1);
63 writel(sccr, ssi->base + SSI_STCCR);
65 sccr = readl(ssi->base + SSI_SRCCR);
66 sccr &= ~SSI_STCCR_DC_MASK;
67 sccr |= SSI_STCCR_DC(slots - 1);
68 writel(sccr, ssi->base + SSI_SRCCR);
70 writel(~tx_mask, ssi->base + SSI_STMSK);
71 writel(~rx_mask, ssi->base + SSI_SRMSK);
77 * SSI DAI format configuration.
78 * Should only be called when port is inactive (i.e. SSIEN = 0).
80 static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
82 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
85 scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
88 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
89 case SND_SOC_DAIFMT_I2S:
90 /* data on rising edge of bclk, frame low 1clk before data */
91 strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSI |
94 if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
95 scr &= ~SSI_I2S_MODE_MASK;
96 scr |= SSI_SCR_I2S_MODE_SLAVE;
99 case SND_SOC_DAIFMT_LEFT_J:
100 /* data on rising edge of bclk, frame high with data */
101 strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP;
103 case SND_SOC_DAIFMT_DSP_B:
104 /* data on rising edge of bclk, frame high with data */
105 strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSL;
107 case SND_SOC_DAIFMT_DSP_A:
108 /* data on rising edge of bclk, frame high 1clk before data */
109 strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSL |
114 /* DAI clock inversion */
115 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
116 case SND_SOC_DAIFMT_IB_IF:
117 strcr ^= SSI_STCR_TSCKP | SSI_STCR_TFSI;
119 case SND_SOC_DAIFMT_IB_NF:
120 strcr ^= SSI_STCR_TSCKP;
122 case SND_SOC_DAIFMT_NB_IF:
123 strcr ^= SSI_STCR_TFSI;
125 case SND_SOC_DAIFMT_NB_NF:
129 /* DAI clock master masks */
130 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
131 case SND_SOC_DAIFMT_CBM_CFM:
134 /* Master mode not implemented, needs handling of clocks. */
138 strcr |= SSI_STCR_TFEN0;
140 if (ssi->flags & IMX_SSI_NET)
142 if (ssi->flags & IMX_SSI_SYN)
145 writel(strcr, ssi->base + SSI_STCR);
146 writel(strcr, ssi->base + SSI_SRCR);
147 writel(scr, ssi->base + SSI_SCR);
153 * SSI system clock configuration.
154 * Should only be called when port is inactive (i.e. SSIEN = 0).
156 static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
157 int clk_id, unsigned int freq, int dir)
159 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
162 scr = readl(ssi->base + SSI_SCR);
165 case IMX_SSP_SYS_CLK:
166 if (dir == SND_SOC_CLOCK_OUT)
167 scr |= SSI_SCR_SYS_CLK_EN;
169 scr &= ~SSI_SCR_SYS_CLK_EN;
175 writel(scr, ssi->base + SSI_SCR);
182 * Should only be called when port is inactive (i.e. SSIEN = 0).
184 static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
187 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
190 stccr = readl(ssi->base + SSI_STCCR);
191 srccr = readl(ssi->base + SSI_SRCCR);
194 case IMX_SSI_TX_DIV_2:
195 stccr &= ~SSI_STCCR_DIV2;
198 case IMX_SSI_TX_DIV_PSR:
199 stccr &= ~SSI_STCCR_PSR;
202 case IMX_SSI_TX_DIV_PM:
204 stccr |= SSI_STCCR_PM(div);
206 case IMX_SSI_RX_DIV_2:
207 stccr &= ~SSI_STCCR_DIV2;
210 case IMX_SSI_RX_DIV_PSR:
211 stccr &= ~SSI_STCCR_PSR;
214 case IMX_SSI_RX_DIV_PM:
216 stccr |= SSI_STCCR_PM(div);
222 writel(stccr, ssi->base + SSI_STCCR);
223 writel(srccr, ssi->base + SSI_SRCCR);
229 * Should only be called when port is inactive (i.e. SSIEN = 0),
230 * although can be called multiple times by upper layers.
232 static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
233 struct snd_pcm_hw_params *params,
234 struct snd_soc_dai *cpu_dai)
236 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
240 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
245 if (ssi->flags & IMX_SSI_SYN)
248 sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
250 /* DAI data (word) size */
251 switch (params_format(params)) {
252 case SNDRV_PCM_FORMAT_S16_LE:
253 sccr |= SSI_SRCCR_WL(16);
255 case SNDRV_PCM_FORMAT_S20_3LE:
256 sccr |= SSI_SRCCR_WL(20);
258 case SNDRV_PCM_FORMAT_S24_LE:
259 sccr |= SSI_SRCCR_WL(24);
263 writel(sccr, ssi->base + reg);
268 static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
269 struct snd_soc_dai *dai)
271 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(dai);
272 unsigned int sier_bits, sier;
275 scr = readl(ssi->base + SSI_SCR);
276 sier = readl(ssi->base + SSI_SIER);
278 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
279 if (ssi->flags & IMX_SSI_DMA)
280 sier_bits = SSI_SIER_TDMAE;
282 sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
284 if (ssi->flags & IMX_SSI_DMA)
285 sier_bits = SSI_SIER_RDMAE;
287 sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
291 case SNDRV_PCM_TRIGGER_START:
292 case SNDRV_PCM_TRIGGER_RESUME:
293 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
294 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
300 scr |= SSI_SCR_SSIEN;
304 case SNDRV_PCM_TRIGGER_STOP:
305 case SNDRV_PCM_TRIGGER_SUSPEND:
306 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
307 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
313 if (!(scr & (SSI_SCR_TE | SSI_SCR_RE)))
314 scr &= ~SSI_SCR_SSIEN;
321 if (!(ssi->flags & IMX_SSI_USE_AC97))
322 /* rx/tx are always enabled to access ac97 registers */
323 writel(scr, ssi->base + SSI_SCR);
325 writel(sier, ssi->base + SSI_SIER);
330 static const struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
331 .hw_params = imx_ssi_hw_params,
332 .set_fmt = imx_ssi_set_dai_fmt,
333 .set_clkdiv = imx_ssi_set_dai_clkdiv,
334 .set_sysclk = imx_ssi_set_dai_sysclk,
335 .set_tdm_slot = imx_ssi_set_dai_tdm_slot,
336 .trigger = imx_ssi_trigger,
339 static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
341 struct imx_ssi *ssi = dev_get_drvdata(dai->dev);
344 snd_soc_dai_set_drvdata(dai, ssi);
346 val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.maxburst) |
347 SSI_SFCSR_RFWM0(ssi->dma_params_rx.maxburst);
348 writel(val, ssi->base + SSI_SFCSR);
351 dai->playback_dma_data = &ssi->dma_params_tx;
352 dai->capture_dma_data = &ssi->dma_params_rx;
357 static struct snd_soc_dai_driver imx_ssi_dai = {
358 .probe = imx_ssi_dai_probe,
362 .rates = SNDRV_PCM_RATE_8000_96000,
363 .formats = SNDRV_PCM_FMTBIT_S16_LE,
368 .rates = SNDRV_PCM_RATE_8000_96000,
369 .formats = SNDRV_PCM_FMTBIT_S16_LE,
371 .ops = &imx_ssi_pcm_dai_ops,
374 static struct snd_soc_dai_driver imx_ac97_dai = {
375 .probe = imx_ssi_dai_probe,
377 .stream_name = "AC97 Playback",
380 .rates = SNDRV_PCM_RATE_8000_48000,
381 .formats = SNDRV_PCM_FMTBIT_S16_LE,
384 .stream_name = "AC97 Capture",
387 .rates = SNDRV_PCM_RATE_48000,
388 .formats = SNDRV_PCM_FMTBIT_S16_LE,
390 .ops = &imx_ssi_pcm_dai_ops,
393 static const struct snd_soc_component_driver imx_component = {
397 static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
399 void __iomem *base = imx_ssi->base;
401 writel(0x0, base + SSI_SCR);
402 writel(0x0, base + SSI_STCR);
403 writel(0x0, base + SSI_SRCR);
405 writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
407 writel(SSI_SFCSR_RFWM0(8) |
410 SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
412 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
413 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
415 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
416 writel(SSI_SOR_WAIT(3), base + SSI_SOR);
418 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
419 SSI_SCR_TE | SSI_SCR_RE,
422 writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
423 writel(0xff, base + SSI_SACCDIS);
424 writel(0x300, base + SSI_SACCEN);
427 static struct imx_ssi *ac97_ssi;
429 static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
432 struct imx_ssi *imx_ssi = ac97_ssi;
433 void __iomem *base = imx_ssi->base;
440 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
443 writel(lreg, base + SSI_SACADD);
446 writel(lval , base + SSI_SACDAT);
448 writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
452 static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
455 struct imx_ssi *imx_ssi = ac97_ssi;
456 void __iomem *base = imx_ssi->base;
458 unsigned short val = -1;
461 lreg = (reg & 0x7f) << 12 ;
462 writel(lreg, base + SSI_SACADD);
463 writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
467 val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
469 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
474 static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
476 struct imx_ssi *imx_ssi = ac97_ssi;
478 if (imx_ssi->ac97_reset)
479 imx_ssi->ac97_reset(ac97);
480 /* First read sometimes fails, do a dummy read */
481 imx_ssi_ac97_read(ac97, 0);
484 static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
486 struct imx_ssi *imx_ssi = ac97_ssi;
488 if (imx_ssi->ac97_warm_reset)
489 imx_ssi->ac97_warm_reset(ac97);
491 /* First read sometimes fails, do a dummy read */
492 imx_ssi_ac97_read(ac97, 0);
495 static struct snd_ac97_bus_ops imx_ssi_ac97_ops = {
496 .read = imx_ssi_ac97_read,
497 .write = imx_ssi_ac97_write,
498 .reset = imx_ssi_ac97_reset,
499 .warm_reset = imx_ssi_ac97_warm_reset
502 static int imx_ssi_probe(struct platform_device *pdev)
504 struct resource *res;
506 struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
508 struct snd_soc_dai_driver *dai;
510 ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
513 dev_set_drvdata(&pdev->dev, ssi);
516 ssi->ac97_reset = pdata->ac97_reset;
517 ssi->ac97_warm_reset = pdata->ac97_warm_reset;
518 ssi->flags = pdata->flags;
521 ssi->irq = platform_get_irq(pdev, 0);
525 ssi->clk = devm_clk_get(&pdev->dev, NULL);
526 if (IS_ERR(ssi->clk)) {
527 ret = PTR_ERR(ssi->clk);
528 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
532 ret = clk_prepare_enable(ssi->clk);
536 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
537 ssi->base = devm_ioremap_resource(&pdev->dev, res);
538 if (IS_ERR(ssi->base)) {
539 ret = PTR_ERR(ssi->base);
540 goto failed_register;
543 if (ssi->flags & IMX_SSI_USE_AC97) {
545 dev_err(&pdev->dev, "AC'97 SSI already registered\n");
547 goto failed_register;
550 setup_channel_to_ac97(ssi);
555 writel(0x0, ssi->base + SSI_SIER);
557 ssi->dma_params_rx.addr = res->start + SSI_SRX0;
558 ssi->dma_params_tx.addr = res->start + SSI_STX0;
560 ssi->dma_params_tx.maxburst = 6;
561 ssi->dma_params_rx.maxburst = 4;
563 ssi->dma_params_tx.filter_data = &ssi->filter_data_tx;
564 ssi->dma_params_rx.filter_data = &ssi->filter_data_rx;
566 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
568 imx_pcm_dma_params_init_data(&ssi->filter_data_tx, res->start,
572 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
574 imx_pcm_dma_params_init_data(&ssi->filter_data_rx, res->start,
578 platform_set_drvdata(pdev, ssi);
580 ret = snd_soc_set_ac97_ops(&imx_ssi_ac97_ops);
582 dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
583 goto failed_register;
586 ret = snd_soc_register_component(&pdev->dev, &imx_component,
589 dev_err(&pdev->dev, "register DAI failed\n");
590 goto failed_register;
593 ssi->fiq_params.irq = ssi->irq;
594 ssi->fiq_params.base = ssi->base;
595 ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
596 ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
598 ssi->fiq_init = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
599 ssi->dma_init = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
601 if (ssi->fiq_init && ssi->dma_init) {
609 snd_soc_unregister_component(&pdev->dev);
611 clk_disable_unprepare(ssi->clk);
613 snd_soc_set_ac97_ops(NULL);
618 static int imx_ssi_remove(struct platform_device *pdev)
620 struct imx_ssi *ssi = platform_get_drvdata(pdev);
623 imx_pcm_fiq_exit(pdev);
625 snd_soc_unregister_component(&pdev->dev);
627 if (ssi->flags & IMX_SSI_USE_AC97)
630 clk_disable_unprepare(ssi->clk);
631 snd_soc_set_ac97_ops(NULL);
636 static struct platform_driver imx_ssi_driver = {
637 .probe = imx_ssi_probe,
638 .remove = imx_ssi_remove,
645 module_platform_driver(imx_ssi_driver);
647 /* Module information */
648 MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
649 MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
650 MODULE_LICENSE("GPL");
651 MODULE_ALIAS("platform:imx-ssi");