sound/soc/fsl/fsl_xcvr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright 2019 NXP
   3
   4 #include <linux/bitrev.h>
   5 #include <linux/clk.h>
   6 #include <linux/firmware.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/module.h>
   9 #include <linux/of_platform.h>
  10 #include <linux/pm_runtime.h>
  11 #include <linux/regmap.h>
  12 #include <linux/reset.h>
  13 #include <sound/dmaengine_pcm.h>
  14 #include <sound/pcm_iec958.h>
  15 #include <sound/pcm_params.h>
  16
  17 #include "fsl_xcvr.h"
  18 #include "imx-pcm.h"
  19
  20 #define FSL_XCVR_CAPDS_SIZE     256
  21
  22 struct fsl_xcvr_soc_data {
  23         const char *fw_name;
  24         bool spdif_only;
  25         bool use_edma;
  26 };
  27
  28 struct fsl_xcvr {
  29         const struct fsl_xcvr_soc_data *soc_data;
  30         struct platform_device *pdev;
  31         struct regmap *regmap;
  32         struct clk *ipg_clk;
  33         struct clk *pll_ipg_clk;
  34         struct clk *phy_clk;
  35         struct clk *spba_clk;
  36         struct reset_control *reset;
  37         u8 streams;
  38         u32 mode;
  39         u32 arc_mode;
  40         void __iomem *ram_addr;
  41         struct snd_dmaengine_dai_dma_data dma_prms_rx;
  42         struct snd_dmaengine_dai_dma_data dma_prms_tx;
  43         struct snd_aes_iec958 rx_iec958;
  44         struct snd_aes_iec958 tx_iec958;
  45         u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
  46 };
  47
  48 static const struct fsl_xcvr_pll_conf {
  49         u8 mfi;   /* min=0x18, max=0x38 */
  50         u32 mfn;  /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */
  51         u32 mfd;  /* unsigned int */
  52         u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */
  53 } fsl_xcvr_pll_cfg[] = {
  54         { .mfi = 54, .mfn = 1,  .mfd = 6,   .fout = 1300000000, }, /* 1.3 GHz */
  55         { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, },  /* 8000 Hz */
  56         { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, },  /* 11025 Hz */
  57         { .mfi = 29, .mfn = 1,  .mfd = 6,   .fout = 700000000, },  /* 700 MHz */
  58 };
  59
  60 /*
  61  * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
  62  * stream. Todo: to check how this case can be considered below
  63  */
  64 static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, };
  65 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = {
  66         .count = ARRAY_SIZE(fsl_xcvr_earc_channels),
  67         .list = fsl_xcvr_earc_channels,
  68 };
  69
  70 static const u32 fsl_xcvr_earc_rates[] = {
  71         32000, 44100, 48000, 64000, 88200, 96000,
  72         128000, 176400, 192000, 256000, 352800, 384000,
  73         512000, 705600, 768000, 1024000, 1411200, 1536000,
  74 };
  75 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = {
  76         .count = ARRAY_SIZE(fsl_xcvr_earc_rates),
  77         .list = fsl_xcvr_earc_rates,
  78 };
  79
  80 static const u32 fsl_xcvr_spdif_channels[] = { 2, };
  81 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = {
  82         .count = ARRAY_SIZE(fsl_xcvr_spdif_channels),
  83         .list = fsl_xcvr_spdif_channels,
  84 };
  85
  86 static const u32 fsl_xcvr_spdif_rates[] = {
  87         32000, 44100, 48000, 88200, 96000, 176400, 192000,
  88 };
  89 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = {
  90         .count = ARRAY_SIZE(fsl_xcvr_spdif_rates),
  91         .list = fsl_xcvr_spdif_rates,
  92 };
  93
  94 static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol,
  95                                  struct snd_ctl_elem_value *ucontrol)
  96 {
  97         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  98         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  99         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 100         unsigned int *item = ucontrol->value.enumerated.item;
 101
 102         xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]);
 103
 104         return 0;
 105 }
 106
 107 static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol,
 108                                  struct snd_ctl_elem_value *ucontrol)
 109 {
 110         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 111         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 112
 113         ucontrol->value.enumerated.item[0] = xcvr->arc_mode;
 114
 115         return 0;
 116 }
 117
 118 static const u32 fsl_xcvr_phy_arc_cfg[] = {
 119         FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN,
 120 };
 121
 122 static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", };
 123 static const struct soc_enum fsl_xcvr_arc_mode_enum =
 124         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode);
 125 static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl =
 126         SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum,
 127                      fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put);
 128
 129 /* Capabilities data structure, bytes */
 130 static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol,
 131                                           struct snd_ctl_elem_info *uinfo)
 132 {
 133         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 134         uinfo->count = FSL_XCVR_CAPDS_SIZE;
 135
 136         return 0;
 137 }
 138
 139 static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol,
 140                               struct snd_ctl_elem_value *ucontrol)
 141 {
 142         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 143         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 144
 145         memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE);
 146
 147         return 0;
 148 }
 149
 150 static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol,
 151                               struct snd_ctl_elem_value *ucontrol)
 152 {
 153         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 154         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 155
 156         memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE);
 157
 158         return 0;
 159 }
 160
 161 static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = {
 162         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 163         .name = "Capabilities Data Structure",
 164         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
 165         .info = fsl_xcvr_type_capds_bytes_info,
 166         .get = fsl_xcvr_capds_get,
 167         .put = fsl_xcvr_capds_put,
 168 };
 169
 170 static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name,
 171                                  bool active)
 172 {
 173         struct snd_soc_card *card = dai->component->card;
 174         struct snd_kcontrol *kctl;
 175         bool enabled;
 176
 177         lockdep_assert_held(&card->snd_card->controls_rwsem);
 178
 179         kctl = snd_soc_card_get_kcontrol_locked(card, name);
 180         if (kctl == NULL)
 181                 return -ENOENT;
 182
 183         enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0);
 184         if (active == enabled)
 185                 return 0; /* nothing to do */
 186
 187         if (active)
 188                 kctl->vd[0].access |=  SNDRV_CTL_ELEM_ACCESS_WRITE;
 189         else
 190                 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE;
 191
 192         snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
 193
 194         return 1;
 195 }
 196
 197 static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol,
 198                              struct snd_ctl_elem_value *ucontrol)
 199 {
 200         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 201         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 202         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 203         unsigned int *item = ucontrol->value.enumerated.item;
 204         struct snd_soc_card *card = dai->component->card;
 205         struct snd_soc_pcm_runtime *rtd;
 206
 207         xcvr->mode = snd_soc_enum_item_to_val(e, item[0]);
 208
 209         fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
 210                               (xcvr->mode == FSL_XCVR_MODE_ARC));
 211         fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
 212                               (xcvr->mode == FSL_XCVR_MODE_EARC));
 213         /* Allow playback for SPDIF only */
 214         rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
 215         rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count =
 216                 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0);
 217         return 0;
 218 }
 219
 220 static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol,
 221                              struct snd_ctl_elem_value *ucontrol)
 222 {
 223         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 224         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 225
 226         ucontrol->value.enumerated.item[0] = xcvr->mode;
 227
 228         return 0;
 229 }
 230
 231 static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", };
 232 static const struct soc_enum fsl_xcvr_mode_enum =
 233         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode);
 234 static struct snd_kcontrol_new fsl_xcvr_mode_kctl =
 235         SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum,
 236                      fsl_xcvr_mode_get, fsl_xcvr_mode_put);
 237
 238 /** phy: true => phy, false => pll */
 239 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
 240 {
 241         struct device *dev = &xcvr->pdev->dev;
 242         u32 val, idx, tidx;
 243         int ret;
 244
 245         idx  = BIT(phy ? 26 : 24);
 246         tidx = BIT(phy ? 27 : 25);
 247
 248         regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF);
 249         regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg);
 250         regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
 251         regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
 252
 253         ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
 254                                        (val & idx) == ((val & tidx) >> 1),
 255                                        10, 10000);
 256         if (ret)
 257                 dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n",
 258                         phy ? "PHY" : "PLL", reg, data);
 259         return ret;
 260 }
 261
 262 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
 263 {
 264         struct device *dev = &xcvr->pdev->dev;
 265         u32 i, div = 0, log2;
 266         int ret;
 267
 268         if (xcvr->soc_data->spdif_only)
 269                 return 0;
 270
 271         for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) {
 272                 if (fsl_xcvr_pll_cfg[i].fout % freq == 0) {
 273                         div = fsl_xcvr_pll_cfg[i].fout / freq;
 274                         break;
 275                 }
 276         }
 277
 278         if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg))
 279                 return -EINVAL;
 280
 281         log2 = ilog2(div);
 282
 283         /* Release AI interface from reset */
 284         ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
 285                            FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
 286         if (ret < 0) {
 287                 dev_err(dev, "Error while setting IER0: %d\n", ret);
 288                 return ret;
 289         }
 290
 291         /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */
 292         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET,
 293                           FSL_XCVR_PLL_BANDGAP_EN_VBG, 0);
 294
 295         /* PLL: CTRL0: DIV_INTEGER */
 296         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0);
 297         /* PLL: NUMERATOR: MFN */
 298         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0);
 299         /* PLL: DENOMINATOR: MFD */
 300         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0);
 301         /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */
 302         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
 303                           FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0);
 304         udelay(25);
 305         /* PLL: CTRL0: Clear Hold Ring Off */
 306         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR,
 307                           FSL_XCVR_PLL_CTRL0_HROFF, 0);
 308         udelay(100);
 309         if (tx) { /* TX is enabled for SPDIF only */
 310                 /* PLL: POSTDIV: PDIV0 */
 311                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
 312                                   FSL_XCVR_PLL_PDIVx(log2, 0), 0);
 313                 /* PLL: CTRL_SET: CLKMUX0_EN */
 314                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
 315                                   FSL_XCVR_PLL_CTRL0_CM0_EN, 0);
 316         } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
 317                 /* PLL: POSTDIV: PDIV1 */
 318                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
 319                                   FSL_XCVR_PLL_PDIVx(log2, 1), 0);
 320                 /* PLL: CTRL_SET: CLKMUX1_EN */
 321                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
 322                                   FSL_XCVR_PLL_CTRL0_CM1_EN, 0);
 323         } else { /* SPDIF / ARC RX */
 324                 /* PLL: POSTDIV: PDIV2 */
 325                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
 326                                   FSL_XCVR_PLL_PDIVx(log2, 2), 0);
 327                 /* PLL: CTRL_SET: CLKMUX2_EN */
 328                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
 329                                   FSL_XCVR_PLL_CTRL0_CM2_EN, 0);
 330         }
 331
 332         if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
 333                 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
 334                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
 335                                   FSL_XCVR_PHY_CTRL_TSDIFF_OE |
 336                                   FSL_XCVR_PHY_CTRL_PHY_EN, 1);
 337                 /* PHY: CTRL2_SET: EARC_TX_MODE */
 338                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
 339                                   FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
 340         } else if (!tx) { /* SPDIF / ARC RX mode */
 341                 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
 342                         /* PHY: CTRL_SET: SPDIF_EN */
 343                         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
 344                                           FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
 345                 else    /* PHY: CTRL_SET: ARC RX setup */
 346                         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
 347                                           FSL_XCVR_PHY_CTRL_PHY_EN |
 348                                           FSL_XCVR_PHY_CTRL_RX_CM_EN |
 349                                           fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1);
 350         }
 351
 352         dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n",
 353                 freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi,
 354                 fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2);
 355         return 0;
 356 }
 357
 358 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
 359 {
 360         struct device *dev = &xcvr->pdev->dev;
 361         int ret;
 362
 363         freq = xcvr->soc_data->spdif_only ? freq / 5 : freq;
 364         clk_disable_unprepare(xcvr->phy_clk);
 365         ret = clk_set_rate(xcvr->phy_clk, freq);
 366         if (ret < 0) {
 367                 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret);
 368                 return ret;
 369         }
 370         ret = clk_prepare_enable(xcvr->phy_clk);
 371         if (ret) {
 372                 dev_err(dev, "failed to start PHY clock: %d\n", ret);
 373                 return ret;
 374         }
 375
 376         if (xcvr->soc_data->spdif_only)
 377                 return 0;
 378         /* Release AI interface from reset */
 379         ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
 380                            FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
 381         if (ret < 0) {
 382                 dev_err(dev, "Error while setting IER0: %d\n", ret);
 383                 return ret;
 384         }
 385
 386         if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
 387                 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
 388                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
 389                                   FSL_XCVR_PHY_CTRL_TSDIFF_OE |
 390                                   FSL_XCVR_PHY_CTRL_PHY_EN, 1);
 391                 /* PHY: CTRL2_SET: EARC_TX_MODE */
 392                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
 393                                   FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
 394         } else { /* SPDIF mode */
 395                 /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */
 396                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
 397                                   FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS |
 398                                   FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
 399         }
 400
 401         dev_dbg(dev, "PLL Fexp: %u\n", freq);
 402
 403         return 0;
 404 }
 405
 406 #define FSL_XCVR_SPDIF_RX_FREQ  175000000
 407 static int fsl_xcvr_prepare(struct snd_pcm_substream *substream,
 408                             struct snd_soc_dai *dai)
 409 {
 410         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 411         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 412         u32 m_ctl = 0, v_ctl = 0;
 413         u32 r = substream->runtime->rate, ch = substream->runtime->channels;
 414         u32 fout = 32 * r * ch * 10;
 415         int ret = 0;
 416
 417         switch (xcvr->mode) {
 418         case FSL_XCVR_MODE_SPDIF:
 419                 if (xcvr->soc_data->spdif_only && tx) {
 420                         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
 421                                                  FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM,
 422                                                  FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM);
 423                         if (ret < 0) {
 424                                 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret);
 425                                 return ret;
 426                         }
 427                 }
 428                 fallthrough;
 429         case FSL_XCVR_MODE_ARC:
 430                 if (tx) {
 431                         ret = fsl_xcvr_en_aud_pll(xcvr, fout);
 432                         if (ret < 0) {
 433                                 dev_err(dai->dev, "Failed to set TX freq %u: %d\n",
 434                                         fout, ret);
 435                                 return ret;
 436                         }
 437
 438                         ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
 439                                            FSL_XCVR_TX_DPTH_CTRL_FRM_FMT);
 440                         if (ret < 0) {
 441                                 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret);
 442                                 return ret;
 443                         }
 444
 445                         /**
 446                          * set SPDIF MODE - this flag is used to gate
 447                          * SPDIF output, useless for SPDIF RX
 448                          */
 449                         m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
 450                         v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
 451                 } else {
 452                         /**
 453                          * Clear RX FIFO, flip RX FIFO bits,
 454                          * disable eARC related HW mode detects
 455                          */
 456                         ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
 457                                            FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
 458                                            FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO |
 459                                            FSL_XCVR_RX_DPTH_CTRL_COMP |
 460                                            FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
 461                         if (ret < 0) {
 462                                 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
 463                                 return ret;
 464                         }
 465
 466                         ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx);
 467                         if (ret < 0) {
 468                                 dev_err(dai->dev, "Failed to set RX freq %u: %d\n",
 469                                         FSL_XCVR_SPDIF_RX_FREQ, ret);
 470                                 return ret;
 471                         }
 472                 }
 473                 break;
 474         case FSL_XCVR_MODE_EARC:
 475                 if (!tx) {
 476                         /** Clear RX FIFO, flip RX FIFO bits */
 477                         ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
 478                                            FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
 479                                            FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO);
 480                         if (ret < 0) {
 481                                 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
 482                                 return ret;
 483                         }
 484
 485                         /** Enable eARC related HW mode detects */
 486                         ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR,
 487                                            FSL_XCVR_RX_DPTH_CTRL_COMP |
 488                                            FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
 489                         if (ret < 0) {
 490                                 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret);
 491                                 return ret;
 492                         }
 493                 }
 494
 495                 /* clear CMDC RESET */
 496                 m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
 497                 /* set TX_RX_MODE */
 498                 m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE;
 499                 v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0);
 500                 break;
 501         }
 502
 503         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
 504                                  FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL);
 505         if (ret < 0) {
 506                 dev_err(dai->dev, "Error while setting IER0: %d\n", ret);
 507                 return ret;
 508         }
 509
 510         /* set DPATH RESET */
 511         m_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
 512         v_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
 513         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl);
 514         if (ret < 0) {
 515                 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret);
 516                 return ret;
 517         }
 518
 519         return 0;
 520 }
 521
 522 static int fsl_xcvr_constr(const struct snd_pcm_substream *substream,
 523                            const struct snd_pcm_hw_constraint_list *channels,
 524                            const struct snd_pcm_hw_constraint_list *rates)
 525 {
 526         struct snd_pcm_runtime *rt = substream->runtime;
 527         int ret;
 528
 529         ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
 530                                          channels);
 531         if (ret < 0)
 532                 return ret;
 533
 534         ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE,
 535                                          rates);
 536         if (ret < 0)
 537                 return ret;
 538
 539         return 0;
 540 }
 541
 542 static int fsl_xcvr_startup(struct snd_pcm_substream *substream,
 543                             struct snd_soc_dai *dai)
 544 {
 545         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 546         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 547         int ret = 0;
 548
 549         if (xcvr->streams & BIT(substream->stream)) {
 550                 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R");
 551                 return -EBUSY;
 552         }
 553
 554         /*
 555          * EDMA controller needs period size to be a multiple of
 556          * tx/rx maxburst
 557          */
 558         if (xcvr->soc_data->use_edma)
 559                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 560                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 561                                            tx ? xcvr->dma_prms_tx.maxburst :
 562                                            xcvr->dma_prms_rx.maxburst);
 563
 564         switch (xcvr->mode) {
 565         case FSL_XCVR_MODE_SPDIF:
 566         case FSL_XCVR_MODE_ARC:
 567                 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
 568                                       &fsl_xcvr_spdif_rates_constr);
 569                 break;
 570         case FSL_XCVR_MODE_EARC:
 571                 ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr,
 572                                       &fsl_xcvr_earc_rates_constr);
 573                 break;
 574         }
 575         if (ret < 0)
 576                 return ret;
 577
 578         xcvr->streams |= BIT(substream->stream);
 579
 580         if (!xcvr->soc_data->spdif_only) {
 581                 struct snd_soc_card *card = dai->component->card;
 582
 583                 /* Disable XCVR controls if there is stream started */
 584                 down_read(&card->snd_card->controls_rwsem);
 585                 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false);
 586                 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false);
 587                 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false);
 588                 up_read(&card->snd_card->controls_rwsem);
 589         }
 590
 591         return 0;
 592 }
 593
 594 static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream,
 595                               struct snd_soc_dai *dai)
 596 {
 597         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 598         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 599         u32 mask = 0, val = 0;
 600         int ret;
 601
 602         xcvr->streams &= ~BIT(substream->stream);
 603
 604         /* Enable XCVR controls if there is no stream started */
 605         if (!xcvr->streams) {
 606                 if (!xcvr->soc_data->spdif_only) {
 607                         struct snd_soc_card *card = dai->component->card;
 608
 609                         down_read(&card->snd_card->controls_rwsem);
 610                         fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true);
 611                         fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
 612                                                 (xcvr->mode == FSL_XCVR_MODE_ARC));
 613                         fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
 614                                                 (xcvr->mode == FSL_XCVR_MODE_EARC));
 615                         up_read(&card->snd_card->controls_rwsem);
 616                 }
 617                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
 618                                          FSL_XCVR_IRQ_EARC_ALL, 0);
 619                 if (ret < 0) {
 620                         dev_err(dai->dev, "Failed to set IER0: %d\n", ret);
 621                         return;
 622                 }
 623
 624                 /* clear SPDIF MODE */
 625                 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
 626                         mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
 627         }
 628
 629         if (xcvr->mode == FSL_XCVR_MODE_EARC) {
 630                 /* set CMDC RESET */
 631                 mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
 632                 val  |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
 633         }
 634
 635         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
 636         if (ret < 0) {
 637                 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret);
 638                 return;
 639         }
 640 }
 641
 642 static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
 643                             struct snd_soc_dai *dai)
 644 {
 645         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 646         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 647         int ret;
 648
 649         switch (cmd) {
 650         case SNDRV_PCM_TRIGGER_START:
 651         case SNDRV_PCM_TRIGGER_RESUME:
 652         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 653                 if (tx) {
 654                         switch (xcvr->mode) {
 655                         case FSL_XCVR_MODE_EARC:
 656                                 /* set isr_cmdc_tx_en, w1c */
 657                                 ret = regmap_write(xcvr->regmap,
 658                                                    FSL_XCVR_ISR_SET,
 659                                                    FSL_XCVR_ISR_CMDC_TX_EN);
 660                                 if (ret < 0) {
 661                                         dev_err(dai->dev, "err updating isr %d\n", ret);
 662                                         return ret;
 663                                 }
 664                                 fallthrough;
 665                         case FSL_XCVR_MODE_SPDIF:
 666                                 ret = regmap_write(xcvr->regmap,
 667                                          FSL_XCVR_TX_DPTH_CTRL_SET,
 668                                          FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
 669                                 if (ret < 0) {
 670                                         dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret);
 671                                         return ret;
 672                                 }
 673                                 break;
 674                         }
 675                 }
 676
 677                 /* enable DMA RD/WR */
 678                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
 679                                          FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0);
 680                 if (ret < 0) {
 681                         dev_err(dai->dev, "Failed to enable DMA: %d\n", ret);
 682                         return ret;
 683                 }
 684
 685                 /* clear DPATH RESET */
 686                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
 687                                          FSL_XCVR_EXT_CTRL_DPTH_RESET(tx),
 688                                          0);
 689                 if (ret < 0) {
 690                         dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret);
 691                         return ret;
 692                 }
 693
 694                 break;
 695         case SNDRV_PCM_TRIGGER_STOP:
 696         case SNDRV_PCM_TRIGGER_SUSPEND:
 697         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 698                 /* disable DMA RD/WR */
 699                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
 700                                          FSL_XCVR_EXT_CTRL_DMA_DIS(tx),
 701                                          FSL_XCVR_EXT_CTRL_DMA_DIS(tx));
 702                 if (ret < 0) {
 703                         dev_err(dai->dev, "Failed to disable DMA: %d\n", ret);
 704                         return ret;
 705                 }
 706
 707                 if (tx) {
 708                         switch (xcvr->mode) {
 709                         case FSL_XCVR_MODE_SPDIF:
 710                                 ret = regmap_write(xcvr->regmap,
 711                                          FSL_XCVR_TX_DPTH_CTRL_CLR,
 712                                          FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
 713                                 if (ret < 0) {
 714                                         dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
 715                                         return ret;
 716                                 }
 717                                 if (xcvr->soc_data->spdif_only)
 718                                         break;
 719                                 else
 720                                         fallthrough;
 721                         case FSL_XCVR_MODE_EARC:
 722                                 /* clear ISR_CMDC_TX_EN, W1C */
 723                                 ret = regmap_write(xcvr->regmap,
 724                                                    FSL_XCVR_ISR_CLR,
 725                                                    FSL_XCVR_ISR_CMDC_TX_EN);
 726                                 if (ret < 0) {
 727                                         dev_err(dai->dev,
 728                                                 "Err updating ISR %d\n", ret);
 729                                         return ret;
 730                                 }
 731                                 break;
 732                         }
 733                 }
 734                 break;
 735         default:
 736                 return -EINVAL;
 737         }
 738
 739         return 0;
 740 }
 741
 742 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
 743 {
 744         struct device *dev = &xcvr->pdev->dev;
 745         const struct firmware *fw;
 746         int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET;
 747         u32 mask, val;
 748
 749         ret = reject_firmware(&fw, xcvr->soc_data->fw_name, dev);
 750         if (ret) {
 751                 dev_err(dev, "failed to request firmware.\n");
 752                 return ret;
 753         }
 754
 755         rem = fw->size;
 756
 757         /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */
 758         if (rem > 16384) {
 759                 dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem);
 760                 release_firmware(fw);
 761                 return -ENOMEM;
 762         }
 763
 764         for (page = 0; page < 10; page++) {
 765                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
 766                                          FSL_XCVR_EXT_CTRL_PAGE_MASK,
 767                                          FSL_XCVR_EXT_CTRL_PAGE(page));
 768                 if (ret < 0) {
 769                         dev_err(dev, "FW: failed to set page %d, err=%d\n",
 770                                 page, ret);
 771                         goto err_firmware;
 772                 }
 773
 774                 off = page * size;
 775                 out = min(rem, size);
 776                 /* IPG clock is assumed to be running, otherwise it will hang */
 777                 if (out > 0) {
 778                         /* write firmware into code memory */
 779                         memcpy_toio(xcvr->ram_addr, fw->data + off, out);
 780                         rem -= out;
 781                         if (rem == 0) {
 782                                 /* last part of firmware written */
 783                                 /* clean remaining part of code memory page */
 784                                 memset_io(xcvr->ram_addr + out, 0, size - out);
 785                         }
 786                 } else {
 787                         /* clean current page, including data memory */
 788                         memset_io(xcvr->ram_addr, 0, size);
 789                 }
 790         }
 791
 792 err_firmware:
 793         release_firmware(fw);
 794         if (ret < 0)
 795                 return ret;
 796
 797         /* configure watermarks */
 798         mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK;
 799         val  = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX);
 800         val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX);
 801         /* disable DMA RD/WR */
 802         mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
 803         val  |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
 804         /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
 805         mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK;
 806         val  |= FSL_XCVR_EXT_CTRL_PAGE(8);
 807
 808         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
 809         if (ret < 0) {
 810                 dev_err(dev, "Failed to set watermarks: %d\n", ret);
 811                 return ret;
 812         }
 813
 814         /* Store Capabilities Data Structure into Data RAM */
 815         memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds,
 816                     FSL_XCVR_CAPDS_SIZE);
 817         return 0;
 818 }
 819
 820 static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol,
 821                                      struct snd_ctl_elem_info *uinfo)
 822 {
 823         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 824         uinfo->count = 1;
 825
 826         return 0;
 827 }
 828
 829 static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol,
 830                                            struct snd_ctl_elem_info *uinfo)
 831 {
 832         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 833         uinfo->count = sizeof_field(struct snd_aes_iec958, status);
 834
 835         return 0;
 836 }
 837
 838 static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol,
 839                               struct snd_ctl_elem_value *ucontrol)
 840 {
 841         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 842         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 843
 844         memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24);
 845
 846         return 0;
 847 }
 848
 849 static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol,
 850                               struct snd_ctl_elem_value *ucontrol)
 851 {
 852         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 853         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 854
 855         memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24);
 856
 857         return 0;
 858 }
 859
 860 static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol,
 861                               struct snd_ctl_elem_value *ucontrol)
 862 {
 863         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 864         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 865
 866         memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24);
 867
 868         return 0;
 869 }
 870
 871 static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = {
 872         /* Channel status controller */
 873         {
 874                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 875                 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
 876                 .access = SNDRV_CTL_ELEM_ACCESS_READ,
 877                 .info = fsl_xcvr_type_iec958_info,
 878                 .get = fsl_xcvr_rx_cs_get,
 879         },
 880         /* Capture channel status, bytes */
 881         {
 882                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 883                 .name = "Capture Channel Status",
 884                 .access = SNDRV_CTL_ELEM_ACCESS_READ,
 885                 .info = fsl_xcvr_type_iec958_bytes_info,
 886                 .get = fsl_xcvr_rx_cs_get,
 887         },
 888 };
 889
 890 static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = {
 891         /* Channel status controller */
 892         {
 893                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 894                 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
 895                 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
 896                 .info = fsl_xcvr_type_iec958_info,
 897                 .get = fsl_xcvr_tx_cs_get,
 898                 .put = fsl_xcvr_tx_cs_put,
 899         },
 900         /* Playback channel status, bytes */
 901         {
 902                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 903                 .name = "Playback Channel Status",
 904                 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
 905                 .info = fsl_xcvr_type_iec958_bytes_info,
 906                 .get = fsl_xcvr_tx_cs_get,
 907                 .put = fsl_xcvr_tx_cs_put,
 908         },
 909 };
 910
 911 static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai)
 912 {
 913         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 914
 915         snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx);
 916
 917         if (xcvr->soc_data->spdif_only)
 918                 xcvr->mode = FSL_XCVR_MODE_SPDIF;
 919         else {
 920                 snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1);
 921                 snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1);
 922                 snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1);
 923         }
 924         snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls,
 925                                  ARRAY_SIZE(fsl_xcvr_tx_ctls));
 926         snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls,
 927                                  ARRAY_SIZE(fsl_xcvr_rx_ctls));
 928         return 0;
 929 }
 930
 931 static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = {
 932         .probe          = fsl_xcvr_dai_probe,
 933         .prepare        = fsl_xcvr_prepare,
 934         .startup        = fsl_xcvr_startup,
 935         .shutdown       = fsl_xcvr_shutdown,
 936         .trigger        = fsl_xcvr_trigger,
 937 };
 938
 939 static struct snd_soc_dai_driver fsl_xcvr_dai = {
 940         .ops = &fsl_xcvr_dai_ops,
 941         .playback = {
 942                 .stream_name = "CPU-Playback",
 943                 .channels_min = 1,
 944                 .channels_max = 32,
 945                 .rate_min = 32000,
 946                 .rate_max = 1536000,
 947                 .rates = SNDRV_PCM_RATE_KNOT,
 948                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
 949         },
 950         .capture = {
 951                 .stream_name = "CPU-Capture",
 952                 .channels_min = 1,
 953                 .channels_max = 32,
 954                 .rate_min = 32000,
 955                 .rate_max = 1536000,
 956                 .rates = SNDRV_PCM_RATE_KNOT,
 957                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
 958         },
 959 };
 960
 961 static const struct snd_soc_component_driver fsl_xcvr_comp = {
 962         .name                   = "fsl-xcvr-dai",
 963         .legacy_dai_naming      = 1,
 964 };
 965
 966 static const struct reg_default fsl_xcvr_reg_defaults[] = {
 967         { FSL_XCVR_VERSION,     0x00000000 },
 968         { FSL_XCVR_EXT_CTRL,    0xF8204040 },
 969         { FSL_XCVR_EXT_STATUS,  0x00000000 },
 970         { FSL_XCVR_EXT_IER0,    0x00000000 },
 971         { FSL_XCVR_EXT_IER1,    0x00000000 },
 972         { FSL_XCVR_EXT_ISR,     0x00000000 },
 973         { FSL_XCVR_EXT_ISR_SET, 0x00000000 },
 974         { FSL_XCVR_EXT_ISR_CLR, 0x00000000 },
 975         { FSL_XCVR_EXT_ISR_TOG, 0x00000000 },
 976         { FSL_XCVR_IER,         0x00000000 },
 977         { FSL_XCVR_ISR,         0x00000000 },
 978         { FSL_XCVR_ISR_SET,     0x00000000 },
 979         { FSL_XCVR_ISR_CLR,     0x00000000 },
 980         { FSL_XCVR_ISR_TOG,     0x00000000 },
 981         { FSL_XCVR_CLK_CTRL,    0x0000018F },
 982         { FSL_XCVR_RX_DPTH_CTRL,        0x00040CC1 },
 983         { FSL_XCVR_RX_DPTH_CTRL_SET,    0x00040CC1 },
 984         { FSL_XCVR_RX_DPTH_CTRL_CLR,    0x00040CC1 },
 985         { FSL_XCVR_RX_DPTH_CTRL_TOG,    0x00040CC1 },
 986         { FSL_XCVR_RX_DPTH_CNTR_CTRL,   0x00000000 },
 987         { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 },
 988         { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
 989         { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
 990         { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 },
 991         { FSL_XCVR_RX_DPTH_BCR,  0x00000000 },
 992         { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 },
 993         { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 },
 994         { FSL_XCVR_TX_DPTH_CTRL,        0x00000000 },
 995         { FSL_XCVR_TX_DPTH_CTRL_SET,    0x00000000 },
 996         { FSL_XCVR_TX_DPTH_CTRL_CLR,    0x00000000 },
 997         { FSL_XCVR_TX_DPTH_CTRL_TOG,    0x00000000 },
 998         { FSL_XCVR_TX_CS_DATA_0,        0x00000000 },
 999         { FSL_XCVR_TX_CS_DATA_1,        0x00000000 },
1000         { FSL_XCVR_TX_CS_DATA_2,        0x00000000 },
1001         { FSL_XCVR_TX_CS_DATA_3,        0x00000000 },
1002         { FSL_XCVR_TX_CS_DATA_4,        0x00000000 },
1003         { FSL_XCVR_TX_CS_DATA_5,        0x00000000 },
1004         { FSL_XCVR_TX_DPTH_CNTR_CTRL,   0x00000000 },
1005         { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 },
1006         { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
1007         { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
1008         { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 },
1009         { FSL_XCVR_TX_DPTH_BCR,  0x00000000 },
1010         { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 },
1011         { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 },
1012         { FSL_XCVR_DEBUG_REG_0,         0x00000000 },
1013         { FSL_XCVR_DEBUG_REG_1,         0x00000000 },
1014 };
1015
1016 static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
1017 {
1018         struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1019
1020         if (xcvr->soc_data->spdif_only)
1021                 if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) ||
1022                     reg > FSL_XCVR_TX_DPTH_BCRR)
1023                         return false;
1024         switch (reg) {
1025         case FSL_XCVR_VERSION:
1026         case FSL_XCVR_EXT_CTRL:
1027         case FSL_XCVR_EXT_STATUS:
1028         case FSL_XCVR_EXT_IER0:
1029         case FSL_XCVR_EXT_IER1:
1030         case FSL_XCVR_EXT_ISR:
1031         case FSL_XCVR_EXT_ISR_SET:
1032         case FSL_XCVR_EXT_ISR_CLR:
1033         case FSL_XCVR_EXT_ISR_TOG:
1034         case FSL_XCVR_IER:
1035         case FSL_XCVR_ISR:
1036         case FSL_XCVR_ISR_SET:
1037         case FSL_XCVR_ISR_CLR:
1038         case FSL_XCVR_ISR_TOG:
1039         case FSL_XCVR_PHY_AI_CTRL:
1040         case FSL_XCVR_PHY_AI_CTRL_SET:
1041         case FSL_XCVR_PHY_AI_CTRL_CLR:
1042         case FSL_XCVR_PHY_AI_CTRL_TOG:
1043         case FSL_XCVR_PHY_AI_RDATA:
1044         case FSL_XCVR_CLK_CTRL:
1045         case FSL_XCVR_RX_DPTH_CTRL:
1046         case FSL_XCVR_RX_DPTH_CTRL_SET:
1047         case FSL_XCVR_RX_DPTH_CTRL_CLR:
1048         case FSL_XCVR_RX_DPTH_CTRL_TOG:
1049         case FSL_XCVR_RX_CS_DATA_0:
1050         case FSL_XCVR_RX_CS_DATA_1:
1051         case FSL_XCVR_RX_CS_DATA_2:
1052         case FSL_XCVR_RX_CS_DATA_3:
1053         case FSL_XCVR_RX_CS_DATA_4:
1054         case FSL_XCVR_RX_CS_DATA_5:
1055         case FSL_XCVR_RX_DPTH_CNTR_CTRL:
1056         case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
1057         case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
1058         case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
1059         case FSL_XCVR_RX_DPTH_TSCR:
1060         case FSL_XCVR_RX_DPTH_BCR:
1061         case FSL_XCVR_RX_DPTH_BCTR:
1062         case FSL_XCVR_RX_DPTH_BCRR:
1063         case FSL_XCVR_TX_DPTH_CTRL:
1064         case FSL_XCVR_TX_DPTH_CTRL_SET:
1065         case FSL_XCVR_TX_DPTH_CTRL_CLR:
1066         case FSL_XCVR_TX_DPTH_CTRL_TOG:
1067         case FSL_XCVR_TX_CS_DATA_0:
1068         case FSL_XCVR_TX_CS_DATA_1:
1069         case FSL_XCVR_TX_CS_DATA_2:
1070         case FSL_XCVR_TX_CS_DATA_3:
1071         case FSL_XCVR_TX_CS_DATA_4:
1072         case FSL_XCVR_TX_CS_DATA_5:
1073         case FSL_XCVR_TX_DPTH_CNTR_CTRL:
1074         case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
1075         case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
1076         case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
1077         case FSL_XCVR_TX_DPTH_TSCR:
1078         case FSL_XCVR_TX_DPTH_BCR:
1079         case FSL_XCVR_TX_DPTH_BCTR:
1080         case FSL_XCVR_TX_DPTH_BCRR:
1081         case FSL_XCVR_DEBUG_REG_0:
1082         case FSL_XCVR_DEBUG_REG_1:
1083                 return true;
1084         default:
1085                 return false;
1086         }
1087 }
1088
1089 static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
1090 {
1091         struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1092
1093         if (xcvr->soc_data->spdif_only)
1094                 if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA)
1095                         return false;
1096         switch (reg) {
1097         case FSL_XCVR_EXT_CTRL:
1098         case FSL_XCVR_EXT_IER0:
1099         case FSL_XCVR_EXT_IER1:
1100         case FSL_XCVR_EXT_ISR:
1101         case FSL_XCVR_EXT_ISR_SET:
1102         case FSL_XCVR_EXT_ISR_CLR:
1103         case FSL_XCVR_EXT_ISR_TOG:
1104         case FSL_XCVR_IER:
1105         case FSL_XCVR_ISR_SET:
1106         case FSL_XCVR_ISR_CLR:
1107         case FSL_XCVR_ISR_TOG:
1108         case FSL_XCVR_PHY_AI_CTRL:
1109         case FSL_XCVR_PHY_AI_CTRL_SET:
1110         case FSL_XCVR_PHY_AI_CTRL_CLR:
1111         case FSL_XCVR_PHY_AI_CTRL_TOG:
1112         case FSL_XCVR_PHY_AI_WDATA:
1113         case FSL_XCVR_CLK_CTRL:
1114         case FSL_XCVR_RX_DPTH_CTRL:
1115         case FSL_XCVR_RX_DPTH_CTRL_SET:
1116         case FSL_XCVR_RX_DPTH_CTRL_CLR:
1117         case FSL_XCVR_RX_DPTH_CTRL_TOG:
1118         case FSL_XCVR_RX_DPTH_CNTR_CTRL:
1119         case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
1120         case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
1121         case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
1122         case FSL_XCVR_TX_DPTH_CTRL_SET:
1123         case FSL_XCVR_TX_DPTH_CTRL_CLR:
1124         case FSL_XCVR_TX_DPTH_CTRL_TOG:
1125         case FSL_XCVR_TX_CS_DATA_0:
1126         case FSL_XCVR_TX_CS_DATA_1:
1127         case FSL_XCVR_TX_CS_DATA_2:
1128         case FSL_XCVR_TX_CS_DATA_3:
1129         case FSL_XCVR_TX_CS_DATA_4:
1130         case FSL_XCVR_TX_CS_DATA_5:
1131         case FSL_XCVR_TX_DPTH_CNTR_CTRL:
1132         case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
1133         case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
1134         case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
1135                 return true;
1136         default:
1137                 return false;
1138         }
1139 }
1140
1141 static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg)
1142 {
1143         return fsl_xcvr_readable_reg(dev, reg);
1144 }
1145
1146 static const struct regmap_config fsl_xcvr_regmap_cfg = {
1147         .reg_bits = 32,
1148         .reg_stride = 4,
1149         .val_bits = 32,
1150         .max_register = FSL_XCVR_MAX_REG,
1151         .reg_defaults = fsl_xcvr_reg_defaults,
1152         .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults),
1153         .readable_reg = fsl_xcvr_readable_reg,
1154         .volatile_reg = fsl_xcvr_volatile_reg,
1155         .writeable_reg = fsl_xcvr_writeable_reg,
1156         .cache_type = REGCACHE_FLAT,
1157 };
1158
1159 static irqreturn_t irq0_isr(int irq, void *devid)
1160 {
1161         struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
1162         struct device *dev = &xcvr->pdev->dev;
1163         struct regmap *regmap = xcvr->regmap;
1164         void __iomem *reg_ctrl, *reg_buff;
1165         u32 isr, isr_clr = 0, val, i;
1166
1167         regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr);
1168
1169         if (isr & FSL_XCVR_IRQ_NEW_CS) {
1170                 dev_dbg(dev, "Received new CS block\n");
1171                 isr_clr |= FSL_XCVR_IRQ_NEW_CS;
1172                 if (!xcvr->soc_data->spdif_only) {
1173                         /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
1174                         regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1175                                            FSL_XCVR_EXT_CTRL_PAGE_MASK,
1176                                            FSL_XCVR_EXT_CTRL_PAGE(8));
1177
1178                         /* Find updated CS buffer */
1179                         reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0;
1180                         reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0;
1181                         memcpy_fromio(&val, reg_ctrl, sizeof(val));
1182                         if (!val) {
1183                                 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1;
1184                                 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1;
1185                                 memcpy_fromio(&val, reg_ctrl, sizeof(val));
1186                         }
1187
1188                         if (val) {
1189                                 /* copy CS buffer */
1190                                 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff,
1191                                               sizeof(xcvr->rx_iec958.status));
1192                                 for (i = 0; i < 6; i++) {
1193                                         val = *(u32 *)(xcvr->rx_iec958.status + i*4);
1194                                         *(u32 *)(xcvr->rx_iec958.status + i*4) =
1195                                                 bitrev32(val);
1196                                 }
1197                                 /* clear CS control register */
1198                                 memset_io(reg_ctrl, 0, sizeof(val));
1199                         }
1200                 }
1201         }
1202         if (isr & FSL_XCVR_IRQ_NEW_UD) {
1203                 dev_dbg(dev, "Received new UD block\n");
1204                 isr_clr |= FSL_XCVR_IRQ_NEW_UD;
1205         }
1206         if (isr & FSL_XCVR_IRQ_MUTE) {
1207                 dev_dbg(dev, "HW mute bit detected\n");
1208                 isr_clr |= FSL_XCVR_IRQ_MUTE;
1209         }
1210         if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) {
1211                 dev_dbg(dev, "RX/TX FIFO full/empty\n");
1212                 isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR;
1213         }
1214         if (isr & FSL_XCVR_IRQ_ARC_MODE) {
1215                 dev_dbg(dev, "CMDC SM falls out of eARC mode\n");
1216                 isr_clr |= FSL_XCVR_IRQ_ARC_MODE;
1217         }
1218         if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) {
1219                 dev_dbg(dev, "DMA read request\n");
1220                 isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ;
1221         }
1222         if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) {
1223                 dev_dbg(dev, "DMA write request\n");
1224                 isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ;
1225         }
1226
1227         if (isr_clr) {
1228                 regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr);
1229                 return IRQ_HANDLED;
1230         }
1231
1232         return IRQ_NONE;
1233 }
1234
1235 static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = {
1236         .fw_name = "/*(DEBLOBBED)*/",
1237 };
1238
1239 static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = {
1240         .spdif_only = true,
1241         .use_edma = true,
1242 };
1243
1244 static const struct of_device_id fsl_xcvr_dt_ids[] = {
1245         { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
1246         { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
1247         { /* sentinel */ }
1248 };
1249 MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids);
1250
1251 static int fsl_xcvr_probe(struct platform_device *pdev)
1252 {
1253         struct device *dev = &pdev->dev;
1254         struct fsl_xcvr *xcvr;
1255         struct resource *rx_res, *tx_res;
1256         void __iomem *regs;
1257         int ret, irq;
1258
1259         xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL);
1260         if (!xcvr)
1261                 return -ENOMEM;
1262
1263         xcvr->pdev = pdev;
1264         xcvr->soc_data = of_device_get_match_data(&pdev->dev);
1265
1266         xcvr->ipg_clk = devm_clk_get(dev, "ipg");
1267         if (IS_ERR(xcvr->ipg_clk)) {
1268                 dev_err(dev, "failed to get ipg clock\n");
1269                 return PTR_ERR(xcvr->ipg_clk);
1270         }
1271
1272         xcvr->phy_clk = devm_clk_get(dev, "phy");
1273         if (IS_ERR(xcvr->phy_clk)) {
1274                 dev_err(dev, "failed to get phy clock\n");
1275                 return PTR_ERR(xcvr->phy_clk);
1276         }
1277
1278         xcvr->spba_clk = devm_clk_get(dev, "spba");
1279         if (IS_ERR(xcvr->spba_clk)) {
1280                 dev_err(dev, "failed to get spba clock\n");
1281                 return PTR_ERR(xcvr->spba_clk);
1282         }
1283
1284         xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg");
1285         if (IS_ERR(xcvr->pll_ipg_clk)) {
1286                 dev_err(dev, "failed to get pll_ipg clock\n");
1287                 return PTR_ERR(xcvr->pll_ipg_clk);
1288         }
1289
1290         xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram");
1291         if (IS_ERR(xcvr->ram_addr))
1292                 return PTR_ERR(xcvr->ram_addr);
1293
1294         regs = devm_platform_ioremap_resource_byname(pdev, "regs");
1295         if (IS_ERR(regs))
1296                 return PTR_ERR(regs);
1297
1298         xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs,
1299                                                  &fsl_xcvr_regmap_cfg);
1300         if (IS_ERR(xcvr->regmap)) {
1301                 dev_err(dev, "failed to init XCVR regmap: %ld\n",
1302                         PTR_ERR(xcvr->regmap));
1303                 return PTR_ERR(xcvr->regmap);
1304         }
1305
1306         xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
1307         if (IS_ERR(xcvr->reset)) {
1308                 dev_err(dev, "failed to get XCVR reset control\n");
1309                 return PTR_ERR(xcvr->reset);
1310         }
1311
1312         /* get IRQs */
1313         irq = platform_get_irq(pdev, 0);
1314         if (irq < 0)
1315                 return irq;
1316
1317         ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
1318         if (ret) {
1319                 dev_err(dev, "failed to claim IRQ0: %i\n", ret);
1320                 return ret;
1321         }
1322
1323         rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo");
1324         tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo");
1325         if (!rx_res || !tx_res) {
1326                 dev_err(dev, "could not find rxfifo or txfifo resource\n");
1327                 return -EINVAL;
1328         }
1329         xcvr->dma_prms_rx.chan_name = "rx";
1330         xcvr->dma_prms_tx.chan_name = "tx";
1331         xcvr->dma_prms_rx.addr = rx_res->start;
1332         xcvr->dma_prms_tx.addr = tx_res->start;
1333         xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX;
1334         xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX;
1335
1336         platform_set_drvdata(pdev, xcvr);
1337         pm_runtime_enable(dev);
1338         regcache_cache_only(xcvr->regmap, true);
1339
1340         /*
1341          * Register platform component before registering cpu dai for there
1342          * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1343          */
1344         ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1345         if (ret) {
1346                 pm_runtime_disable(dev);
1347                 dev_err(dev, "failed to pcm register\n");
1348                 return ret;
1349         }
1350
1351         ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp,
1352                                               &fsl_xcvr_dai, 1);
1353         if (ret) {
1354                 pm_runtime_disable(dev);
1355                 dev_err(dev, "failed to register component %s\n",
1356                         fsl_xcvr_comp.name);
1357         }
1358
1359         return ret;
1360 }
1361
1362 static void fsl_xcvr_remove(struct platform_device *pdev)
1363 {
1364         pm_runtime_disable(&pdev->dev);
1365 }
1366
1367 static __maybe_unused int fsl_xcvr_runtime_suspend(struct device *dev)
1368 {
1369         struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1370         int ret;
1371
1372         /*
1373          * Clear interrupts, when streams starts or resumes after
1374          * suspend, interrupts are enabled in prepare(), so no need
1375          * to enable interrupts in resume().
1376          */
1377         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
1378                                  FSL_XCVR_IRQ_EARC_ALL, 0);
1379         if (ret < 0)
1380                 dev_err(dev, "Failed to clear IER0: %d\n", ret);
1381
1382         if (!xcvr->soc_data->spdif_only) {
1383                 /* Assert M0+ reset */
1384                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1385                                         FSL_XCVR_EXT_CTRL_CORE_RESET,
1386                                         FSL_XCVR_EXT_CTRL_CORE_RESET);
1387                 if (ret < 0)
1388                         dev_err(dev, "Failed to assert M0+ core: %d\n", ret);
1389         }
1390
1391         regcache_cache_only(xcvr->regmap, true);
1392
1393         clk_disable_unprepare(xcvr->spba_clk);
1394         clk_disable_unprepare(xcvr->phy_clk);
1395         clk_disable_unprepare(xcvr->pll_ipg_clk);
1396         clk_disable_unprepare(xcvr->ipg_clk);
1397
1398         return 0;
1399 }
1400
1401 static __maybe_unused int fsl_xcvr_runtime_resume(struct device *dev)
1402 {
1403         struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1404         int ret;
1405
1406         ret = reset_control_assert(xcvr->reset);
1407         if (ret < 0) {
1408                 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret);
1409                 return ret;
1410         }
1411
1412         ret = clk_prepare_enable(xcvr->ipg_clk);
1413         if (ret) {
1414                 dev_err(dev, "failed to start IPG clock.\n");
1415                 return ret;
1416         }
1417
1418         ret = clk_prepare_enable(xcvr->pll_ipg_clk);
1419         if (ret) {
1420                 dev_err(dev, "failed to start PLL IPG clock.\n");
1421                 goto stop_ipg_clk;
1422         }
1423
1424         ret = clk_prepare_enable(xcvr->phy_clk);
1425         if (ret) {
1426                 dev_err(dev, "failed to start PHY clock: %d\n", ret);
1427                 goto stop_pll_ipg_clk;
1428         }
1429
1430         ret = clk_prepare_enable(xcvr->spba_clk);
1431         if (ret) {
1432                 dev_err(dev, "failed to start SPBA clock.\n");
1433                 goto stop_phy_clk;
1434         }
1435
1436         regcache_cache_only(xcvr->regmap, false);
1437         regcache_mark_dirty(xcvr->regmap);
1438         ret = regcache_sync(xcvr->regmap);
1439
1440         if (ret) {
1441                 dev_err(dev, "failed to sync regcache.\n");
1442                 goto stop_spba_clk;
1443         }
1444
1445         if (xcvr->soc_data->spdif_only)
1446                 return 0;
1447
1448         ret = reset_control_deassert(xcvr->reset);
1449         if (ret) {
1450                 dev_err(dev, "failed to deassert M0+ reset.\n");
1451                 goto stop_spba_clk;
1452         }
1453
1454         ret = fsl_xcvr_load_firmware(xcvr);
1455         if (ret) {
1456                 dev_err(dev, "failed to load firmware.\n");
1457                 goto stop_spba_clk;
1458         }
1459
1460         /* Release M0+ reset */
1461         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1462                                  FSL_XCVR_EXT_CTRL_CORE_RESET, 0);
1463         if (ret < 0) {
1464                 dev_err(dev, "M0+ core release failed: %d\n", ret);
1465                 goto stop_spba_clk;
1466         }
1467
1468         /* Let M0+ core complete firmware initialization */
1469         msleep(50);
1470
1471         return 0;
1472
1473 stop_spba_clk:
1474         clk_disable_unprepare(xcvr->spba_clk);
1475 stop_phy_clk:
1476         clk_disable_unprepare(xcvr->phy_clk);
1477 stop_pll_ipg_clk:
1478         clk_disable_unprepare(xcvr->pll_ipg_clk);
1479 stop_ipg_clk:
1480         clk_disable_unprepare(xcvr->ipg_clk);
1481
1482         return ret;
1483 }
1484
1485 static const struct dev_pm_ops fsl_xcvr_pm_ops = {
1486         SET_RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend,
1487                            fsl_xcvr_runtime_resume,
1488                            NULL)
1489         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1490                                 pm_runtime_force_resume)
1491 };
1492
1493 static struct platform_driver fsl_xcvr_driver = {
1494         .probe = fsl_xcvr_probe,
1495         .driver = {
1496                 .name = "fsl,imx8mp-audio-xcvr",
1497                 .pm = &fsl_xcvr_pm_ops,
1498                 .of_match_table = fsl_xcvr_dt_ids,
1499         },
1500         .remove_new = fsl_xcvr_remove,
1501 };
1502 module_platform_driver(fsl_xcvr_driver);
1503
1504 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>");
1505 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver");
1506 MODULE_LICENSE("GPL v2");