sound/soc/fsl/fsl_xcvr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright 2019 NXP
   3
   4 #include <linux/bitrev.h>
   5 #include <linux/clk.h>
   6 #include <linux/firmware.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/module.h>
   9 #include <linux/of_platform.h>
  10 #include <linux/pm_runtime.h>
  11 #include <linux/regmap.h>
  12 #include <linux/reset.h>
  13 #include <sound/dmaengine_pcm.h>
  14 #include <sound/pcm_iec958.h>
  15 #include <sound/pcm_params.h>
  16
  17 #include "fsl_xcvr.h"
  18 #include "imx-pcm.h"
  19
  20 #define FSL_XCVR_CAPDS_SIZE     256
  21
  22 struct fsl_xcvr_soc_data {
  23         const char *fw_name;
  24         bool spdif_only;
  25         bool use_edma;
  26 };
  27
  28 struct fsl_xcvr {
  29         const struct fsl_xcvr_soc_data *soc_data;
  30         struct platform_device *pdev;
  31         struct regmap *regmap;
  32         struct clk *ipg_clk;
  33         struct clk *pll_ipg_clk;
  34         struct clk *phy_clk;
  35         struct clk *spba_clk;
  36         struct reset_control *reset;
  37         u8 streams;
  38         u32 mode;
  39         u32 arc_mode;
  40         void __iomem *ram_addr;
  41         struct snd_dmaengine_dai_dma_data dma_prms_rx;
  42         struct snd_dmaengine_dai_dma_data dma_prms_tx;
  43         struct snd_aes_iec958 rx_iec958;
  44         struct snd_aes_iec958 tx_iec958;
  45         u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
  46 };
  47
  48 static const struct fsl_xcvr_pll_conf {
  49         u8 mfi;   /* min=0x18, max=0x38 */
  50         u32 mfn;  /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */
  51         u32 mfd;  /* unsigned int */
  52         u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */
  53 } fsl_xcvr_pll_cfg[] = {
  54         { .mfi = 54, .mfn = 1,  .mfd = 6,   .fout = 1300000000, }, /* 1.3 GHz */
  55         { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, },  /* 8000 Hz */
  56         { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, },  /* 11025 Hz */
  57         { .mfi = 29, .mfn = 1,  .mfd = 6,   .fout = 700000000, },  /* 700 MHz */
  58 };
  59
  60 /*
  61  * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
  62  * stream. Todo: to check how this case can be considered below
  63  */
  64 static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, };
  65 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = {
  66         .count = ARRAY_SIZE(fsl_xcvr_earc_channels),
  67         .list = fsl_xcvr_earc_channels,
  68 };
  69
  70 static const u32 fsl_xcvr_earc_rates[] = {
  71         32000, 44100, 48000, 64000, 88200, 96000,
  72         128000, 176400, 192000, 256000, 352800, 384000,
  73         512000, 705600, 768000, 1024000, 1411200, 1536000,
  74 };
  75 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = {
  76         .count = ARRAY_SIZE(fsl_xcvr_earc_rates),
  77         .list = fsl_xcvr_earc_rates,
  78 };
  79
  80 static const u32 fsl_xcvr_spdif_channels[] = { 2, };
  81 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = {
  82         .count = ARRAY_SIZE(fsl_xcvr_spdif_channels),
  83         .list = fsl_xcvr_spdif_channels,
  84 };
  85
  86 static const u32 fsl_xcvr_spdif_rates[] = {
  87         32000, 44100, 48000, 88200, 96000, 176400, 192000,
  88 };
  89 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = {
  90         .count = ARRAY_SIZE(fsl_xcvr_spdif_rates),
  91         .list = fsl_xcvr_spdif_rates,
  92 };
  93
  94 static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol,
  95                                  struct snd_ctl_elem_value *ucontrol)
  96 {
  97         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  98         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  99         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 100         unsigned int *item = ucontrol->value.enumerated.item;
 101
 102         xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]);
 103
 104         return 0;
 105 }
 106
 107 static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol,
 108                                  struct snd_ctl_elem_value *ucontrol)
 109 {
 110         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 111         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 112
 113         ucontrol->value.enumerated.item[0] = xcvr->arc_mode;
 114
 115         return 0;
 116 }
 117
 118 static const u32 fsl_xcvr_phy_arc_cfg[] = {
 119         FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN,
 120 };
 121
 122 static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", };
 123 static const struct soc_enum fsl_xcvr_arc_mode_enum =
 124         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode);
 125 static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl =
 126         SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum,
 127                      fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put);
 128
 129 /* Capabilities data structure, bytes */
 130 static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol,
 131                                           struct snd_ctl_elem_info *uinfo)
 132 {
 133         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 134         uinfo->count = FSL_XCVR_CAPDS_SIZE;
 135
 136         return 0;
 137 }
 138
 139 static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol,
 140                               struct snd_ctl_elem_value *ucontrol)
 141 {
 142         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 143         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 144
 145         memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE);
 146
 147         return 0;
 148 }
 149
 150 static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol,
 151                               struct snd_ctl_elem_value *ucontrol)
 152 {
 153         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 154         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 155
 156         memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE);
 157
 158         return 0;
 159 }
 160
 161 static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = {
 162         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 163         .name = "Capabilities Data Structure",
 164         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
 165         .info = fsl_xcvr_type_capds_bytes_info,
 166         .get = fsl_xcvr_capds_get,
 167         .put = fsl_xcvr_capds_put,
 168 };
 169
 170 static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name,
 171                                  bool active)
 172 {
 173         struct snd_soc_card *card = dai->component->card;
 174         struct snd_kcontrol *kctl;
 175         bool enabled;
 176
 177         kctl = snd_soc_card_get_kcontrol(card, name);
 178         if (kctl == NULL)
 179                 return -ENOENT;
 180
 181         enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0);
 182         if (active == enabled)
 183                 return 0; /* nothing to do */
 184
 185         if (active)
 186                 kctl->vd[0].access |=  SNDRV_CTL_ELEM_ACCESS_WRITE;
 187         else
 188                 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE;
 189
 190         snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
 191
 192         return 1;
 193 }
 194
 195 static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol,
 196                              struct snd_ctl_elem_value *ucontrol)
 197 {
 198         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 199         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 200         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 201         unsigned int *item = ucontrol->value.enumerated.item;
 202         struct snd_soc_card *card = dai->component->card;
 203         struct snd_soc_pcm_runtime *rtd;
 204
 205         xcvr->mode = snd_soc_enum_item_to_val(e, item[0]);
 206
 207         fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
 208                               (xcvr->mode == FSL_XCVR_MODE_ARC));
 209         fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
 210                               (xcvr->mode == FSL_XCVR_MODE_EARC));
 211         /* Allow playback for SPDIF only */
 212         rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
 213         rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count =
 214                 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0);
 215         return 0;
 216 }
 217
 218 static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol,
 219                              struct snd_ctl_elem_value *ucontrol)
 220 {
 221         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 222         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 223
 224         ucontrol->value.enumerated.item[0] = xcvr->mode;
 225
 226         return 0;
 227 }
 228
 229 static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", };
 230 static const struct soc_enum fsl_xcvr_mode_enum =
 231         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode);
 232 static struct snd_kcontrol_new fsl_xcvr_mode_kctl =
 233         SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum,
 234                      fsl_xcvr_mode_get, fsl_xcvr_mode_put);
 235
 236 /** phy: true => phy, false => pll */
 237 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
 238 {
 239         struct device *dev = &xcvr->pdev->dev;
 240         u32 val, idx, tidx;
 241         int ret;
 242
 243         idx  = BIT(phy ? 26 : 24);
 244         tidx = BIT(phy ? 27 : 25);
 245
 246         regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF);
 247         regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg);
 248         regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
 249         regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
 250
 251         ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
 252                                        (val & idx) == ((val & tidx) >> 1),
 253                                        10, 10000);
 254         if (ret)
 255                 dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n",
 256                         phy ? "PHY" : "PLL", reg, data);
 257         return ret;
 258 }
 259
 260 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
 261 {
 262         struct device *dev = &xcvr->pdev->dev;
 263         u32 i, div = 0, log2;
 264         int ret;
 265
 266         if (xcvr->soc_data->spdif_only)
 267                 return 0;
 268
 269         for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) {
 270                 if (fsl_xcvr_pll_cfg[i].fout % freq == 0) {
 271                         div = fsl_xcvr_pll_cfg[i].fout / freq;
 272                         break;
 273                 }
 274         }
 275
 276         if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg))
 277                 return -EINVAL;
 278
 279         log2 = ilog2(div);
 280
 281         /* Release AI interface from reset */
 282         ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
 283                            FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
 284         if (ret < 0) {
 285                 dev_err(dev, "Error while setting IER0: %d\n", ret);
 286                 return ret;
 287         }
 288
 289         /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */
 290         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET,
 291                           FSL_XCVR_PLL_BANDGAP_EN_VBG, 0);
 292
 293         /* PLL: CTRL0: DIV_INTEGER */
 294         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0);
 295         /* PLL: NUMERATOR: MFN */
 296         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0);
 297         /* PLL: DENOMINATOR: MFD */
 298         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0);
 299         /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */
 300         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
 301                           FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0);
 302         udelay(25);
 303         /* PLL: CTRL0: Clear Hold Ring Off */
 304         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR,
 305                           FSL_XCVR_PLL_CTRL0_HROFF, 0);
 306         udelay(100);
 307         if (tx) { /* TX is enabled for SPDIF only */
 308                 /* PLL: POSTDIV: PDIV0 */
 309                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
 310                                   FSL_XCVR_PLL_PDIVx(log2, 0), 0);
 311                 /* PLL: CTRL_SET: CLKMUX0_EN */
 312                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
 313                                   FSL_XCVR_PLL_CTRL0_CM0_EN, 0);
 314         } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
 315                 /* PLL: POSTDIV: PDIV1 */
 316                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
 317                                   FSL_XCVR_PLL_PDIVx(log2, 1), 0);
 318                 /* PLL: CTRL_SET: CLKMUX1_EN */
 319                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
 320                                   FSL_XCVR_PLL_CTRL0_CM1_EN, 0);
 321         } else { /* SPDIF / ARC RX */
 322                 /* PLL: POSTDIV: PDIV2 */
 323                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
 324                                   FSL_XCVR_PLL_PDIVx(log2, 2), 0);
 325                 /* PLL: CTRL_SET: CLKMUX2_EN */
 326                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
 327                                   FSL_XCVR_PLL_CTRL0_CM2_EN, 0);
 328         }
 329
 330         if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
 331                 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
 332                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
 333                                   FSL_XCVR_PHY_CTRL_TSDIFF_OE |
 334                                   FSL_XCVR_PHY_CTRL_PHY_EN, 1);
 335                 /* PHY: CTRL2_SET: EARC_TX_MODE */
 336                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
 337                                   FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
 338         } else if (!tx) { /* SPDIF / ARC RX mode */
 339                 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
 340                         /* PHY: CTRL_SET: SPDIF_EN */
 341                         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
 342                                           FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
 343                 else    /* PHY: CTRL_SET: ARC RX setup */
 344                         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
 345                                           FSL_XCVR_PHY_CTRL_PHY_EN |
 346                                           FSL_XCVR_PHY_CTRL_RX_CM_EN |
 347                                           fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1);
 348         }
 349
 350         dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n",
 351                 freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi,
 352                 fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2);
 353         return 0;
 354 }
 355
 356 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
 357 {
 358         struct device *dev = &xcvr->pdev->dev;
 359         int ret;
 360
 361         freq = xcvr->soc_data->spdif_only ? freq / 5 : freq;
 362         clk_disable_unprepare(xcvr->phy_clk);
 363         ret = clk_set_rate(xcvr->phy_clk, freq);
 364         if (ret < 0) {
 365                 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret);
 366                 return ret;
 367         }
 368         ret = clk_prepare_enable(xcvr->phy_clk);
 369         if (ret) {
 370                 dev_err(dev, "failed to start PHY clock: %d\n", ret);
 371                 return ret;
 372         }
 373
 374         if (xcvr->soc_data->spdif_only)
 375                 return 0;
 376         /* Release AI interface from reset */
 377         ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
 378                            FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
 379         if (ret < 0) {
 380                 dev_err(dev, "Error while setting IER0: %d\n", ret);
 381                 return ret;
 382         }
 383
 384         if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
 385                 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
 386                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
 387                                   FSL_XCVR_PHY_CTRL_TSDIFF_OE |
 388                                   FSL_XCVR_PHY_CTRL_PHY_EN, 1);
 389                 /* PHY: CTRL2_SET: EARC_TX_MODE */
 390                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
 391                                   FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
 392         } else { /* SPDIF mode */
 393                 /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */
 394                 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
 395                                   FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS |
 396                                   FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
 397         }
 398
 399         dev_dbg(dev, "PLL Fexp: %u\n", freq);
 400
 401         return 0;
 402 }
 403
 404 #define FSL_XCVR_SPDIF_RX_FREQ  175000000
 405 static int fsl_xcvr_prepare(struct snd_pcm_substream *substream,
 406                             struct snd_soc_dai *dai)
 407 {
 408         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 409         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 410         u32 m_ctl = 0, v_ctl = 0;
 411         u32 r = substream->runtime->rate, ch = substream->runtime->channels;
 412         u32 fout = 32 * r * ch * 10;
 413         int ret = 0;
 414
 415         switch (xcvr->mode) {
 416         case FSL_XCVR_MODE_SPDIF:
 417                 if (xcvr->soc_data->spdif_only && tx) {
 418                         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
 419                                                  FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM,
 420                                                  FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM);
 421                         if (ret < 0) {
 422                                 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret);
 423                                 return ret;
 424                         }
 425                 }
 426                 fallthrough;
 427         case FSL_XCVR_MODE_ARC:
 428                 if (tx) {
 429                         ret = fsl_xcvr_en_aud_pll(xcvr, fout);
 430                         if (ret < 0) {
 431                                 dev_err(dai->dev, "Failed to set TX freq %u: %d\n",
 432                                         fout, ret);
 433                                 return ret;
 434                         }
 435
 436                         ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
 437                                            FSL_XCVR_TX_DPTH_CTRL_FRM_FMT);
 438                         if (ret < 0) {
 439                                 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret);
 440                                 return ret;
 441                         }
 442
 443                         /**
 444                          * set SPDIF MODE - this flag is used to gate
 445                          * SPDIF output, useless for SPDIF RX
 446                          */
 447                         m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
 448                         v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
 449                 } else {
 450                         /**
 451                          * Clear RX FIFO, flip RX FIFO bits,
 452                          * disable eARC related HW mode detects
 453                          */
 454                         ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
 455                                            FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
 456                                            FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO |
 457                                            FSL_XCVR_RX_DPTH_CTRL_COMP |
 458                                            FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
 459                         if (ret < 0) {
 460                                 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
 461                                 return ret;
 462                         }
 463
 464                         ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx);
 465                         if (ret < 0) {
 466                                 dev_err(dai->dev, "Failed to set RX freq %u: %d\n",
 467                                         FSL_XCVR_SPDIF_RX_FREQ, ret);
 468                                 return ret;
 469                         }
 470                 }
 471                 break;
 472         case FSL_XCVR_MODE_EARC:
 473                 if (!tx) {
 474                         /** Clear RX FIFO, flip RX FIFO bits */
 475                         ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
 476                                            FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
 477                                            FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO);
 478                         if (ret < 0) {
 479                                 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
 480                                 return ret;
 481                         }
 482
 483                         /** Enable eARC related HW mode detects */
 484                         ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR,
 485                                            FSL_XCVR_RX_DPTH_CTRL_COMP |
 486                                            FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
 487                         if (ret < 0) {
 488                                 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret);
 489                                 return ret;
 490                         }
 491                 }
 492
 493                 /* clear CMDC RESET */
 494                 m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
 495                 /* set TX_RX_MODE */
 496                 m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE;
 497                 v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0);
 498                 break;
 499         }
 500
 501         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
 502                                  FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL);
 503         if (ret < 0) {
 504                 dev_err(dai->dev, "Error while setting IER0: %d\n", ret);
 505                 return ret;
 506         }
 507
 508         /* set DPATH RESET */
 509         m_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
 510         v_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
 511         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl);
 512         if (ret < 0) {
 513                 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret);
 514                 return ret;
 515         }
 516
 517         return 0;
 518 }
 519
 520 static int fsl_xcvr_constr(const struct snd_pcm_substream *substream,
 521                            const struct snd_pcm_hw_constraint_list *channels,
 522                            const struct snd_pcm_hw_constraint_list *rates)
 523 {
 524         struct snd_pcm_runtime *rt = substream->runtime;
 525         int ret;
 526
 527         ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
 528                                          channels);
 529         if (ret < 0)
 530                 return ret;
 531
 532         ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE,
 533                                          rates);
 534         if (ret < 0)
 535                 return ret;
 536
 537         return 0;
 538 }
 539
 540 static int fsl_xcvr_startup(struct snd_pcm_substream *substream,
 541                             struct snd_soc_dai *dai)
 542 {
 543         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 544         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 545         int ret = 0;
 546
 547         if (xcvr->streams & BIT(substream->stream)) {
 548                 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R");
 549                 return -EBUSY;
 550         }
 551
 552         /*
 553          * EDMA controller needs period size to be a multiple of
 554          * tx/rx maxburst
 555          */
 556         if (xcvr->soc_data->use_edma)
 557                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 558                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 559                                            tx ? xcvr->dma_prms_tx.maxburst :
 560                                            xcvr->dma_prms_rx.maxburst);
 561
 562         switch (xcvr->mode) {
 563         case FSL_XCVR_MODE_SPDIF:
 564         case FSL_XCVR_MODE_ARC:
 565                 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
 566                                       &fsl_xcvr_spdif_rates_constr);
 567                 break;
 568         case FSL_XCVR_MODE_EARC:
 569                 ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr,
 570                                       &fsl_xcvr_earc_rates_constr);
 571                 break;
 572         }
 573         if (ret < 0)
 574                 return ret;
 575
 576         xcvr->streams |= BIT(substream->stream);
 577
 578         if (!xcvr->soc_data->spdif_only) {
 579                 /* Disable XCVR controls if there is stream started */
 580                 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false);
 581                 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false);
 582                 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false);
 583         }
 584
 585         return 0;
 586 }
 587
 588 static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream,
 589                               struct snd_soc_dai *dai)
 590 {
 591         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 592         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 593         u32 mask = 0, val = 0;
 594         int ret;
 595
 596         xcvr->streams &= ~BIT(substream->stream);
 597
 598         /* Enable XCVR controls if there is no stream started */
 599         if (!xcvr->streams) {
 600                 if (!xcvr->soc_data->spdif_only) {
 601                         fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true);
 602                         fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
 603                                                 (xcvr->mode == FSL_XCVR_MODE_ARC));
 604                         fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
 605                                                 (xcvr->mode == FSL_XCVR_MODE_EARC));
 606                 }
 607                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
 608                                          FSL_XCVR_IRQ_EARC_ALL, 0);
 609                 if (ret < 0) {
 610                         dev_err(dai->dev, "Failed to set IER0: %d\n", ret);
 611                         return;
 612                 }
 613
 614                 /* clear SPDIF MODE */
 615                 if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
 616                         mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
 617         }
 618
 619         if (xcvr->mode == FSL_XCVR_MODE_EARC) {
 620                 /* set CMDC RESET */
 621                 mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
 622                 val  |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
 623         }
 624
 625         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
 626         if (ret < 0) {
 627                 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret);
 628                 return;
 629         }
 630 }
 631
 632 static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
 633                             struct snd_soc_dai *dai)
 634 {
 635         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 636         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 637         int ret;
 638
 639         switch (cmd) {
 640         case SNDRV_PCM_TRIGGER_START:
 641         case SNDRV_PCM_TRIGGER_RESUME:
 642         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 643                 if (tx) {
 644                         switch (xcvr->mode) {
 645                         case FSL_XCVR_MODE_EARC:
 646                                 /* set isr_cmdc_tx_en, w1c */
 647                                 ret = regmap_write(xcvr->regmap,
 648                                                    FSL_XCVR_ISR_SET,
 649                                                    FSL_XCVR_ISR_CMDC_TX_EN);
 650                                 if (ret < 0) {
 651                                         dev_err(dai->dev, "err updating isr %d\n", ret);
 652                                         return ret;
 653                                 }
 654                                 fallthrough;
 655                         case FSL_XCVR_MODE_SPDIF:
 656                                 ret = regmap_write(xcvr->regmap,
 657                                          FSL_XCVR_TX_DPTH_CTRL_SET,
 658                                          FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
 659                                 if (ret < 0) {
 660                                         dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret);
 661                                         return ret;
 662                                 }
 663                                 break;
 664                         }
 665                 }
 666
 667                 /* enable DMA RD/WR */
 668                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
 669                                          FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0);
 670                 if (ret < 0) {
 671                         dev_err(dai->dev, "Failed to enable DMA: %d\n", ret);
 672                         return ret;
 673                 }
 674
 675                 /* clear DPATH RESET */
 676                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
 677                                          FSL_XCVR_EXT_CTRL_DPTH_RESET(tx),
 678                                          0);
 679                 if (ret < 0) {
 680                         dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret);
 681                         return ret;
 682                 }
 683
 684                 break;
 685         case SNDRV_PCM_TRIGGER_STOP:
 686         case SNDRV_PCM_TRIGGER_SUSPEND:
 687         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 688                 /* disable DMA RD/WR */
 689                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
 690                                          FSL_XCVR_EXT_CTRL_DMA_DIS(tx),
 691                                          FSL_XCVR_EXT_CTRL_DMA_DIS(tx));
 692                 if (ret < 0) {
 693                         dev_err(dai->dev, "Failed to disable DMA: %d\n", ret);
 694                         return ret;
 695                 }
 696
 697                 if (tx) {
 698                         switch (xcvr->mode) {
 699                         case FSL_XCVR_MODE_SPDIF:
 700                                 ret = regmap_write(xcvr->regmap,
 701                                          FSL_XCVR_TX_DPTH_CTRL_CLR,
 702                                          FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
 703                                 if (ret < 0) {
 704                                         dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
 705                                         return ret;
 706                                 }
 707                                 if (xcvr->soc_data->spdif_only)
 708                                         break;
 709                                 else
 710                                         fallthrough;
 711                         case FSL_XCVR_MODE_EARC:
 712                                 /* clear ISR_CMDC_TX_EN, W1C */
 713                                 ret = regmap_write(xcvr->regmap,
 714                                                    FSL_XCVR_ISR_CLR,
 715                                                    FSL_XCVR_ISR_CMDC_TX_EN);
 716                                 if (ret < 0) {
 717                                         dev_err(dai->dev,
 718                                                 "Err updating ISR %d\n", ret);
 719                                         return ret;
 720                                 }
 721                                 break;
 722                         }
 723                 }
 724                 break;
 725         default:
 726                 return -EINVAL;
 727         }
 728
 729         return 0;
 730 }
 731
 732 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
 733 {
 734         struct device *dev = &xcvr->pdev->dev;
 735         const struct firmware *fw;
 736         int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET;
 737         u32 mask, val;
 738
 739         ret = reject_firmware(&fw, xcvr->soc_data->fw_name, dev);
 740         if (ret) {
 741                 dev_err(dev, "failed to request firmware.\n");
 742                 return ret;
 743         }
 744
 745         rem = fw->size;
 746
 747         /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */
 748         if (rem > 16384) {
 749                 dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem);
 750                 release_firmware(fw);
 751                 return -ENOMEM;
 752         }
 753
 754         for (page = 0; page < 10; page++) {
 755                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
 756                                          FSL_XCVR_EXT_CTRL_PAGE_MASK,
 757                                          FSL_XCVR_EXT_CTRL_PAGE(page));
 758                 if (ret < 0) {
 759                         dev_err(dev, "FW: failed to set page %d, err=%d\n",
 760                                 page, ret);
 761                         goto err_firmware;
 762                 }
 763
 764                 off = page * size;
 765                 out = min(rem, size);
 766                 /* IPG clock is assumed to be running, otherwise it will hang */
 767                 if (out > 0) {
 768                         /* write firmware into code memory */
 769                         memcpy_toio(xcvr->ram_addr, fw->data + off, out);
 770                         rem -= out;
 771                         if (rem == 0) {
 772                                 /* last part of firmware written */
 773                                 /* clean remaining part of code memory page */
 774                                 memset_io(xcvr->ram_addr + out, 0, size - out);
 775                         }
 776                 } else {
 777                         /* clean current page, including data memory */
 778                         memset_io(xcvr->ram_addr, 0, size);
 779                 }
 780         }
 781
 782 err_firmware:
 783         release_firmware(fw);
 784         if (ret < 0)
 785                 return ret;
 786
 787         /* configure watermarks */
 788         mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK;
 789         val  = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX);
 790         val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX);
 791         /* disable DMA RD/WR */
 792         mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
 793         val  |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
 794         /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
 795         mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK;
 796         val  |= FSL_XCVR_EXT_CTRL_PAGE(8);
 797
 798         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
 799         if (ret < 0) {
 800                 dev_err(dev, "Failed to set watermarks: %d\n", ret);
 801                 return ret;
 802         }
 803
 804         /* Store Capabilities Data Structure into Data RAM */
 805         memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds,
 806                     FSL_XCVR_CAPDS_SIZE);
 807         return 0;
 808 }
 809
 810 static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol,
 811                                      struct snd_ctl_elem_info *uinfo)
 812 {
 813         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 814         uinfo->count = 1;
 815
 816         return 0;
 817 }
 818
 819 static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol,
 820                                            struct snd_ctl_elem_info *uinfo)
 821 {
 822         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 823         uinfo->count = sizeof_field(struct snd_aes_iec958, status);
 824
 825         return 0;
 826 }
 827
 828 static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol,
 829                               struct snd_ctl_elem_value *ucontrol)
 830 {
 831         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 832         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 833
 834         memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24);
 835
 836         return 0;
 837 }
 838
 839 static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol,
 840                               struct snd_ctl_elem_value *ucontrol)
 841 {
 842         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 843         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 844
 845         memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24);
 846
 847         return 0;
 848 }
 849
 850 static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol,
 851                               struct snd_ctl_elem_value *ucontrol)
 852 {
 853         struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
 854         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 855
 856         memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24);
 857
 858         return 0;
 859 }
 860
 861 static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = {
 862         /* Channel status controller */
 863         {
 864                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 865                 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
 866                 .access = SNDRV_CTL_ELEM_ACCESS_READ,
 867                 .info = fsl_xcvr_type_iec958_info,
 868                 .get = fsl_xcvr_rx_cs_get,
 869         },
 870         /* Capture channel status, bytes */
 871         {
 872                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 873                 .name = "Capture Channel Status",
 874                 .access = SNDRV_CTL_ELEM_ACCESS_READ,
 875                 .info = fsl_xcvr_type_iec958_bytes_info,
 876                 .get = fsl_xcvr_rx_cs_get,
 877         },
 878 };
 879
 880 static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = {
 881         /* Channel status controller */
 882         {
 883                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 884                 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
 885                 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
 886                 .info = fsl_xcvr_type_iec958_info,
 887                 .get = fsl_xcvr_tx_cs_get,
 888                 .put = fsl_xcvr_tx_cs_put,
 889         },
 890         /* Playback channel status, bytes */
 891         {
 892                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 893                 .name = "Playback Channel Status",
 894                 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
 895                 .info = fsl_xcvr_type_iec958_bytes_info,
 896                 .get = fsl_xcvr_tx_cs_get,
 897                 .put = fsl_xcvr_tx_cs_put,
 898         },
 899 };
 900
 901 static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai)
 902 {
 903         struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
 904
 905         snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx);
 906
 907         if (xcvr->soc_data->spdif_only)
 908                 xcvr->mode = FSL_XCVR_MODE_SPDIF;
 909         else {
 910                 snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1);
 911                 snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1);
 912                 snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1);
 913         }
 914         snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls,
 915                                  ARRAY_SIZE(fsl_xcvr_tx_ctls));
 916         snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls,
 917                                  ARRAY_SIZE(fsl_xcvr_rx_ctls));
 918         return 0;
 919 }
 920
 921 static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = {
 922         .probe          = fsl_xcvr_dai_probe,
 923         .prepare        = fsl_xcvr_prepare,
 924         .startup        = fsl_xcvr_startup,
 925         .shutdown       = fsl_xcvr_shutdown,
 926         .trigger        = fsl_xcvr_trigger,
 927 };
 928
 929 static struct snd_soc_dai_driver fsl_xcvr_dai = {
 930         .ops = &fsl_xcvr_dai_ops,
 931         .playback = {
 932                 .stream_name = "CPU-Playback",
 933                 .channels_min = 1,
 934                 .channels_max = 32,
 935                 .rate_min = 32000,
 936                 .rate_max = 1536000,
 937                 .rates = SNDRV_PCM_RATE_KNOT,
 938                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
 939         },
 940         .capture = {
 941                 .stream_name = "CPU-Capture",
 942                 .channels_min = 1,
 943                 .channels_max = 32,
 944                 .rate_min = 32000,
 945                 .rate_max = 1536000,
 946                 .rates = SNDRV_PCM_RATE_KNOT,
 947                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
 948         },
 949 };
 950
 951 static const struct snd_soc_component_driver fsl_xcvr_comp = {
 952         .name                   = "fsl-xcvr-dai",
 953         .legacy_dai_naming      = 1,
 954 };
 955
 956 static const struct reg_default fsl_xcvr_reg_defaults[] = {
 957         { FSL_XCVR_VERSION,     0x00000000 },
 958         { FSL_XCVR_EXT_CTRL,    0xF8204040 },
 959         { FSL_XCVR_EXT_STATUS,  0x00000000 },
 960         { FSL_XCVR_EXT_IER0,    0x00000000 },
 961         { FSL_XCVR_EXT_IER1,    0x00000000 },
 962         { FSL_XCVR_EXT_ISR,     0x00000000 },
 963         { FSL_XCVR_EXT_ISR_SET, 0x00000000 },
 964         { FSL_XCVR_EXT_ISR_CLR, 0x00000000 },
 965         { FSL_XCVR_EXT_ISR_TOG, 0x00000000 },
 966         { FSL_XCVR_IER,         0x00000000 },
 967         { FSL_XCVR_ISR,         0x00000000 },
 968         { FSL_XCVR_ISR_SET,     0x00000000 },
 969         { FSL_XCVR_ISR_CLR,     0x00000000 },
 970         { FSL_XCVR_ISR_TOG,     0x00000000 },
 971         { FSL_XCVR_CLK_CTRL,    0x0000018F },
 972         { FSL_XCVR_RX_DPTH_CTRL,        0x00040CC1 },
 973         { FSL_XCVR_RX_DPTH_CTRL_SET,    0x00040CC1 },
 974         { FSL_XCVR_RX_DPTH_CTRL_CLR,    0x00040CC1 },
 975         { FSL_XCVR_RX_DPTH_CTRL_TOG,    0x00040CC1 },
 976         { FSL_XCVR_RX_DPTH_CNTR_CTRL,   0x00000000 },
 977         { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 },
 978         { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
 979         { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
 980         { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 },
 981         { FSL_XCVR_RX_DPTH_BCR,  0x00000000 },
 982         { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 },
 983         { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 },
 984         { FSL_XCVR_TX_DPTH_CTRL,        0x00000000 },
 985         { FSL_XCVR_TX_DPTH_CTRL_SET,    0x00000000 },
 986         { FSL_XCVR_TX_DPTH_CTRL_CLR,    0x00000000 },
 987         { FSL_XCVR_TX_DPTH_CTRL_TOG,    0x00000000 },
 988         { FSL_XCVR_TX_CS_DATA_0,        0x00000000 },
 989         { FSL_XCVR_TX_CS_DATA_1,        0x00000000 },
 990         { FSL_XCVR_TX_CS_DATA_2,        0x00000000 },
 991         { FSL_XCVR_TX_CS_DATA_3,        0x00000000 },
 992         { FSL_XCVR_TX_CS_DATA_4,        0x00000000 },
 993         { FSL_XCVR_TX_CS_DATA_5,        0x00000000 },
 994         { FSL_XCVR_TX_DPTH_CNTR_CTRL,   0x00000000 },
 995         { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 },
 996         { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
 997         { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
 998         { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 },
 999         { FSL_XCVR_TX_DPTH_BCR,  0x00000000 },
1000         { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 },
1001         { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 },
1002         { FSL_XCVR_DEBUG_REG_0,         0x00000000 },
1003         { FSL_XCVR_DEBUG_REG_1,         0x00000000 },
1004 };
1005
1006 static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
1007 {
1008         struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1009
1010         if (xcvr->soc_data->spdif_only)
1011                 if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) ||
1012                     reg > FSL_XCVR_TX_DPTH_BCRR)
1013                         return false;
1014         switch (reg) {
1015         case FSL_XCVR_VERSION:
1016         case FSL_XCVR_EXT_CTRL:
1017         case FSL_XCVR_EXT_STATUS:
1018         case FSL_XCVR_EXT_IER0:
1019         case FSL_XCVR_EXT_IER1:
1020         case FSL_XCVR_EXT_ISR:
1021         case FSL_XCVR_EXT_ISR_SET:
1022         case FSL_XCVR_EXT_ISR_CLR:
1023         case FSL_XCVR_EXT_ISR_TOG:
1024         case FSL_XCVR_IER:
1025         case FSL_XCVR_ISR:
1026         case FSL_XCVR_ISR_SET:
1027         case FSL_XCVR_ISR_CLR:
1028         case FSL_XCVR_ISR_TOG:
1029         case FSL_XCVR_PHY_AI_CTRL:
1030         case FSL_XCVR_PHY_AI_CTRL_SET:
1031         case FSL_XCVR_PHY_AI_CTRL_CLR:
1032         case FSL_XCVR_PHY_AI_CTRL_TOG:
1033         case FSL_XCVR_PHY_AI_RDATA:
1034         case FSL_XCVR_CLK_CTRL:
1035         case FSL_XCVR_RX_DPTH_CTRL:
1036         case FSL_XCVR_RX_DPTH_CTRL_SET:
1037         case FSL_XCVR_RX_DPTH_CTRL_CLR:
1038         case FSL_XCVR_RX_DPTH_CTRL_TOG:
1039         case FSL_XCVR_RX_CS_DATA_0:
1040         case FSL_XCVR_RX_CS_DATA_1:
1041         case FSL_XCVR_RX_CS_DATA_2:
1042         case FSL_XCVR_RX_CS_DATA_3:
1043         case FSL_XCVR_RX_CS_DATA_4:
1044         case FSL_XCVR_RX_CS_DATA_5:
1045         case FSL_XCVR_RX_DPTH_CNTR_CTRL:
1046         case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
1047         case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
1048         case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
1049         case FSL_XCVR_RX_DPTH_TSCR:
1050         case FSL_XCVR_RX_DPTH_BCR:
1051         case FSL_XCVR_RX_DPTH_BCTR:
1052         case FSL_XCVR_RX_DPTH_BCRR:
1053         case FSL_XCVR_TX_DPTH_CTRL:
1054         case FSL_XCVR_TX_DPTH_CTRL_SET:
1055         case FSL_XCVR_TX_DPTH_CTRL_CLR:
1056         case FSL_XCVR_TX_DPTH_CTRL_TOG:
1057         case FSL_XCVR_TX_CS_DATA_0:
1058         case FSL_XCVR_TX_CS_DATA_1:
1059         case FSL_XCVR_TX_CS_DATA_2:
1060         case FSL_XCVR_TX_CS_DATA_3:
1061         case FSL_XCVR_TX_CS_DATA_4:
1062         case FSL_XCVR_TX_CS_DATA_5:
1063         case FSL_XCVR_TX_DPTH_CNTR_CTRL:
1064         case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
1065         case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
1066         case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
1067         case FSL_XCVR_TX_DPTH_TSCR:
1068         case FSL_XCVR_TX_DPTH_BCR:
1069         case FSL_XCVR_TX_DPTH_BCTR:
1070         case FSL_XCVR_TX_DPTH_BCRR:
1071         case FSL_XCVR_DEBUG_REG_0:
1072         case FSL_XCVR_DEBUG_REG_1:
1073                 return true;
1074         default:
1075                 return false;
1076         }
1077 }
1078
1079 static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
1080 {
1081         struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1082
1083         if (xcvr->soc_data->spdif_only)
1084                 if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA)
1085                         return false;
1086         switch (reg) {
1087         case FSL_XCVR_EXT_CTRL:
1088         case FSL_XCVR_EXT_IER0:
1089         case FSL_XCVR_EXT_IER1:
1090         case FSL_XCVR_EXT_ISR:
1091         case FSL_XCVR_EXT_ISR_SET:
1092         case FSL_XCVR_EXT_ISR_CLR:
1093         case FSL_XCVR_EXT_ISR_TOG:
1094         case FSL_XCVR_IER:
1095         case FSL_XCVR_ISR_SET:
1096         case FSL_XCVR_ISR_CLR:
1097         case FSL_XCVR_ISR_TOG:
1098         case FSL_XCVR_PHY_AI_CTRL:
1099         case FSL_XCVR_PHY_AI_CTRL_SET:
1100         case FSL_XCVR_PHY_AI_CTRL_CLR:
1101         case FSL_XCVR_PHY_AI_CTRL_TOG:
1102         case FSL_XCVR_PHY_AI_WDATA:
1103         case FSL_XCVR_CLK_CTRL:
1104         case FSL_XCVR_RX_DPTH_CTRL:
1105         case FSL_XCVR_RX_DPTH_CTRL_SET:
1106         case FSL_XCVR_RX_DPTH_CTRL_CLR:
1107         case FSL_XCVR_RX_DPTH_CTRL_TOG:
1108         case FSL_XCVR_RX_DPTH_CNTR_CTRL:
1109         case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
1110         case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
1111         case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
1112         case FSL_XCVR_TX_DPTH_CTRL_SET:
1113         case FSL_XCVR_TX_DPTH_CTRL_CLR:
1114         case FSL_XCVR_TX_DPTH_CTRL_TOG:
1115         case FSL_XCVR_TX_CS_DATA_0:
1116         case FSL_XCVR_TX_CS_DATA_1:
1117         case FSL_XCVR_TX_CS_DATA_2:
1118         case FSL_XCVR_TX_CS_DATA_3:
1119         case FSL_XCVR_TX_CS_DATA_4:
1120         case FSL_XCVR_TX_CS_DATA_5:
1121         case FSL_XCVR_TX_DPTH_CNTR_CTRL:
1122         case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
1123         case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
1124         case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
1125                 return true;
1126         default:
1127                 return false;
1128         }
1129 }
1130
1131 static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg)
1132 {
1133         return fsl_xcvr_readable_reg(dev, reg);
1134 }
1135
1136 static const struct regmap_config fsl_xcvr_regmap_cfg = {
1137         .reg_bits = 32,
1138         .reg_stride = 4,
1139         .val_bits = 32,
1140         .max_register = FSL_XCVR_MAX_REG,
1141         .reg_defaults = fsl_xcvr_reg_defaults,
1142         .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults),
1143         .readable_reg = fsl_xcvr_readable_reg,
1144         .volatile_reg = fsl_xcvr_volatile_reg,
1145         .writeable_reg = fsl_xcvr_writeable_reg,
1146         .cache_type = REGCACHE_FLAT,
1147 };
1148
1149 static irqreturn_t irq0_isr(int irq, void *devid)
1150 {
1151         struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
1152         struct device *dev = &xcvr->pdev->dev;
1153         struct regmap *regmap = xcvr->regmap;
1154         void __iomem *reg_ctrl, *reg_buff;
1155         u32 isr, isr_clr = 0, val, i;
1156
1157         regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr);
1158
1159         if (isr & FSL_XCVR_IRQ_NEW_CS) {
1160                 dev_dbg(dev, "Received new CS block\n");
1161                 isr_clr |= FSL_XCVR_IRQ_NEW_CS;
1162                 if (!xcvr->soc_data->spdif_only) {
1163                         /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
1164                         regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1165                                            FSL_XCVR_EXT_CTRL_PAGE_MASK,
1166                                            FSL_XCVR_EXT_CTRL_PAGE(8));
1167
1168                         /* Find updated CS buffer */
1169                         reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0;
1170                         reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0;
1171                         memcpy_fromio(&val, reg_ctrl, sizeof(val));
1172                         if (!val) {
1173                                 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1;
1174                                 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1;
1175                                 memcpy_fromio(&val, reg_ctrl, sizeof(val));
1176                         }
1177
1178                         if (val) {
1179                                 /* copy CS buffer */
1180                                 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff,
1181                                               sizeof(xcvr->rx_iec958.status));
1182                                 for (i = 0; i < 6; i++) {
1183                                         val = *(u32 *)(xcvr->rx_iec958.status + i*4);
1184                                         *(u32 *)(xcvr->rx_iec958.status + i*4) =
1185                                                 bitrev32(val);
1186                                 }
1187                                 /* clear CS control register */
1188                                 memset_io(reg_ctrl, 0, sizeof(val));
1189                         }
1190                 }
1191         }
1192         if (isr & FSL_XCVR_IRQ_NEW_UD) {
1193                 dev_dbg(dev, "Received new UD block\n");
1194                 isr_clr |= FSL_XCVR_IRQ_NEW_UD;
1195         }
1196         if (isr & FSL_XCVR_IRQ_MUTE) {
1197                 dev_dbg(dev, "HW mute bit detected\n");
1198                 isr_clr |= FSL_XCVR_IRQ_MUTE;
1199         }
1200         if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) {
1201                 dev_dbg(dev, "RX/TX FIFO full/empty\n");
1202                 isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR;
1203         }
1204         if (isr & FSL_XCVR_IRQ_ARC_MODE) {
1205                 dev_dbg(dev, "CMDC SM falls out of eARC mode\n");
1206                 isr_clr |= FSL_XCVR_IRQ_ARC_MODE;
1207         }
1208         if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) {
1209                 dev_dbg(dev, "DMA read request\n");
1210                 isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ;
1211         }
1212         if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) {
1213                 dev_dbg(dev, "DMA write request\n");
1214                 isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ;
1215         }
1216
1217         if (isr_clr) {
1218                 regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr);
1219                 return IRQ_HANDLED;
1220         }
1221
1222         return IRQ_NONE;
1223 }
1224
1225 static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = {
1226         .fw_name = "/*(DEBLOBBED)*/",
1227 };
1228
1229 static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = {
1230         .spdif_only = true,
1231         .use_edma = true,
1232 };
1233
1234 static const struct of_device_id fsl_xcvr_dt_ids[] = {
1235         { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
1236         { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
1237         { /* sentinel */ }
1238 };
1239 MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids);
1240
1241 static int fsl_xcvr_probe(struct platform_device *pdev)
1242 {
1243         struct device *dev = &pdev->dev;
1244         struct fsl_xcvr *xcvr;
1245         struct resource *rx_res, *tx_res;
1246         void __iomem *regs;
1247         int ret, irq;
1248
1249         xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL);
1250         if (!xcvr)
1251                 return -ENOMEM;
1252
1253         xcvr->pdev = pdev;
1254         xcvr->soc_data = of_device_get_match_data(&pdev->dev);
1255
1256         xcvr->ipg_clk = devm_clk_get(dev, "ipg");
1257         if (IS_ERR(xcvr->ipg_clk)) {
1258                 dev_err(dev, "failed to get ipg clock\n");
1259                 return PTR_ERR(xcvr->ipg_clk);
1260         }
1261
1262         xcvr->phy_clk = devm_clk_get(dev, "phy");
1263         if (IS_ERR(xcvr->phy_clk)) {
1264                 dev_err(dev, "failed to get phy clock\n");
1265                 return PTR_ERR(xcvr->phy_clk);
1266         }
1267
1268         xcvr->spba_clk = devm_clk_get(dev, "spba");
1269         if (IS_ERR(xcvr->spba_clk)) {
1270                 dev_err(dev, "failed to get spba clock\n");
1271                 return PTR_ERR(xcvr->spba_clk);
1272         }
1273
1274         xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg");
1275         if (IS_ERR(xcvr->pll_ipg_clk)) {
1276                 dev_err(dev, "failed to get pll_ipg clock\n");
1277                 return PTR_ERR(xcvr->pll_ipg_clk);
1278         }
1279
1280         xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram");
1281         if (IS_ERR(xcvr->ram_addr))
1282                 return PTR_ERR(xcvr->ram_addr);
1283
1284         regs = devm_platform_ioremap_resource_byname(pdev, "regs");
1285         if (IS_ERR(regs))
1286                 return PTR_ERR(regs);
1287
1288         xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs,
1289                                                  &fsl_xcvr_regmap_cfg);
1290         if (IS_ERR(xcvr->regmap)) {
1291                 dev_err(dev, "failed to init XCVR regmap: %ld\n",
1292                         PTR_ERR(xcvr->regmap));
1293                 return PTR_ERR(xcvr->regmap);
1294         }
1295
1296         xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
1297         if (IS_ERR(xcvr->reset)) {
1298                 dev_err(dev, "failed to get XCVR reset control\n");
1299                 return PTR_ERR(xcvr->reset);
1300         }
1301
1302         /* get IRQs */
1303         irq = platform_get_irq(pdev, 0);
1304         if (irq < 0)
1305                 return irq;
1306
1307         ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
1308         if (ret) {
1309                 dev_err(dev, "failed to claim IRQ0: %i\n", ret);
1310                 return ret;
1311         }
1312
1313         rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo");
1314         tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo");
1315         if (!rx_res || !tx_res) {
1316                 dev_err(dev, "could not find rxfifo or txfifo resource\n");
1317                 return -EINVAL;
1318         }
1319         xcvr->dma_prms_rx.chan_name = "rx";
1320         xcvr->dma_prms_tx.chan_name = "tx";
1321         xcvr->dma_prms_rx.addr = rx_res->start;
1322         xcvr->dma_prms_tx.addr = tx_res->start;
1323         xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX;
1324         xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX;
1325
1326         platform_set_drvdata(pdev, xcvr);
1327         pm_runtime_enable(dev);
1328         regcache_cache_only(xcvr->regmap, true);
1329
1330         /*
1331          * Register platform component before registering cpu dai for there
1332          * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1333          */
1334         ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1335         if (ret) {
1336                 pm_runtime_disable(dev);
1337                 dev_err(dev, "failed to pcm register\n");
1338                 return ret;
1339         }
1340
1341         ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp,
1342                                               &fsl_xcvr_dai, 1);
1343         if (ret) {
1344                 pm_runtime_disable(dev);
1345                 dev_err(dev, "failed to register component %s\n",
1346                         fsl_xcvr_comp.name);
1347         }
1348
1349         return ret;
1350 }
1351
1352 static void fsl_xcvr_remove(struct platform_device *pdev)
1353 {
1354         pm_runtime_disable(&pdev->dev);
1355 }
1356
1357 static __maybe_unused int fsl_xcvr_runtime_suspend(struct device *dev)
1358 {
1359         struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1360         int ret;
1361
1362         /*
1363          * Clear interrupts, when streams starts or resumes after
1364          * suspend, interrupts are enabled in prepare(), so no need
1365          * to enable interrupts in resume().
1366          */
1367         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
1368                                  FSL_XCVR_IRQ_EARC_ALL, 0);
1369         if (ret < 0)
1370                 dev_err(dev, "Failed to clear IER0: %d\n", ret);
1371
1372         if (!xcvr->soc_data->spdif_only) {
1373                 /* Assert M0+ reset */
1374                 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1375                                         FSL_XCVR_EXT_CTRL_CORE_RESET,
1376                                         FSL_XCVR_EXT_CTRL_CORE_RESET);
1377                 if (ret < 0)
1378                         dev_err(dev, "Failed to assert M0+ core: %d\n", ret);
1379         }
1380
1381         regcache_cache_only(xcvr->regmap, true);
1382
1383         clk_disable_unprepare(xcvr->spba_clk);
1384         clk_disable_unprepare(xcvr->phy_clk);
1385         clk_disable_unprepare(xcvr->pll_ipg_clk);
1386         clk_disable_unprepare(xcvr->ipg_clk);
1387
1388         return 0;
1389 }
1390
1391 static __maybe_unused int fsl_xcvr_runtime_resume(struct device *dev)
1392 {
1393         struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1394         int ret;
1395
1396         ret = reset_control_assert(xcvr->reset);
1397         if (ret < 0) {
1398                 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret);
1399                 return ret;
1400         }
1401
1402         ret = clk_prepare_enable(xcvr->ipg_clk);
1403         if (ret) {
1404                 dev_err(dev, "failed to start IPG clock.\n");
1405                 return ret;
1406         }
1407
1408         ret = clk_prepare_enable(xcvr->pll_ipg_clk);
1409         if (ret) {
1410                 dev_err(dev, "failed to start PLL IPG clock.\n");
1411                 goto stop_ipg_clk;
1412         }
1413
1414         ret = clk_prepare_enable(xcvr->phy_clk);
1415         if (ret) {
1416                 dev_err(dev, "failed to start PHY clock: %d\n", ret);
1417                 goto stop_pll_ipg_clk;
1418         }
1419
1420         ret = clk_prepare_enable(xcvr->spba_clk);
1421         if (ret) {
1422                 dev_err(dev, "failed to start SPBA clock.\n");
1423                 goto stop_phy_clk;
1424         }
1425
1426         regcache_cache_only(xcvr->regmap, false);
1427         regcache_mark_dirty(xcvr->regmap);
1428         ret = regcache_sync(xcvr->regmap);
1429
1430         if (ret) {
1431                 dev_err(dev, "failed to sync regcache.\n");
1432                 goto stop_spba_clk;
1433         }
1434
1435         if (xcvr->soc_data->spdif_only)
1436                 return 0;
1437
1438         ret = reset_control_deassert(xcvr->reset);
1439         if (ret) {
1440                 dev_err(dev, "failed to deassert M0+ reset.\n");
1441                 goto stop_spba_clk;
1442         }
1443
1444         ret = fsl_xcvr_load_firmware(xcvr);
1445         if (ret) {
1446                 dev_err(dev, "failed to load firmware.\n");
1447                 goto stop_spba_clk;
1448         }
1449
1450         /* Release M0+ reset */
1451         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1452                                  FSL_XCVR_EXT_CTRL_CORE_RESET, 0);
1453         if (ret < 0) {
1454                 dev_err(dev, "M0+ core release failed: %d\n", ret);
1455                 goto stop_spba_clk;
1456         }
1457
1458         /* Let M0+ core complete firmware initialization */
1459         msleep(50);
1460
1461         return 0;
1462
1463 stop_spba_clk:
1464         clk_disable_unprepare(xcvr->spba_clk);
1465 stop_phy_clk:
1466         clk_disable_unprepare(xcvr->phy_clk);
1467 stop_pll_ipg_clk:
1468         clk_disable_unprepare(xcvr->pll_ipg_clk);
1469 stop_ipg_clk:
1470         clk_disable_unprepare(xcvr->ipg_clk);
1471
1472         return ret;
1473 }
1474
1475 static const struct dev_pm_ops fsl_xcvr_pm_ops = {
1476         SET_RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend,
1477                            fsl_xcvr_runtime_resume,
1478                            NULL)
1479         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1480                                 pm_runtime_force_resume)
1481 };
1482
1483 static struct platform_driver fsl_xcvr_driver = {
1484         .probe = fsl_xcvr_probe,
1485         .driver = {
1486                 .name = "fsl,imx8mp-audio-xcvr",
1487                 .pm = &fsl_xcvr_pm_ops,
1488                 .of_match_table = fsl_xcvr_dt_ids,
1489         },
1490         .remove_new = fsl_xcvr_remove,
1491 };
1492 module_platform_driver(fsl_xcvr_driver);
1493
1494 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>");
1495 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver");
1496 MODULE_LICENSE("GPL v2");